TWI564981B - Method of manufacturing semiconductor devices - Google Patents

Description

Method of manufacturing a semiconductor device

The present invention is generally directed to the fabrication of semiconductor devices and methods for managing such fabrication. More specifically, the present invention relates to the possibility of improving the semiconductor device obtained by the manufacturing process to function as specified after completion.

The process used to fabricate semiconductor devices involves a number of steps that are highly complex and extremely expensive. The large investment required in infrastructure, materials, and time helps to carefully control the yield of semiconductor manufacturing processes. It is desirable to identify process variations and material defects early in the fabrication process when problems are ameliorated by redoing or by selectively discarding a portion or all of a semiconductor substrate or group of substrates.

Defects in the semiconductor substrate are often detected by means of optical inspection. Other forms of measurement and inspection can also be used to identify defects. Examples of techniques useful for identifying defects in process variations include, but are not limited to, multiple wavelengths of light and multiple resolutions, ellipsometry, reflectometry, diffraction, photoacoustic techniques, electron beam inspection, scanning Electron microscopy, atomic force microscopy, infrared microscopy, UV microscopy, interference techniques, and optical inspection and/or detection under visible light microscopy.

By definition, the term "defect" will be used to broadly refer to any feature or characteristic portion of an undesired semiconductor substrate. If a feature or characteristic portion lowers a semiconductor device or a group of semiconductor devices, the feature portion or special The feature or characteristic portion of one or more of the substrates is undesired. This feature or characteristic is also undesirable where the feature or characteristic portion tends to reduce the yield of the semiconductor fabrication process. Yield is defined as the ratio of the acceptable quality of the semiconductor to the number of semiconductor devices that begin. Based on these definitions, in some cases and not otherwise, a feature or feature may be a defect. At the feature or characteristic portion (eg, contaminants, particulates, dose/exposure exposure errors, defocus errors, layer thickness variations, or cracks) by causing one or more of the one or more semiconductor devices to appear unreliable or unworkable In the case where the yield of the semiconductor process is lowered, the feature or characteristic portion will be considered as a defect. The feature or characteristic portion is not considered a defect in the case where the feature or characteristic portion does not adversely affect the yield of the semiconductor manufacturing process or the negative effect on the yield is acceptable.

Those skilled in the art will appreciate that careful and continuous monitoring of all types of features and characteristics can be performed on features and features that are defects, and that are not defective but under changing conditions (ie, different application or processing conditions) It is important to distinguish between the feature and the feature of the defect. In addition to monitoring the semiconductor manufacturing process, careful tracking of the features and characteristics and measurement of the yield are used to inform the design and specifications of the semiconductor device.

One of the problems encountered in the monitoring features and characteristics is that it is difficult to spatially align defects that occur or occur early in the semiconductor fabrication process with patterns or semiconductor devices that may later appear on the semiconductor device in the process. It is also desirable to ensure that an early defect can be accurately located relative to a particular semiconductor device in which the feature or feature portion is present. (several) patterns on the pair of substrates It is particularly difficult to compare or verify the feature or characteristic portion previously present with respect to the (several) pattern on the substrate. Moreover, any error introduced in the locating feature and the characterization portion can be a composite type in which the semiconductor device being fabricated is relatively small. In such cases, the defect may be incorrectly associated with a semiconductor device or devices in which the defect is not present. Process engineers responsible for managing and monitoring semiconductor manufacturing processes on a number of occasions will often discard excessive amounts of semiconductor devices to avoid accidentally containing or identifying fully processed semiconductor devices that may be defective. The location of a defect can be determined and the semiconductor device can be accurately identified, and only such semiconductor devices affected by the defect are critical to improving the yield of the semiconductor fabrication process.

By properly identifying and tracking features or features and by achieving accurate positioning of such features or features, semiconductor devices that are more likely to function and have lower cost at runtime can be created.

Accordingly, there is a need for methods that can properly correlate one of the defects of the semiconductor substrate with the correct location of the defect on a semiconductor substrate. It is also advantageous to ensure that a defect is properly associated with a semiconductor device or devices that are affected by the defect.

One method of fabricating a high quality and high profit semiconductor device involves ensuring that all defects identified on a substrate have their exact location. This embodiment of the invention begins by inspecting an unpatterned substrate to identify one or more defects on the substrate, if any defects are present. Record the position and orientation of each defect found on the substrate. Later, perform the subsequent steps on the substrate Steps. Generally speaking, this results in the formation of some form of pattern on the substrate. The currently patterned substrate and the identified defects, if any, are examined and the location and orientation of the defects are recorded. In view of the fact that at least a portion of the defects identified on the unpatterned substrate will be found on the currently patterned substrate, the defects found on the unpatterned substrate can be spatially aligned with the defects found on the current patterned substrate. This alignment produces a positional transition that can be used to modify the location of the recorded defect found on either of the unpatterned or patterned substrates. Figure 4 is a schematic illustration of how the respective patterns of defects can be aligned using the resulting positional transformation identified as one of the offset in the X direction, one offset in the width direction, and the rotational offset Theta.

Once accurate alignment occurs, process control decisions can be made more accurately. Subsequently, semiconductor fabrication processes can be operated at higher yields, and such semiconductor fabrication processes are more profitable.

In the following detailed description of the invention, reference to the drawings In the drawings, like numerals are used to refer to the These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the invention. Therefore, the following detailed description is not to be taken in a

Steps to identify defects on both patterned and unpatterned substrates The alignment of defects identified on the unpatterned substrate with semiconductor devices that are later formed on the same substrate. Figure 1 schematically illustrates a type of inspection or metrology system that can be used to identify defects on a substrate S. The optical inspection system 10 illustrated in FIG. 1 is similar to the inspection system of the type described in U.S. Patent No. 6,826,298, the entire disclosure of which is incorporated herein.

The optical inspection system 10 includes a camera 14 and a illuminator 12 that are constructed and arranged to capture an image or images of a substrate S. Light from illuminator 12 is directed along path 16 to one of the optical axes of camera 14. It should be noted that the path 16 in the illustration of Figure 1 is in the fiber. However, the radiation from illuminator 12 can be directed onto an optical axis using a type of mirror or other optical component (not shown) that is commonly used and known to those skilled in the art. The beam splitter 18 couples the light from the illuminator 12 to one of the optical axes of the camera 14 such that light from the illuminator 12 is incident on the substrate S and is incident substantially normal. Light returns from substrate S to a suitable sensor (not shown) of camera 14, which captures an image of substrate S. It should be noted that camera 14 can be of any useful configuration and can include any useful type of sensor, including sensors that capture information that can be referred to as an image but that is invisible in the traditional sense that the photo is visible. For example, camera 14 can be an area scan camera, a line of scan cameras, or a point sensor array. Suitable sensors may include, but are not limited to, various types of charge coupled devices (CCDs), complementary metal oxide semiconductor sensors (CMOS), enhanced charge coupled device (ICCD) sensors, photomultiplier tubes (PMT) ) and photodiode sensors.

In addition to the illuminator 12, an additional or alternative illuminator 13 can be provided. In general, illuminator 12 is used when it is generally referred to as brightfield illumination. The illuminator 13 that directs light at any useful wavelength to the substrate S at a low glancing angle that does not reflect normal along the optical axis of the camera 14 is suitable for what is commonly referred to as dark field illumination.

In some embodiments, the concatenation of all images of a substrate S may be analyzed or evaluated on a per-image basis, on an area basis (ie, as an image group), such as on a pixel-by-pixel basis of a group of pixels. Analyze or evaluate the image of the substrate S on the basis. In one embodiment, an image of an entire substrate S can be stitched together to form a large image of the entire substrate S. In another embodiment, images and the like may be recorded together in a data structure representing one of the entire substrates S without stitching the individual images together. In such later embodiments, this data structure is often referred to as a wafer. In addition to arranging the image of the entire substrate S relative to each other, additional information about the substrate S can be recorded. Examples of this type of information include locations where one or more defects have been identified on the substrate. Other useful information recorded in the wafer map includes metric data such as layer thickness or critical dimension. Those skilled in the art will readily appreciate the nature and extent of the information that can be stored in a wafer map.

2A and 2B schematically illustrate two wafer diagram representations of a substrate S. In Figure 2a, substrate S is a semiconductor wafer having an alignment structure referred to as a flat portion 20 formed in an edge. The flat portion 20 is used by an automated system to properly align the substrate S with an inspection, metrology or processing system. Figure 2b shows the flatness used for drawing with Figure 2a A substrate S of the notch 22 of the same purpose. Each of the substrates depicted in Figures 2a and 2b is substantially unpatterned because they do not form any form of structure thereon. However, it can be seen that each of the substrates S illustrated in Figures 2a and 2b has a plurality of defects D thereon. As noted above, such defects D may be fragments, cracks, particles, stains, scratches, or other undesirable features formed on or deposited on the surface of substrate S.

The unpatterned substrate S, such as the substrate S depicted in Figures 2a and 2b, is typically inspected and/or analyzed prior to processing. It is this defect D that is shown in the inspection and analysis identification pattern for identification. The unpatterned substrate S will experience if the substrate S has an acceptable quality, ie, the nature, size, density, and/or total number of defects D found on the substrate S are acceptable to the process engineer responsible for managing the semiconductor fabrication process. Subsequent semiconductor manufacturing processes. Such processes may include, but are not limited to, etching, grinding, depositing, rinsing, inspection, metrology, and the like. In addition to facilitating the progression of an unpatterned substrate S toward the fully patterned substrate S, the various steps in the fabrication process can introduce additional defects. Therefore, it is common practice to inspect or analyze the substrate S multiple times during the manufacturing process.

Figure 3 illustrates a substrate S that has been at least partially patterned. As can be seen, individual semiconductor devices 26 have been formed on substrate S. The wafer pattern representation of the substrate S in FIG. 3 also contains information on the defect D identified on the substrate S. It has been found that, in general, at least a portion of the defect D found on the patterned substrate S will correspond to the defect D found on the unpatterned substrate, for example, as depicted in Figures 2a and 2b. However, due to inherent uncertainty Qualitatively relates to the location of the defect D found on the unpatterned wafer, so it is not desirable to simply serially combine the information obtained from the unpatterned substrate S with the information obtained from the patterned substrate S into a single wafer map. In practice, it is preferable to match the pattern formed by the defect D found on the unpatterned substrate S with the pattern of the defect D found on the patterned substrate S. In doing so, positional conversion can be obtained that can be used to align images and/or data from unpatterned substrates with images and/or data from unpatterned substrates. In describing the relative evaluation of patterned and unpatterned substrates, it is important to keep in mind the comparison of the same substrate at multiple stages in the semiconductor fabrication process. In other words, the defects identified on the unpatterned substrate S are aligned with the defects found thereon after the same substrate S has been patterned, and the defects are essentially the same defects. It should be noted that the term "patterning" as used herein has a broad meaning and refers to any process step but can alter the structure of substrate S.

The alignment of the defect D identified on an unpatterned substrate S with the defect D found on the same substrate S in a later patterned state can be accomplished using any suitable intensity or feature-based alignment or registration algorithm . Some examples include, but are not limited to, spatial pattern matching algorithms (eg, RANSAC) and frequency domain pattern matching algorithms (eg, phase correlation methods). Although vector and other notation can also be used, positional translation has generally been obtained in the X, Y, and θ notation, and the previously assigned position of the defect D identified on the unpatterned substrate S can be modified to make the defects D and slightly The same defect D alignment visible on the patterned substrate S in the later stage. In other words, the defects identified on the unpatterned substrate S are aligned with the defects themselves after the intermediate process steps have been performed on the substrate. Usually by modifying the wafer pattern representing the unpatterned substrate S Data alignment is performed by the identified defect location. Although the data in the wafer pattern representing the patterned substrate S can also be modified, it is generally necessary to have fewer steps to modify the wafer pattern representing the unpatterned substrate S.

It must be noted that many of the defects identified on the unpatterned substrate S may not be visible after the substrate has been patterned or otherwise subjected to subsequent processing steps. In an embodiment, the process engineer can identify a subset of defects D found on the unpatterned substrate S that will be used for the reference point of the alignment purpose. The process of identifying or selecting may be performed according to any of a number of criteria including, but not limited to, the location of the defect, its size, aspect ratio, or any other suitable criteria, bearing in mind that such criteria will generally pertain to processing steps that have been performed at a later time. After that, the possibility of the effect appearing on the substrate S. In other embodiments, the alignment or registration algorithm will use all identified defects from the patterned and unpatterned substrates for alignment purposes. In embodiments where all identified defects are used for alignment purposes, certain restrictions may be placed on the algorithm to prevent incorrect alignment. For example, where the maximum expected offset between defect patterns is 200 μ, positional shifts requiring a displacement greater than 200 μ can be omitted in the feasible solution set.

While the alignment as described above can be performed repeatedly, it is generally the case that only one alignment between the defect pattern that has been identified on the unpatterned substrate and the defect pattern that has been identified on the patterned substrate is performed.

In addition to aligning the defect patterns found on the unpatterned and patterned substrates, the steps of the present invention can also be used to identify variations between inspection systems. For example, comparing a wafer map identifying the location of a defect on a patterned or unpatterned substrate to a wafer of the same substrate that is intended to identify the same defect location on the substrate The graph identifies the differences between the respective inspection systems. This is especially useful when different inspection systems are used for different points in the manufacturing process of semiconductor devices. In the respective steps of the manufacturing process, where the same inspection system is used on the substrate, the image of the substrate will experience the same optical aberrations and distortions. Therefore, it is usually only necessary to align. However, in the case of inspection systems using different manufacturers or inspection systems using different models, the maps can be formed separately based on different types and degrees of optical aberrations and distortions. In this case, alignment can occur between the wafer maps produced by the respective inspection systems. Furthermore, this alignment can be performed between defect patterns found on unpatterned substrates and patterned substrates, or between defect patterns found on respective patterned substrates.

Once the alignment has been completed, the process engineer responsible for managing the fabrication of the semiconductor device on a substrate S can more accurately evaluate the quality of the substrate S and the semiconductor device 26 formed thereon. Further, better alignment allows yield management systems (YMS), automatic defect classification systems (ADCs), and electronic data analysis (EDA) systems to more accurately identify defects, identify process variations, determine root causes, and modify process schedules. The board is reworked and the pass/fail status of the individual semiconductor device, the semiconductor device on the portion of the substrate, and all of the semiconductor devices on the substrate are determined. As a result, the output of the semiconductor fabrication process or system utilizing the present invention can have higher yields of higher quality and is more profitable.

in conclusion

While various examples are provided above, the invention is not limited to the details of the examples. Although specific embodiments of the invention have been illustrated and described herein, However, those skilled in the art will appreciate that any configuration that is calculated to achieve the same objectives may be substituted for the particular embodiments shown. Many modifications of the invention will be apparent to those skilled in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is apparent that the invention is intended to be limited only by the scope of the following claims.

10‧‧‧Optical inspection system

12‧‧‧ illuminators

13‧‧‧ illuminator

14‧‧‧ camera

16‧‧‧ Path

S‧‧‧Substrate

18‧‧‧ Spectroscope

20‧‧‧ Flat Department

22‧‧‧ gap

D‧‧‧ Defects

26‧‧‧Semiconductor device

X, Y‧‧‧ position offset

Θ‧‧‧ angular offset

Figure 1 is a schematic illustration of an optical system that can be used as part of the present invention.

Figure 2a is a schematic view of a substrate having one of the alignment features referred to as a flat portion formed in the substrate.

Figure 2b is a schematic view of a substrate having one of the alignment features, a notch formed in the substrate.

Figure 3 is a schematic view of a substrate on which a pattern is formed.

Figure 4 is a schematic illustration of the positional transition between patterns of defects identified on a substrate under different process steps.

10‧‧‧Optical inspection system

12‧‧‧ illuminators

13‧‧‧ illuminator

14‧‧‧ camera

16‧‧‧ Path

S‧‧‧Substrate

18‧‧‧ Spectroscope

Claims (12)

A method of fabricating a semiconductor device, the method comprising: inspecting an unpatterned substrate to identify any defects in the presence of one or more defects; recording at least a portion of any identified defects found on the unpatterned substrate Positioning one of the substrates; performing a processing step on the substrate to form a currently patterned substrate, wherein at least a portion of the currently patterned substrate has a pattern thereon; inspecting the currently patterned substrate to Identifying any defect when one or more defects are present on the patterned substrate, recording one of each of at least a portion of any identified defects found on the currently patterned substrate; and on the unpatterned substrate The at least a portion of any identified defects identified to define a spatial pattern aligned with a spatial pattern defined by at least a portion of any identified defects found on the currently patterned substrate, the identified defect The position of the respective spatial patterns aligned with the defects identified on the unpatterned substrate and formed at the mesh Providing a conversion between the position of at least a portion of the patterned substrate of one pattern. A method of fabricating a semiconductor device according to claim 1, the method comprising: providing an x, y position offset and an angular offset to define a position conversion for subsequent formation on the substrate At least part of the formation The position of the sub-pattern identifies the location of one of the identified defects on the unpatterned substrate. The method of claim 2, further comprising: modifying a predefined process step, and subsequently applying the modified process step to the semiconductor substrate, the modification of the predefined process step being based at least in part on the alignment step. The method of claim 2, further comprising: modifying a predefined process step, and subsequently applying the modified process step to at least one semiconductor device on the semiconductor substrate, the modification of the predefined process step Based at least in part on the alignment step. The method of claim 2, further comprising: omitting one of the semiconductor devices formed on a semiconductor substrate in an additional process based at least in part on the aligning step. The method of claim 2, further comprising, after the aligning step, performing at least one processing step on identifying at least one of the plurality of semiconductor devices in the aligning step. A method of fabricating a semiconductor device, wherein one of the fabrication methods is obtained, at least in part, by aligning identified defects identified on an unpatterned substrate with defects found on the same, subsequently patterned substrate output. The method of claim 7, wherein the aligning step is used at least in part to omit a number of semiconductor devices in a further process, one of the semiconductor devices balancing undergoing subsequent processing, the subsequent processing being omitted from the further processing Semiconductor devices have a generally higher perceived product quality. The method of claim 7, wherein the aligning step is used at least in part to subject a plurality of semiconductor devices to further processing, the further processed semiconductor devices having approximately the same as the semiconductor devices omitted from further processing Perceived quality. A method of fabricating a semiconductor device, the method comprising: identifying a defect on a substrate via an optical inspection in a first stage of a fabrication process and in a subsequent second phase of the fabrication process; The defects found on the substrate in the first and second stages are represented as respective wafer maps; the defects of the respective wafer maps are aligned to ensure proper defect alignment and identification, wherein the alignment step Including applying a positional shifting operation whereby unless the identified defect in the wafer map of the first stage is offset, the identified defect in the wafer map for the second stage exceeds an expected offset value Otherwise, the identified defect in the wafer map for the first stage is designated to align the identified defect in the wafer map for the second stage. A method of fabricating a semiconductor device according to claim 10, the method comprising: identifying a defect identified in a wafer pattern representing an unpatterned substrate and identifying a wafer pattern on a patterned substrate The defects are aligned and the two wafer patterns are derived from the same substrate. A method of fabricating a semiconductor device according to claim 11 of the patent application, the method comprising: A defect identified in a wafer pattern representing one of the unpatterned substrates is aligned with a defect identified in a wafer pattern representing one of the patterned substrates, the two wafer patterns being derived from the same substrate, the pair The quasi-step further identifies a position of each alignment defect relative to the pattern formed on the patterned substrate.