TWI557860B - Semiconductor package and method of fabricating the same - Google Patents
Semiconductor package and method of fabricating the same Download PDFInfo
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- TWI557860B TWI557860B TW103123435A TW103123435A TWI557860B TW I557860 B TWI557860 B TW I557860B TW 103123435 A TW103123435 A TW 103123435A TW 103123435 A TW103123435 A TW 103123435A TW I557860 B TWI557860 B TW I557860B
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- Prior art keywords
- layer
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- semiconductor package
- encapsulation layer
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- 239000004065 semiconductor Substances 0.000 title claims description 129
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000010410 layer Substances 0.000 claims description 124
- 238000005538 encapsulation Methods 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 13
- 239000011241 protective layer Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 238000000465 moulding Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 4
- 238000006073 displacement reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000007654 immersion Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000002335 surface treatment layer Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
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- 230000008859 change Effects 0.000 description 1
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- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本發明係有關一種封裝製程，特別是關於一種能避免雷射鑽孔之問題的半導體封裝件及其製法。 The present invention relates to a packaging process, and more particularly to a semiconductor package capable of avoiding the problem of laser drilling and a method of fabricating the same.
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂開發出不同的立體封裝技術，例如，扇出式封裝堆疊(Fan Out Package on package，簡稱FO PoP)等，以配合各種晶片上大幅增加之輸入/出埠數量，進而將不同功能之積體電路整合於單一封裝結構，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。 With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, and in order to improve electrical functions and save packaging space, different stereo packaging technologies have been developed, for example, fan-out package stacking. (Fan Out Package on package, referred to as FO PoP), etc., in order to match the increased number of input/outputs on various wafers, and then integrate the integrated circuits of different functions into a single package structure, which can be used as a system package ( SiP) heterogeneous integration features, which can be used to integrate various electronic components, such as memory, central processing unit, graphics processor, image application processor, etc., by stacking design, suitable for thin and light electronic products. .
第1A至1F圖係為習知封裝堆疊裝置之其中一半導體封裝件1之製法之剖面示意圖。 1A to 1F are schematic cross-sectional views showing a method of manufacturing a semiconductor package 1 of a conventional package stacking device.
如第1A圖所示，設置一如晶片之半導體元件10於一承載件11之熱化離形層110上，再形成一封裝層13於該 熱化離形層110上以包覆該半導體元件10。 As shown in FIG. 1A, a semiconductor component 10 such as a wafer is disposed on the thermal release layer 110 of a carrier 11 to form an encapsulation layer 13 thereon. The release layer 110 is heated to coat the semiconductor element 10.
如第1B圖所示，將具有銅箔120之另一承載件12設於該封裝層13上。 As shown in FIG. 1B, another carrier 12 having a copper foil 120 is disposed on the encapsulation layer 13.
如第1C圖所示，移除該承載件11及其熱化離形層110，以露出該半導體元件10與封裝層13。 As shown in FIG. 1C, the carrier 11 and its thermal release layer 110 are removed to expose the semiconductor component 10 and the encapsulation layer 13.
如第1D圖所示，以雷射方式形成複數開口130於該半導體元件10周邊之封裝層13上。 As shown in FIG. 1D, a plurality of openings 130 are formed in a laser pattern on the encapsulation layer 13 around the semiconductor device 10.
如第1E圖所示，藉由該銅箔120電鍍導電材料於該些開口130中，以形成導電柱14，再於該封裝層13上形成複數線路重佈層(redistribution layer，簡稱RDL)15，以令該線路重佈層15電性連接該導電柱14與該半導體元件10之電極墊100。 As shown in FIG. 1E, the copper foil 120 is plated with a conductive material in the openings 130 to form the conductive pillars 14, and a plurality of redistribution layers (RDLs) 15 are formed on the package layer 13. The circuit redistribution layer 15 is electrically connected to the conductive pillar 14 and the electrode pad 100 of the semiconductor component 10.
如第1F圖所示，移除該另一承載件12，再利用該銅箔120進行圖案化線路製程，以形成一線路結構16，之後再進行切單製程。 As shown in FIG. 1F, the other carrier 12 is removed, and the copper foil 120 is used to perform a patterned circuit process to form a wiring structure 16, and then a singulation process is performed.
惟，習知半導體封裝件1之製法中，因以雷射方式形成複數開口130，故雷射之熱效應會造成該開口130之壁面極為粗糙(如第1C圖所示之粗糙表面130a)，以致於當電鍍製作該導電柱14時，電鍍品質不佳，因而造成良率過低及產品可靠度不佳等問題。 However, in the manufacturing method of the conventional semiconductor package 1, since the plurality of openings 130 are formed by laser, the thermal effect of the laser causes the wall surface of the opening 130 to be extremely rough (such as the rough surface 130a shown in FIG. 1C). When the conductive pillars 14 are electroplated, the plating quality is not good, which causes problems such as low yield and poor product reliability.
再者，雖可使用蝕刻方式形成該開口130以避免發生該粗糙表面130a之狀況，但若要形成直徑100um以上的開口130，蝕刻方式之製程時間過長，因而會大幅增加成本。 Further, although the opening 130 may be formed by etching to avoid the occurrence of the rough surface 130a, if the opening 130 having a diameter of 100 μm or more is formed, the etching time of the etching method is too long, and the cost is greatly increased.
另外，該熱化離形層110具有撓性，且其熱膨脹係數 (Coefficient of thermal expansion,CTE)與該封裝層13注入封裝用之模具時之膠體流動所產生之側推力，將一同影響該半導體元件10固定之精度，亦即容易使半導體元件10產生偏移，致使該半導體元件10未置於該熱化離形層之預定位置上。故而，該線路重佈層15與該半導體元件10之電極墊100間的對位將產生偏移，當該承載件11之尺寸越大時，各該半導體元件10間之位置公差亦隨之加大，而當偏移公差過大時，將使該線路重佈層15無法與該電極墊100連接，亦即對該線路重佈層15與該半導體元件10間之電性連接造成極大影響，因而造成良率過低及產品可靠度不佳等問題。 In addition, the thermalized release layer 110 has flexibility and its coefficient of thermal expansion The coefficient of thermal expansion (CTE) and the side thrust generated by the gel flow when the encapsulating layer 13 is injected into the mold for packaging will affect the accuracy of fixing the semiconductor element 10, that is, the semiconductor element 10 is easily displaced. The semiconductor component 10 is caused not to be placed at a predetermined position of the thermal release layer. Therefore, the alignment between the circuit redistribution layer 15 and the electrode pad 100 of the semiconductor device 10 will be offset. When the size of the carrier member 11 is larger, the positional tolerance between the semiconductor elements 10 is also increased. If the offset tolerance is too large, the circuit redistribution layer 15 cannot be connected to the electrode pad 100, that is, the electrical connection between the circuit redistribution layer 15 and the semiconductor component 10 is greatly affected. Problems such as low yield and poor product reliability.
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明提供一種半導體封裝件，係包括：至少一半導體元件；一具有相對之第一表面與第二表面的封裝層，係包覆該半導體元件，該封裝層係具有至少一開口及至少一開槽，該開口係連通該第一及第二表面，該開槽係連通該第二表面並呈現絕緣狀態，其中，該開口之側面與該開槽之側面係呈平滑表面；以及線路層，係設於該封裝層之第二表面上，且該線路層具有形成於該開口中之導電體。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a semiconductor package comprising: at least one semiconductor component; and an encapsulation layer having a first surface and a second surface opposite to cover the semiconductor component, the encapsulation layer Having at least one opening and at least one slot communicating with the first and second surfaces, the slot communicating with the second surface and exhibiting an insulating state, wherein a side of the opening and a side of the slot are a smooth surface; and a circuit layer disposed on the second surface of the encapsulation layer, and the circuit layer has an electrical conductor formed in the opening.
本發明復提供一種半導體封裝件之製法，係包括：提供一設有至少一半導體元件之承載件；形成一具有至少一 開口的封裝層於該承載件上，使該封裝層包覆該半導體元件，且該封裝層與該開口係一同製成，該封裝層係具有相對之第一表面與第二表面，該第一表面係結合該承載件，該開口係連通該第一及第二表面，其中，該開口之側面係呈平滑表面；形成線路層於該封裝層之第二表面上，且該線路層具有形成於該開口中之導電體；以及移除該承載件。 The invention provides a method for fabricating a semiconductor package, comprising: providing a carrier member provided with at least one semiconductor component; forming one having at least one An opening encapsulation layer on the carrier, the encapsulation layer encapsulating the semiconductor component, and the encapsulation layer is formed together with the opening system, the encapsulation layer having opposite first and second surfaces, the first The surface is coupled to the carrier, the opening is connected to the first and second surfaces, wherein the side of the opening is a smooth surface; the circuit layer is formed on the second surface of the encapsulation layer, and the circuit layer is formed on An electrical conductor in the opening; and removing the carrier.
前述之半導體封裝件中，該開槽係位於該半導體元件與該開口之間。 In the aforementioned semiconductor package, the trench is located between the semiconductor element and the opening.
前述之製法中，該封裝層係以模封製程或壓合製程形成者。 In the foregoing method, the encapsulation layer is formed by a molding process or a lamination process.
前述之製法中，該封裝層之製程係包括：提供一其內具有至少一凸部之模具；設置該承載件與該半導體元件於該模具中，且形成封裝材於該模具中，以令該封裝材成為該封裝層，且該封裝層於對應該凸部之處係成為該開口；以及移除該模具。例如，該封裝層之步驟係包括：將該封裝材形成於該模具中；將該承載件與該半導體元件設於該模具中；以及壓合該封裝材與該承載件，使該封裝層包覆該半導體元件。或者，該封裝層之步驟係包括：將該承載件與該半導體元件設於該模具中；以及將該封裝材填入該模具中，使該封裝層包覆該半導體元件。 In the above method, the process of the encapsulation layer includes: providing a mold having at least one protrusion therein; disposing the carrier and the semiconductor component in the mold, and forming a package in the mold to make the The encapsulation material becomes the encapsulation layer, and the encapsulation layer is the opening corresponding to the convex portion; and the mold is removed. For example, the step of encapsulating the layer includes: forming the encapsulant in the mold; disposing the carrier and the semiconductor component in the mold; and pressing the package and the carrier to package the encapsulation layer The semiconductor component is covered. Alternatively, the step of encapsulating the layer comprises: disposing the carrier and the semiconductor component in the mold; and filling the encapsulant into the mold, and encapsulating the encapsulation layer with the semiconductor component.
依上述，該模具內復設有至少一定位塊，使該半導體元件受制於該定位塊而定位。因此，於形成該封裝材後，該封裝層復形成有連通該第二表面之開槽，且該開槽係位於該半導體元件與該開口之間，又該開槽係呈現絕緣狀 態，其中，該開槽之側面係呈平滑表面，而該開槽之型式係為長條狀或孔狀。 According to the above, at least one positioning block is disposed in the mold, so that the semiconductor component is positioned by the positioning block. Therefore, after the package material is formed, the encapsulation layer is formed with a groove connecting the second surface, and the groove is located between the semiconductor element and the opening, and the groove is insulative The side of the groove is a smooth surface, and the groove is in the form of a strip or a hole.
前述之半導體封裝件及其製法中，該半導體元件之作用面係齊平該封裝層之第一表面。 In the foregoing semiconductor package and method of fabricating the same, the active surface of the semiconductor component is flush with the first surface of the encapsulation layer.
前述之半導體封裝件及其製法中，該半導體元件之非作用面係齊平該封裝層之第二表面。 In the foregoing semiconductor package and method of fabricating the same, the inactive surface of the semiconductor component is flush with the second surface of the encapsulation layer.
前述之半導體封裝件及其製法中，形成該導電體之材質係包含銅、鋁、鈦或其至少二者之組合。 In the above semiconductor package and method of fabricating the same, the material forming the conductor comprises copper, aluminum, titanium or a combination of at least two thereof.
前述之半導體封裝件及其製法中，復包括形成絕緣保護層於該封裝層之第二表面與該線路層上，且該絕緣保護層係露出該線路層之部分表面。 In the foregoing semiconductor package and method of fabricating the same, the insulating protective layer is formed on the second surface of the encapsulation layer and the circuit layer, and the insulating protection layer exposes a part of the surface of the circuit layer.
另外，前述之半導體封裝件及其製法中，復包括移除該承載件之後，形成線路結構於該封裝層之第一表面上，且該線路結構電性連接該導電體及/或該半導體元件。例如，該線路結構係包含至少一線路重佈層。 In addition, in the foregoing semiconductor package and the manufacturing method thereof, after removing the carrier, forming a wiring structure on the first surface of the packaging layer, and the wiring structure is electrically connected to the electrical conductor and/or the semiconductor component . For example, the line structure includes at least one line redistribution layer.
由上可知，本發明之半導體封裝件及其製法中，藉由該封裝層與該些開口一同製成，使該開口之壁面之粗糙度極低，因而當電鍍製作該導電體時，能提升電鍍品質，以避免良率過低及產品可靠度不佳等問題。 It can be seen from the above that in the semiconductor package of the present invention and the manufacturing method thereof, the encapsulation layer is formed together with the openings, so that the roughness of the wall surface of the opening is extremely low, so that when the electroconducting body is electroplated, the lifting can be improved. Plating quality to avoid problems such as low yield and poor product reliability.
再者，藉由該封裝層與該些開口一同製成，能大幅縮短製程時間。 Furthermore, by making the encapsulation layer together with the openings, the process time can be greatly shortened.
又，藉由模具之定位塊，以於形成該封裝層時，能限制該半導體元件之位移，而達到定位該半導體元件之目的。 Moreover, by positioning the block of the mold, when the package layer is formed, the displacement of the semiconductor element can be restricted to achieve the purpose of positioning the semiconductor element.
1,2,2’,4‧‧‧半導體封裝件 1,2,2',4‧‧‧Semiconductor package
10,20‧‧‧半導體元件 10,20‧‧‧Semiconductor components
100,200‧‧‧電極墊 100,200‧‧‧electrode pads
11,21‧‧‧承載件 11, 21‧‧‧ Carrying parts
110‧‧‧熱化離形層 110‧‧‧heating the release layer
12‧‧‧另一承載件 12‧‧‧Another carrier
120‧‧‧銅箔 120‧‧‧ copper foil
13,23‧‧‧封裝層 13,23‧‧‧Encapsulation layer
130,230‧‧‧開口 130,230‧‧‧ openings
130a‧‧‧粗糙表面 130a‧‧‧Rough surface
14‧‧‧導電柱 14‧‧‧conductive column
15,260‧‧‧線路重佈層 15,260‧‧‧Line redistribution
16,26‧‧‧線路結構 16,26‧‧‧Line structure
20a‧‧‧作用面 20a‧‧‧Action surface
20b‧‧‧非作用面 20b‧‧‧Non-active surface
210‧‧‧間隔層 210‧‧‧ spacer
22‧‧‧封裝材 22‧‧‧Package
23a‧‧‧第一表面 23a‧‧‧ first surface
23b‧‧‧第二表面 23b‧‧‧ second surface
231‧‧‧開槽 231‧‧‧ slotting
24‧‧‧線路層 24‧‧‧Line layer
240‧‧‧導電體 240‧‧‧Electrical conductor
241‧‧‧電性接觸墊 241‧‧‧Electrical contact pads
242‧‧‧表面處理層 242‧‧‧Surface treatment layer
25‧‧‧絕緣保護層 25‧‧‧Insulating protective layer
250‧‧‧開孔 250‧‧‧ openings
27,28‧‧‧導電元件 27,28‧‧‧Conductive components
3‧‧‧電子裝置 3‧‧‧Electronic devices
40‧‧‧封裝基板 40‧‧‧Package substrate
41‧‧‧晶片 41‧‧‧ wafer
9‧‧‧模具 9‧‧‧Mold
9a‧‧‧第一模體 9a‧‧‧First phantom
9b‧‧‧第二模體 9b‧‧‧Second phantom
90‧‧‧凸部 90‧‧‧ convex
91‧‧‧定位塊 91‧‧‧ Positioning block
92‧‧‧離形膜 92‧‧‧Dissecting film
S‧‧‧切割路徑 S‧‧‧ cutting path
第1A至1F圖係為習知半導體封裝件之製法之剖面示意圖；第2A至2H圖係為本發明半導體封裝件之製法之剖視示意圖；其中，第2A’圖係為第2A圖之承載件與半導體晶片之上視平面圖，第2A”圖係為第2A圖之第一模體之局部上視平面圖，第2B’圖係為第2B圖之另一方式，第2H’圖係為第2H圖之另一實施例；以及第3圖係為本發明半導體封裝件之後續應用之剖視示意圖。 1A to 1F are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; and FIGS. 2A to 2H are cross-sectional views showing a method of fabricating the semiconductor package of the present invention; wherein the 2A' is a carrier of FIG. 2A FIG. 2A" is a partial top plan view of the first mode of FIG. 2A, and FIG. 2B' is another mode of FIG. 2B, and the 2H' picture is the first Another embodiment of the 2H diagram; and FIG. 3 is a cross-sectional view of a subsequent application of the semiconductor package of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower", "first", "second" and "one" are used in the description for convenience of description, and are not intended to limit the invention. Changes in the scope of implementation, changes or adjustments in their relative relationship, are considered to be within the scope of the present invention.
第2A至2H圖係為本發明半導體封裝件2之製法之剖視示意圖。 2A to 2H are schematic cross-sectional views showing the manufacturing method of the semiconductor package 2 of the present invention.
如第2A及2A’圖所示，提供一設有複數半導體元件20之承載件21，且提供一其內具有複數凸部90及複數定位塊91之模具9。 As shown in Figs. 2A and 2A', a carrier 21 having a plurality of semiconductor elements 20 is provided, and a mold 9 having a plurality of projections 90 and a plurality of positioning blocks 91 therein is provided.
於本實施例中，各該半導體元件20具有相對之作用面20a與非作用面20b，且該作用面20a具有複數電極墊200。 In this embodiment, each of the semiconductor elements 20 has an opposite active surface 20a and an inactive surface 20b, and the active surface 20a has a plurality of electrode pads 200.
再者，該承載件21可選用金屬板、半導體晶圓或玻璃板，且該承載件21具有一如離形膜、黏著材、絕緣材等之間隔層210，以供接合該半導體元件20之作用面20a。 Furthermore, the carrier member 21 may be a metal plate, a semiconductor wafer or a glass plate, and the carrier member 21 has a spacer layer 210 such as a release film, an adhesive material, an insulating material or the like for bonding the semiconductor device 20 Acting surface 20a.
又，該模具9係包含第一模體9a與第二模體9b，該些凸部90及定位塊91係設於該第一模體9a，且該第一模體9a表面設有一離形膜92。 Moreover, the mold 9 includes a first mold body 9a and a second mold body 9b. The protrusions 90 and the positioning block 91 are disposed on the first mold body 9a, and a surface of the first mold body 9a is provided with a release shape. Membrane 92.
另外，該凸部90係為錐形柱結構，該些定位塊91係為尖錐，且該凸部90之長度係大於該定位塊91之長度，該些定位塊91並對應該半導體元件20之形狀排設，而該些凸部90係位於該些定位塊91之外圍，如第2A”圖所示。 In addition, the convex portion 90 is a tapered column structure, the positioning blocks 91 are tapered, and the length of the convex portion 90 is greater than the length of the positioning block 91. The positioning blocks 91 are corresponding to the semiconductor component 20 The shape is arranged, and the protrusions 90 are located at the periphery of the positioning blocks 91, as shown in FIG. 2A.
如第2B圖所示，將如樹脂之封裝材22形成於該模具9之第一模體9a上，且將該承載件21與該半導體元件20設於該模具9之第二模體9b上。 As shown in FIG. 2B, a package material 22 such as a resin is formed on the first mold body 9a of the mold 9, and the carrier member 21 and the semiconductor element 20 are disposed on the second mold body 9b of the mold 9. .
如第2C圖所示，壓合該第一模體9a與第二模體9b(即壓合該封裝材22與該承載件21)，使該封裝材22成為封裝層23而包覆該半導體元件20，且該封裝層23於對應各該凸部90之處係成為開口230，而該封裝層23於對應各 該定位塊91之處係成為開槽231。 As shown in FIG. 2C, the first mold body 9a and the second mold body 9b are press-fitted (ie, the package member 22 and the carrier member 21 are pressed together), and the package member 22 is encapsulated to cover the semiconductor. The component 20, and the encapsulation layer 23 is an opening 230 corresponding to each of the protrusions 90, and the encapsulation layer 23 is correspondingly The positioning block 91 is a slot 231.
於本實施例中，該封裝層23、該些開口230與該些開槽231係一同製成，且於形成該封裝層23時，該定位塊91會限制該半導體元件20之位移範圍，使該半導體元件20不會受該封裝材22壓迫而過度位移，故藉由該定位塊91之設計能達到定位該半導體元件20之效果。 In the embodiment, the encapsulation layer 23 and the openings 230 are formed together with the slots 231, and when the encapsulation layer 23 is formed, the positioning block 91 limits the displacement range of the semiconductor component 20, so that The semiconductor element 20 is not excessively displaced by the pressing of the package 22, so that the positioning of the positioning block 91 can achieve the effect of positioning the semiconductor element 20.
於另一實施例中，亦可先將該承載件21與該半導體元件20設於該模具9中，如第2B’圖所示，再以模封(molding)方式將封裝材22填入該模具9中，使該封裝層23包覆該半導體元件20。 In another embodiment, the carrier 21 and the semiconductor component 20 may be first disposed in the mold 9, as shown in FIG. 2B', and the package 22 is filled in the molding manner. In the mold 9, the encapsulating layer 23 is coated with the semiconductor element 20.
再者，該開槽231之型式可為長條狀或孔狀，如依該定位塊91之形狀。 Moreover, the shape of the slot 231 may be elongated or hole-shaped, such as in the shape of the positioning block 91.
如第2D圖所示，移除該模具9，以外露出該半導體元件20之非作用面20b、該承載件21與該封裝層23，且藉由該離形膜92以利於分離該模具9與該封裝層23。 As shown in FIG. 2D, the mold 9 is removed, and the non-active surface 20b of the semiconductor component 20, the carrier 21 and the encapsulation layer 23 are exposed, and the release film 92 is used to facilitate separation of the mold 9 and The encapsulation layer 23.
於本實施例中，該封裝層23具有相對之第一表面23a及第二表面23b，且該第一表面23a係結合於該承載件21。 In the embodiment, the encapsulation layer 23 has a first surface 23a and a second surface 23b opposite to each other, and the first surface 23a is coupled to the carrier 21.
再者，各該開口230係位於該半導體元件20周邊區域並連通該第一及第二表面23a,23b。 Furthermore, each of the openings 230 is located in a peripheral region of the semiconductor element 20 and communicates with the first and second surfaces 23a, 23b.
又，各該開槽231係連通該第二表面23b而未連通該第一表面23a並位於該半導體元件20與該些開口230之間。 Moreover, each of the slots 231 communicates with the second surface 23b without communicating with the first surface 23a and between the semiconductor element 20 and the openings 230.
另外，該半導體元件20之非作用面20b係齊平該封裝層23之第二表面23b。 In addition, the non-active surface 20b of the semiconductor element 20 is flush with the second surface 23b of the encapsulation layer 23.
如第2E圖所示，進行RDL製程，以形成一線路層24於該封裝層23之第二表面23b上，且該線路層24具有形成於該開口230中之導電體240。 As shown in FIG. 2E, an RDL process is performed to form a wiring layer 24 on the second surface 23b of the encapsulation layer 23, and the wiring layer 24 has an electrical conductor 240 formed in the opening 230.
於本實施例中，該導電體240係為導電柱，且形成該導電體240之材質係包含銅、鋁、鈦或其至少二者之組合。 In this embodiment, the electrical conductor 240 is a conductive pillar, and the material forming the electrical conductor 240 includes copper, aluminum, titanium, or a combination of at least two thereof.
再者，形成一絕緣保護層25於該封裝層23之第二表面23b與該線路層24上，且該絕緣保護層25係形成有複數開孔250，以令該線路層24之部分表面外露出該些開孔250，俾供作為電性接觸墊241。 Furthermore, an insulating protective layer 25 is formed on the second surface 23b of the encapsulating layer 23 and the wiring layer 24, and the insulating protective layer 25 is formed with a plurality of openings 250 to make the surface of the circuit layer 24 outside the surface. The openings 250 are exposed and serve as electrical contact pads 241.
又，各該電性接觸墊241上可依需求形成表面處理層242，且形成該表面處理層242之材質係為鎳、鈀、金所組群組之合金、多層金屬或有機保焊劑(Organic Solderability Preservative，簡稱OSP)所組成之群組中之其中一者，例如，電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)等，但不限於上述。 Moreover, the surface treatment layer 242 can be formed on each of the electrical contact pads 241, and the surface treatment layer 242 is formed of an alloy of nickel, palladium, gold, a multilayer metal or an organic soldering agent (Organic). One of the groups consisting of Solderability Preservative (OSP), for example, electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin), etc., but not limited to the above.
另外，各該開槽231係呈現絕緣狀態，例如，該絕緣保護層25填滿各該開槽231。 In addition, each of the slots 231 is in an insulated state, for example, the insulating protective layer 25 fills each of the slots 231.
如第2F圖所示，移除該承載件21及其該間隔層210，以外露出該半導體元件20之作用面20a、該封裝層23之第一表面23a與導電體240之底端。 As shown in FIG. 2F, the carrier 21 and the spacer layer 210 are removed, and the active surface 20a of the semiconductor device 20, the first surface 23a of the encapsulation layer 23 and the bottom end of the conductor 240 are exposed.
於本實施例中，該半導體元件20之作用面20a係齊平該封裝層23之第一表面23a。 In this embodiment, the active surface 20a of the semiconductor component 20 is flush with the first surface 23a of the encapsulation layer 23.
如第2G圖所示，形成一線路結構26於該封裝層23 之第一表面23a上，使該線路結構26電性連接該導電體240與該半導體元件20之電極墊200。 As shown in FIG. 2G, a wiring structure 26 is formed on the encapsulation layer 23 The circuit structure 26 is electrically connected to the conductive body 240 and the electrode pad 200 of the semiconductor element 20 on the first surface 23a.
於本實施例中，該線路結構26係包含至少一線路重佈層(redistribution layer,RDL)260與設於最外層線路重佈層260上之複數導電元件27，且該導電元件27係包含銲錫材料。 In this embodiment, the circuit structure 26 includes at least one redistribution layer (RDL) 260 and a plurality of conductive elements 27 disposed on the outermost circuit redistribution layer 260, and the conductive element 27 includes solder. material.
如第2H圖所示，沿如第2G圖所示之切割路徑S進行切單製程，以獲取複數該半導體封裝件2。 As shown in FIG. 2H, a singulation process is performed along the dicing path S as shown in FIG. 2G to obtain a plurality of the semiconductor packages 2.
於另一實施例中，當該模具9未具有定位塊91時，該封裝層23不會形成開槽231，因而將製成如第2H’圖所示之半導體封裝件2’，且於此製程中，該模具9之凸部90可依需求兼具定位該半導體元件20之用，例如該凸部90之位置更靠近該半導體元件20。 In another embodiment, when the mold 9 does not have the positioning block 91, the encapsulation layer 23 does not form the slit 231, and thus the semiconductor package 2' shown in FIG. 2H' is formed, and In the process, the convex portion 90 of the mold 9 can be used for positioning the semiconductor element 20 as needed, for example, the convex portion 90 is located closer to the semiconductor element 20.
本發明之製法中，藉由在模封或壓合製程的模具9上設置凸部90，以利用該些凸部90形成該開口230，使該封裝層23與該些開口230係一同製成，故該開口230之壁面之粗糙度極低(例如，該開口230之側面與該開槽231之側面係呈平滑表面)，因而當電鍍製作該導電體240時，能提升電鍍品質，以避免良率過低及產品可靠度不佳等問題。 In the manufacturing method of the present invention, the convex portion 90 is provided on the mold 9 of the molding or pressing process, and the opening 230 is formed by the convex portions 90, so that the encapsulating layer 23 is formed together with the openings 230. Therefore, the roughness of the wall surface of the opening 230 is extremely low (for example, the side surface of the opening 230 and the side surface of the opening 231 are smooth surfaces), so that when the conductive body 240 is electroplated, the plating quality can be improved to avoid Problems such as low yield and poor product reliability.
再者，於模封或壓合製程時，同時製成該封裝層23與該些開口230，因而能大幅縮短製程時間，故若要形成直徑100um以上的開口230，其製程時間極短，因而利於降低成本。 Furthermore, during the molding or lamination process, the encapsulation layer 23 and the openings 230 are simultaneously formed, so that the process time can be greatly shortened. Therefore, if the opening 230 having a diameter of 100 μm or more is formed, the process time is extremely short. Conducive to reducing costs.
又，藉由在模具9上設置定位塊91，以於模封或壓合製程時限制該半導體元件20之位移，故於量產時，當該承載件21之尺寸越大時，該半導體元件20間之位置公差不會隨之加大。因此，於製作該線路結構26時，該線路重佈層260與該電極墊200間之電性連接能有效對接，因而能提高良率及提升產品可靠度。 Moreover, by providing the positioning block 91 on the mold 9, the displacement of the semiconductor element 20 is restricted during the molding or pressing process, so that when the size of the carrier 21 is larger, the semiconductor element is mass-produced. The positional tolerances of the 20 rooms will not increase. Therefore, when the circuit structure 26 is fabricated, the electrical connection between the circuit redistribution layer 260 and the electrode pad 200 can be effectively docked, thereby improving yield and improving product reliability.
另外，於後續製程中，如第3圖所示，該半導體封裝件2可藉由該些導電元件27接置如電路板之電子裝置3，且該些電性接觸墊241可藉由複數導電元件28接置另一半導體封裝件4，以形成封裝堆疊裝置，其中，該另一半導體封裝件4係包含一封裝基板40與至少一晶片41。 In addition, in the subsequent process, as shown in FIG. 3, the semiconductor package 2 can be connected to the electronic device 3 such as a circuit board by the conductive elements 27, and the electrical contact pads 241 can be electrically conductive. The component 28 is connected to another semiconductor package 4 to form a package stacking device, wherein the other semiconductor package 4 comprises a package substrate 40 and at least one wafer 41.
本發明提供一種半導體封裝件2，係包括：一半導體元件20、一具有相對之第一表面23a與第二表面23b的封裝層23、以及一線路層24。 The present invention provides a semiconductor package 2 comprising a semiconductor component 20, an encapsulation layer 23 having opposing first and second surfaces 23a, 23b, and a wiring layer 24.
所述之半導體元件20係具有相對之作用面20a與非作用面20b，且該作用面20a具有複數電極墊200。 The semiconductor device 20 has an opposite active surface 20a and an inactive surface 20b, and the active surface 20a has a plurality of electrode pads 200.
所述之封裝層23係包覆該半導體元件20，且該封裝層23具有至少一開口230及至少一開槽231，該開口230係連通該第一及第二表面23a,23b，該開槽231係連通該第二表面23b而未連通該第一表面23a並呈現絕緣狀態，其中，該開口230之側面與該開槽231之側面係呈平滑表面。 The encapsulation layer 23 covers the semiconductor component 20, and the encapsulation layer 23 has at least one opening 230 and at least one slot 231. The opening 230 communicates with the first and second surfaces 23a, 23b. The second surface 23b communicates with the first surface 23a and is in an insulated state, wherein the side surface of the opening 230 and the side surface of the slit 231 have a smooth surface.
所述之線路層24係設於該封裝層23之第二表面23b上，且該線路層24具有形成於該開口230中之導電體240。 The circuit layer 24 is disposed on the second surface 23b of the encapsulation layer 23, and the circuit layer 24 has an electrical conductor 240 formed in the opening 230.
於一實施例中，該開槽231係位於該半導體元件20 與該開口230之間。 In an embodiment, the slot 231 is located in the semiconductor component 20 Between the opening 230 and the opening.
於一實施例中，形成該導電體240之材質係包含銅、鋁、鈦或其至少二者之組合。 In one embodiment, the material forming the electrical conductor 240 comprises copper, aluminum, titanium, or a combination of at least two thereof.
於一實施例中，所述之半導體封裝件2復包括一絕緣保護層25，係設於該封裝層23之第二表面23b與該線路層24上，且該絕緣保護層25係露出該線路層24之部分表面。 In one embodiment, the semiconductor package 2 includes an insulating protective layer 25 disposed on the second surface 23b of the encapsulating layer 23 and the wiring layer 24, and the insulating protective layer 25 exposes the wiring. Part of the surface of layer 24.
於一實施例中，所述之半導體封裝件2復包括一線路結構26，係設於該封裝層23之第一表面23a上，且該線路結構26電性連接該導電體240與該半導體元件20。該線路結構26係包含至少一線路重佈層260。 In one embodiment, the semiconductor package 2 includes a wiring structure 26 disposed on the first surface 23a of the encapsulation layer 23, and the wiring structure 26 is electrically connected to the electrical conductor 240 and the semiconductor component. 20. The line structure 26 includes at least one line redistribution layer 260.
綜上所述，本發明之半導體封裝件及其製法中，藉由該封裝層與該些開口一同製成，不僅能避免該開口之壁面過於粗糙，且能大幅縮短製程時間。 In summary, in the semiconductor package of the present invention and the method of fabricating the same, the package layer is formed together with the openings, thereby not only preventing the wall surface of the opening from being too rough, but also greatly shortening the process time.
再者，藉由模具之定位塊，以於形成該封裝層時限制該半導體元件之位移，而達到定位該半導體元件之目的。 Moreover, by positioning the block of the mold, the displacement of the semiconductor element is restricted when the package layer is formed, and the purpose of positioning the semiconductor element is achieved.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
20‧‧‧半導體元件 20‧‧‧Semiconductor components
21‧‧‧承載件 21‧‧‧Carrier
210‧‧‧間隔層 210‧‧‧ spacer
23‧‧‧封裝層 23‧‧‧Encapsulation layer
230‧‧‧開口 230‧‧‧ openings
231‧‧‧開槽 231‧‧‧ slotting
9‧‧‧模具 9‧‧‧Mold
9a‧‧‧第一模體 9a‧‧‧First phantom
9b‧‧‧第二模體 9b‧‧‧Second phantom
90‧‧‧凸部 90‧‧‧ convex
91‧‧‧定位塊 91‧‧‧ Positioning block
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| TW200949962A (en) * | 2008-01-28 | 2009-12-01 | Nichia Corp | Metal mold for injection molding and semiconductor package formed therewith and method of manufacturing semiconductor package |
| TW201119003A (en) * | 2009-11-19 | 2011-06-01 | Advanced Semiconductor Eng | Semiconductor device packages and manufacturing method thereof |
| TW201308538A (en) * | 2011-08-09 | 2013-02-16 | Advanced Semiconductor Eng | Stackable wafer level packages and related methods |
| TW201330746A (en) * | 2011-10-11 | 2013-07-16 | Hitachi Chemical Co Ltd | Structure body having conductor circuit and manufacturing method thereof and thermosetting resin composition |
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| CN100442483C (en) * | 2004-09-16 | 2008-12-10 | 夏普株式会社 | Optical semiconductor device, method for fabricating the same, lead frame and electronic equipment |
| US8558392B2 (en) * | 2010-05-14 | 2013-10-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant |
| US8610286B2 (en) * | 2011-12-08 | 2013-12-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP |
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| TW200949962A (en) * | 2008-01-28 | 2009-12-01 | Nichia Corp | Metal mold for injection molding and semiconductor package formed therewith and method of manufacturing semiconductor package |
| TW201119003A (en) * | 2009-11-19 | 2011-06-01 | Advanced Semiconductor Eng | Semiconductor device packages and manufacturing method thereof |
| TW201308538A (en) * | 2011-08-09 | 2013-02-16 | Advanced Semiconductor Eng | Stackable wafer level packages and related methods |
| TW201330746A (en) * | 2011-10-11 | 2013-07-16 | Hitachi Chemical Co Ltd | Structure body having conductor circuit and manufacturing method thereof and thermosetting resin composition |
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