TWI553808B - Pad structure - Google Patents

Description

Pad structure

The present invention relates to a pad structure, and more particularly to a pad structure having a stepped structure.

With the integration of semiconductor components, in order to achieve high density and high performance targets, development in three-dimensional space has become a trend within a limited unit area. A common three-dimensional semiconductor component such as a non-volatile memory (NAND, Not AND) type flash memory includes a vertical memory array in which a plurality of memory cells are arranged.

Taking a three-dimensional non-volatile memory as an example, although the three-dimensional semiconductor component increases the memory capacity per unit area, the structure of the vertical memory array makes the difficulty of electrically connecting the memory cells of different layers to the outside world. increase. Therefore, how to electrically connect a plurality of memory cells in a three-dimensional non-volatile memory to the outside world and take into consideration the minimization of the unit area is a subject of current research.

The invention provides a pad structure, which can greatly reduce the occupied area of the pad structure in the three-dimensional semiconductor component.

The present invention provides a pad structure comprising a plurality of stepped structures. The stepped structure is disposed on the substrate. Each of the stepped structures includes a plurality of conductor layers and a plurality of dielectric layers alternately stacked with each other. Adjacent two step structures are connected to each other by a common conductor layer and a dielectric layer and are arranged in parallel in the first direction. One of the adjacent two stepped structures includes at least one stepped portion whose height is gradually lowered in the second direction, and the other of the adjacent two stepped structures includes at least one of which the height gradually decreases in the opposite direction of the second direction Step part.

According to an embodiment of the present invention, in the above-mentioned pad structure, the lowest order height of one of the adjacent two step structures is, for example, higher than the other of the adjacent two step structures. The height of the steps.

According to an embodiment of the present invention, in the pad structure described above, the lowest order of one of the adjacent two stepped structures and the highest order of the other of the adjacent two stepped structures may form a connecting portion. . The height of the connecting portion is gradually lowered in the first direction.

According to an embodiment of the present invention, in the pad structure described above, the stepped portion and the connecting portion of the adjacent two stepped structures may form a continuous step.

According to an embodiment of the present invention, in the above-mentioned pad structure, the number of layers of the conductor layer of one of the adjacent two stepped structures is, for example, a conductor larger than the other of the adjacent two stepped structures. The number of layers in the layer.

According to an embodiment of the present invention, in the above pad structure, the second direction is orthogonal to the first direction, for example.

According to an embodiment of the present invention, in the above-mentioned pad structure, a part of the conductor layers of each step structure may have a bare surface. The area of the exposed surface is, for example, gradually increasing, decreasing, or equivalent as the height of the stepped portion is lowered.

According to an embodiment of the present invention, in the pad structure described above, each of the step structures includes two stepped portions. The height of one of the stepped portions is, for example, gradually lowered in the second direction, and the height of the other of the stepped portions is gradually lowered, for example, in the opposite direction of the second direction.

According to an embodiment of the present invention, in the above-described pad structure, the lowest order height of one of the stepped portions is, for example, higher than the highest order height of the other of the stepped portions.

According to an embodiment of the present invention, in the pad structure described above, adjacent two-order conductor layers in the step portion are electrically isolated by a dielectric layer.

Based on the above, since the pad structure proposed by the present invention has a stepped structure, it is possible to easily connect the elements connected to each stage in the three-dimensional space with the outside. In addition, the adjacent two stepped structures have a stepped portion whose height is gradually lowered in the opposite direction, so that more components can be accommodated in the same unit area, and the occupied area of the pad structure in the three-dimensional semiconductor component is greatly reduced, thereby further Achieve high density and high performance goals.

The above described features and advantages of the invention will be apparent from the following description.

1 is a perspective view of a pad structure in accordance with an embodiment of the present invention.

Referring to FIG. 1 , the pad structure 10 includes a plurality of step structures 110 . In this embodiment, the pad structure 10 can include three stepped structures 110, such as the stepped structure 110a, the stepped structure 110b, and the stepped structure 110c. The stepped structures 110a, 110b, 110c are arranged in parallel in the first direction D1, respectively.

The stepped structure 110 may be disposed on the substrate 100. The substrate 100 is, for example, a crucible substrate. The step structure 110 includes a plurality of conductor layers 102 and a plurality of dielectric layers 104 that are alternately stacked one upon another. In this embodiment, the dielectric layer 104 is located on the substrate 100, and the conductor layer 102 is located on the dielectric layer 104, but the invention is not limited thereto.

The material of the conductor layer 102 includes a conductor or a doped semiconductor. The conductor layer 102 is, for example, a metal material, an N+ doped polysilicon, a P+ doped polysilicon, or a combination thereof. The method of forming the conductor layer 102 is, for example, a physical vapor deposition method or a chemical vapor deposition method. The conductor layer 102 may be a word line in the memory or an interconnect structure for connecting the memory cell and the bit line, but the invention is not limited thereto. Those skilled in the art can adjust the use of conductor layer 102 in accordance with product design requirements.

The number of layers of the conductor layer 102 of one of the adjacent two stepped structures 110 is greater than the number of layers of the conductor layer 102 of the other of the adjacent two stepped structures 110. In this embodiment, the number of layers of the conductor layer 102 such as the stepped structure 110a is larger than the number of layers of the conductor layer 102 of the stepped structure 110b, and the number of layers of the conductor layer 102 of the stepped structure 110b is larger than the layer of the conductor layer 102 of the stepped structure 110c. number. That is, the number of layers of the conductor layer 102 of the stepped structure 110 is decreased in the first direction D1. In another embodiment, the number of layers of the conductor layer 102 of the stepped structure 110 may also be increased along the first direction D1.

The material of the dielectric layer 104 may include a dielectric material such as an oxide, a nitride, or an oxynitride. The method of forming the dielectric layer 104 includes a thermal oxidation method or a chemical vapor deposition method.

It should be noted that the adjacent two stepped structures 110 are connected to each other by the common conductor layer 102 and the dielectric layer 104. In this embodiment, the stepped structure 110a and the stepped structure 110b in FIG. 1 are connected to each other by the common conductor layer 102 and the dielectric layer 104 in the first direction D1. That is, the stepped structure 110a, the stepped structure 110b, and the stepped structure 110c in the pad structure 10 are connected to each other by the common conductor layer 102 and the dielectric layer 104.

With continued reference to FIG. 1, each of the stepped structures 110 includes at least one stepped portion 112. In this embodiment, the stepped structure 110a includes a stepped portion 112a, the stepped structure 110b includes a stepped portion 112b, and the stepped structure 110c includes a stepped portion 112c. Each of the steps in the step portion 112 includes at least one conductor layer 102 and one dielectric layer 104, but the invention is not limited thereto. The conductor layers 102 in the adjacent two stages can be electrically isolated by the dielectric layer 104. Further, in the stepped portion 112 of each stepped structure 110, a portion of the conductor layer 102 has a bare surface S. The exposed surface S can be electrically connected to the wire via a contact window (not shown), for example. The exposed surface S in the stepped structure 110 may have the same area, such as the stepped structure 110a and the stepped structure 110b. In addition, the area of the exposed surface S in the stepped structure 110 may also increase as the height of the stepped portion 112 decreases, such as the stepped structure 110c. In other words, the area of the exposed surface S of the lower conductor layer 102 in the adjacent two stages of the stepped structure 110c is, for example, larger than the area of the exposed surface S of the upper conductor layer 102, and the contact window and the deeper exposed surface S can be made. connection. In other embodiments, the exposed surface S of the stepped structure 110 may also decrease as the height of the stepped portion 112 decreases. Those skilled in the art can adjust the area of the exposed surface S in the step structure 110 in accordance with process requirements.

The adjacent two stepped structures 110 have a stepped portion 112 whose height is gradually lowered in the opposite direction. In this embodiment, the stepped structure 110a includes a stepped portion 112a whose height is gradually lowered in the second direction D2, the stepped structure 110b includes a stepped portion 112b whose height is gradually lowered in the reverse direction of the second direction D2, and the stepped structure 110c includes the height along the edge The step portion 112c in which the second direction D2 is gradually lowered. In other words, the adjacent stepped structure 110a and the stepped structure 110b have the stepped portion 112a and the stepped portion 112b which are gradually lowered in opposite directions, and the adjacent stepped structure 110b and the stepped structure 110c have the stepped portion 112b which is gradually lowered in the opposite direction With the step portion 112c. The second direction D2 is different from the first direction D1. The second direction D2 is, for example, orthogonal to the first direction D1.

The lowest order height of one of the adjacent two stepped structures 110 is, for example, a height higher than the highest order of the other of the adjacent two stepped structures 110. In this embodiment, the lowest order height of the stepped structure 110a is, for example, higher than the highest order height of the stepped structure 110b, and the lowest order height of the stepped structure 110b is, for example, higher than the highest order height of the stepped structure 110c.

The lowest order of one of the adjacent two stepped structures 110 and the highest order of the other of the adjacent two stepped structures 110 form the connecting portion 120, and the height of the connecting portion 120 is gradually lowered, for example, along the first direction D1. . In this embodiment, the lowest order of the stepped structure 110a and the highest order of the stepped structure 110b may form the connecting portion 120a, and the lowest order of the stepped structure 110b and the highest order of the stepped structure 110c may form the connecting portion 120b. Further, the stepped portion 112 of the adjacent two stepped structures 110 may form a continuous step with the connecting portion 120. In this embodiment, the stepped portion 112a of the stepped structure 110a and the stepped portion 112b of the stepped structure 110b may form a continuous step by the connecting portion 120a, and the stepped portion 112b of the stepped structure 110b and the stepped portion 112c of the stepped structure 110c may be A continuous step is formed by the connecting portion 120b.

In this embodiment, although the pad structure 10 is illustrated by having three stepped structures 110, it is not necessary to limit the present invention. In another embodiment, the pad structure 10 may also include two stepped structures 110 (such as the stepped structure 110a and the stepped structure 110b or the stepped structure 110b and the stepped structure 110c) or more than four stepped structures 110. Those skilled in the art to which the present invention pertains can adjust the number of ladder structures 110 by themselves according to product design requirements. In addition, the pad structure 10 can be used to connect various semiconductor components to the outside. For example, the pad structure 10 can connect the memory component to an external power source or other external signal.

Based on the above embodiment, since the pad structure 10 has the stepped structure 110, it is possible to easily connect the elements connected to each stage in the three-dimensional space with the outside. In addition, since the adjacent two stepped structures 110 have stepped portions 112 whose heights are gradually lowered in opposite directions, the pad structure 10 of the present embodiment can accommodate more in the same unit area than the conventional pads. The multi-element can greatly reduce the area occupied by the pad structure 10 in the three-dimensional semiconductor component.

Further, in the pad structure 10 shown in FIG. 1, each of the step structures 110 includes only one stepped portion 112. However, the above-described pad structure 10 is illustrative and is not intended to limit the invention. In other embodiments, the stepped structure 110 can also include one or more stepped portions 112, respectively, as described below.

2 is a perspective view of a pad structure in accordance with another embodiment of the present invention.

Referring to FIG. 2, the difference between the pad structure 20 of FIG. 2 and the pad structure 10 of FIG. 1 is as follows. Each of the stepped structures 210 of FIG. 2 has two stepped portions (ie, the stepped portion 112 and the stepped portion 114), and each of the stepped structures 110 of FIG. 1 has only one stepped portion (ie, the stepped portion 112), that is, each stepped structure 210 is different from the number of stepped portions of each of the stepped structures 110. The same components are denoted by the same symbols and will not be described again.

The pad structure 20 includes a plurality of stepped structures 210. In this embodiment, the pad structure 20 is illustrated by including two step structures 210, such as the step structure 210a and the step structure 210b in FIG. In other embodiments, the number of the stepped structures 210 of the pad structure 20 may be more than three.

Each stepped structure 210 includes stepped portions 112, 114. For example, the step structure 210a includes a stepped portion 112a and a stepped portion 114a, and the stepped structure 210b includes a stepped portion 112b and a stepped portion 114b. In this embodiment, each step structure 210 is described by taking two step portions as an example, but the invention is not limited thereto. In other embodiments, each step structure 210 may also have more than three stepped portions.

In each of the stepped structures 210, the height of one of the stepped portions 112, 114 is gradually lowered in the second direction D2, and the height of the other of the stepped portions 112, 114 is gradually decreased in the opposite direction of the second direction D2. In the stepped structure 210a, the height of the stepped portion 112a is gradually lowered, for example, in the second direction D2, and the height of the stepped portion 114a is gradually lowered, for example, in the opposite direction of the second direction D2. Further, in the stepped structure 210b, the height of the stepped portion 114b is gradually lowered, for example, in the second direction D2, and the height of the stepped portion 112b is gradually lowered, for example, in the opposite direction of the second direction D2.

It can be seen from the above embodiment that since the adjacent two stepped structures 210a, 210b respectively have stepped portions 112a, 112b or stepped portions 114a, 114b whose height is gradually lowered in the opposite direction, compared with the conventional pads, The pad structure 20 of the embodiment can accommodate more components in the same unit area and can greatly reduce the area occupied by the pad structure 20 in the three-dimensional semiconductor component.

In the above embodiments, the pad structures 10, 20 are illustrative and are not intended to limit the invention. That is to say, in the adjacent two stepped structures, the pad structure having the stepped portion whose height is gradually lowered in the opposite direction is within the scope of the present invention.

In summary, since the pad structure proposed in the above embodiment has a stepped structure, it is possible to easily connect the components connected to each step in the three-dimensional space with the outside. In addition, each of the two adjacent stepped structures has a stepped portion whose height is gradually lowered in the opposite direction, so that more components can be accommodated in the same unit area, and the pad structure is greatly reduced in the three-dimensional semiconductor component. Area, which in turn achieves high density and high performance goals.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 20: pad structure 100: substrate 102: conductor layer 104: dielectric layer 110, 110a, 110b, 110c, 210, 210a, 210b: step structure 112, 112a, 112b, 112c, 114, 114a, 114b: step Portion 120, 120a, 120b: connecting portion D1, D2: direction S: bare surface

1 is a perspective view of a pad structure in accordance with an embodiment of the present invention. 2 is a perspective view of a pad structure in accordance with another embodiment of the present invention.

10: pad structure 100: substrate 102: conductor layer 104: dielectric layer 110, 110a, 110b, 110c: stepped structure 112, 112a, 112b, 112c: stepped portion 120, 120a, 120b: connecting portion D1, D2: direction S: exposed surface

Claims (10)

A pad structure comprising: a plurality of stepped structures disposed on a substrate, each of the stepped structures comprising a plurality of conductor layers alternately stacked with each other and a plurality of dielectric layers, the adjacent two stepped structures sharing the conductors The layer and the dielectric layers are connected to each other and arranged in parallel along a first direction, wherein one of the adjacent two step structures comprises at least one stepped portion whose height is gradually lowered in a second direction, and adjacent two The other of the stepped structures includes at least one stepped portion whose height is gradually lowered in the opposite direction of the second direction. The pad structure of claim 1, wherein a lowest order height of one of the adjacent two stepped structures is higher than a highest order height of the other of the adjacent two stepped structures. The pad structure according to claim 2, wherein the lowest order of one of the adjacent two stepped structures and the highest order of the other of the adjacent two stepped structures form a connecting portion, the connection The height of the portion is gradually lowered in the first direction. The pad structure of claim 3, wherein the at least one of the adjacent two stepped structures forms a continuous step with the connecting portion. The pad structure of claim 1, wherein the number of layers of the conductor layers of one of the adjacent two step structures is greater than the conductor layers of the other of the adjacent two step structures. The number of layers. The pad structure of claim 1, wherein the second direction is orthogonal to the first direction. The pad structure according to claim 1, wherein a portion of each of the stepped structures has a bare surface, and an area of the exposed surfaces gradually increases as a height of the at least one stepped portion decreases. Declining or equivalent. The pad structure of claim 1, wherein each of the step structures comprises two stepped portions, wherein a height of one of the stepped portions is gradually decreased along the second direction, and the stepped portions are The height of the other one gradually decreases in the opposite direction of the second direction. The pad structure of claim 8, wherein a lowest order height of one of the step portions is higher than a highest order height of the other of the step portions. The pad structure of claim 1, wherein the two adjacent conductor layers of the at least one step portion are electrically isolated by the dielectric layer.