TWI551199B - Substrate with electrical interconnector structure and manufacturing method thereof - Google Patents

Substrate with electrical interconnector structure and manufacturing method thereof Download PDF

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Publication number
TWI551199B
TWI551199B TW103125795A TW103125795A TWI551199B TW I551199 B TWI551199 B TW I551199B TW 103125795 A TW103125795 A TW 103125795A TW 103125795 A TW103125795 A TW 103125795A TW I551199 B TWI551199 B TW I551199B
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layer
metal layer
electrical contact
substrate
contact pads
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TW103125795A
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Chinese (zh)
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TW201542049A (en
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吳柏毅
楊侃儒
黃曉君
莊建隆
馬光華
盧俊宏
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矽品精密工業股份有限公司
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Priority to TW103125795A priority Critical patent/TWI551199B/en
Priority to CN201410408637.4A priority patent/CN105023906B/en
Priority to US14/688,510 priority patent/US9903024B2/en
Publication of TW201542049A publication Critical patent/TW201542049A/en
Application granted granted Critical
Publication of TWI551199B publication Critical patent/TWI551199B/en
Priority to US15/867,919 priority patent/US10774427B2/en
Priority to US16/991,999 priority patent/US11913121B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

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Description

具電性連接結構之基板及其製法 Substrate with electrical connection structure and preparation method thereof

本發明係有關一種具電性連接結構之基板，尤指電性接觸墊與導電凸塊間之結合性改良。 The invention relates to a substrate with an electrical connection structure, in particular to an improved bond between an electrical contact pad and a conductive bump.

隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)或多晶片模組封裝(Multi-Chip Module,MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。 With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. Currently used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (MCM) A crystalline package module, or a three-dimensional stacking of wafers into a three-dimensional integrated circuit (3D IC) wafer stacking technology.

目前三維積體電路(3D IC)晶片堆疊技術，係於封裝基板與半導體晶片之間增設一矽中介板(Silicon interposer)，使該封裝基板可結合具有高佈線密度電極墊之半導體晶片，而達到整合高佈線密度之半導體晶片之目的。 At present, a three-dimensional integrated circuit (3D IC) wafer stacking technology is provided by adding a silicon interposer between a package substrate and a semiconductor wafer, so that the package substrate can be combined with a semiconductor wafer having a high wiring density electrode pad. The purpose of integrating semiconductor wafers with high wiring density.

第1A至1E圖係為習知矽中介板1之製法的剖面示意圖。 1A to 1E are schematic cross-sectional views showing a method of manufacturing the conventional interposer 1.

如第1A圖所示，提供一具有相對之第一表面10a與 第二表面10b之矽板體10，該矽板體10中具有連通該第一表面10a與第二表面10b之複數導電穿孔100、及設於該第一表面10a與該導電穿孔100上之複數電性接觸墊101。 As shown in FIG. 1A, an opposite first surface 10a is provided a slab body 10 of the second surface 10b, the slab body 10 having a plurality of conductive vias 100 communicating with the first surface 10a and the second surface 10b, and a plurality of conductive vias 100 disposed on the first surface 10a and the conductive vias 100 Electrical contact pad 101.

接著，形成一鈍化層11於該矽板體10之第一表面10a上，且該鈍化層11外露出各該電性接觸墊101之部分表面。 Then, a passivation layer 11 is formed on the first surface 10a of the slab body 10, and a portion of the surface of each of the electrical contact pads 101 is exposed outside the passivation layer 11.

接著，形成一晶種層(seed layer)13於該鈍化層11與各該電性接觸墊101上，再形成一電鍍銅層12於該晶種層13上，且該晶種層13之材質係為鈦/銅。 Then, a seed layer 13 is formed on the passivation layer 11 and each of the electrical contact pads 101, and then an electroplated copper layer 12 is formed on the seed layer 13, and the material of the seed layer 13 is formed. It is made of titanium/copper.

接著，形成一阻層14於該電鍍銅層12上，且該阻層14未覆蓋對應各該電性接觸墊101之位置上的電鍍銅層12。 Next, a resist layer 14 is formed on the electroplated copper layer 12, and the resist layer 14 does not cover the electroplated copper layer 12 corresponding to the position of each of the electrical contact pads 101.

接著，形成複數金屬部15於該未覆蓋該阻層14之電鍍銅層12上，且該金屬部15係由一銅層150、一鎳層151、一金層152所構成，該銅層150結合至該電鍍銅層12上，而該鎳層151結合至該銅層150上，使該金層152為最外層。 Next, a plurality of metal portions 15 are formed on the electroplated copper layer 12 that does not cover the resist layer 14. The metal portion 15 is composed of a copper layer 150, a nickel layer 151, and a gold layer 152. The copper layer 150 is formed. Bonded to the electroplated copper layer 12, the nickel layer 151 is bonded to the copper layer 150 such that the gold layer 152 is the outermost layer.

如第1B圖所示，移除該阻層14及其下方之電鍍銅層12。 As shown in FIG. 1B, the resist layer 14 and the electroplated copper layer 12 thereunder are removed.

如第1C圖所示，利用該鎳層151與金層152作為蝕刻擋層，以蝕刻移除位於該金屬部15周圍之晶種層13，使該金屬部15電性連接各該電性接觸墊101。 As shown in FIG. 1C, the nickel layer 151 and the gold layer 152 are used as an etch stop layer to remove the seed layer 13 located around the metal portion 15 by etching, so that the metal portion 15 is electrically connected to each of the electrical contacts. Pad 101.

如第1D圖所示，於該矽板體10之第二表面10b上進行線路重佈層(Redistribution layer,RDL)製程，即先將該矽板體10之第一表面10a及金屬部15藉由黏著層160結合 至一承載件16上，再形成一線路重佈結構17於該矽板體10之第二表面10b上，且該線路重佈結構17係電性連接該導電穿孔100。 As shown in FIG. 1D, a redistribution layer (RDL) process is performed on the second surface 10b of the slab body 10, that is, the first surface 10a and the metal portion 15 of the slab body 10 are first borrowed. Combined by adhesive layer 160 To the carrier member 16, a line redistribution structure 17 is formed on the second surface 10b of the raft body 10, and the circuit redistribution structure 17 is electrically connected to the conductive via 100.

如第1E圖所示，利用隱形切割(stealth dicing,SD)方式進行切單製程，之後再移除該承載件16與該黏著層160，以獲取複數矽中介板1。具體地，先於該矽板體10內以雷射掃瞄形成內嵌切割線(即隱形切割)，再從該承載件16之處向上頂升，使該矽板體10沿該內嵌切割線斷裂，而形成複數矽中介板1，之後提供熱風予該黏著層160，使該黏著層160受熱擴張而呈緊繃狀，即可取出各該矽中介板1，以完成切單製程。 As shown in FIG. 1E, the singulation process is performed by a stealth dicing (SD) method, and then the carrier 16 and the adhesive layer 160 are removed to obtain a plurality of 矽 interposer 1. Specifically, an in-line cutting line (ie, invisible cutting) is formed by laser scanning in the slab body 10, and then lifted upward from the carrier member 16 to cut the slab body 10 along the in-line cutting. The wire breaks to form a plurality of ruthenium interposer 1 and then provides hot air to the adhesive layer 160, so that the adhesive layer 160 is thermally expanded to be tight, and each of the ruthenium interposer 1 can be taken out to complete the singulation process.

於後續應用中，如第1F圖所示，係將該矽中介板1應用至3D堆疊製程中，以製成一半導體封裝件1’。具體地，係將該矽中介板1之線路重佈結構17藉由複數導電元件170電性結合至間距較大之一封裝基板18之複數銲墊180上，並形成底膠181包覆該些導電元件170；而將間距較小之一半導體晶片19之複數電極墊190藉由複數導電元件15a覆晶結合至各該電性接觸墊101上，再形成底膠191包覆該些該導電元件15a。 In a subsequent application, as shown in Fig. 1F, the germanium interposer 1 is applied to a 3D stacking process to form a semiconductor package 1'. Specifically, the circuit redistribution structure 17 of the enamel interposer 1 is electrically coupled to the plurality of pads 180 of the package substrate 18 having a larger pitch by the plurality of conductive elements 170, and the underfill 181 is formed to cover the plurality of pads 180. The conductive element 170; and the plurality of electrode pads 190 of the semiconductor wafer 19 having a smaller pitch are flip-chip bonded to each of the electrical contact pads 101 by a plurality of conductive elements 15a, and then the underfill 191 is formed to cover the conductive elements 15a. .

如第1G圖所示，上述導電元件15a之製作係先於該金屬部15上形成含銲錫材料153之導電凸塊，再將該電極墊190對接該導電凸塊，之後回銲該銲錫材料153；其中，該導電凸塊之種類繁多，且為業界所熟知，故不詳加贅述與圖示。 As shown in FIG. 1G, the conductive element 15a is formed by forming a conductive bump containing the solder material 153 on the metal portion 15, and then the electrode pad 190 is butted to the conductive bump, and then the solder material 153 is reflowed. There are many types of conductive bumps, which are well known in the industry, and therefore are not described in detail.

惟，前述習知矽中介板1之製法中，於蝕刻該晶種層13時，會無效部分該金屬部15之銅層150，致使於該鎳層151與金層152下會形成底切(undercut)結構15’，如第1C圖所示，故於分離該矽中介板1與該承載件16後，如第1E圖所示，該底切結構15’下容易殘留黏著材160’，即使以清潔液體(如水)沖洗該矽中介板1以移除任何殘留物，該底切結構15’下仍會有殘膠(Glue Rsidue)。 However, in the above-described method of fabricating the interposer 1, when the seed layer 13 is etched, a portion of the copper layer 150 of the metal portion 15 is ineffective, so that an undercut is formed under the nickel layer 151 and the gold layer 152 ( The undercut structure 15' is as shown in FIG. 1C. Therefore, after separating the tantalum interposer 1 and the carrier 16, as shown in FIG. 1E, the undercut structure 15' easily retains the adhesive 160', even if The crucible interposer 1 is rinsed with a cleaning liquid such as water to remove any residue, and there is still a residual glue under the undercut structure 15'.

再者，由於該底切結構15’黏附有該黏著材160’，故於後續製程中，當形成具有銲錫材料153之導電凸塊時，殘留之黏著材160’會流至該導電凸塊與該金層152之間，如第1G圖所示，而使各該電性接觸墊101與該導電凸塊間的結合力不佳，致使該半導體晶片19與該矽中介板1之接合不佳及電性連結不良等問題，因而導致該半導體封裝件1’之良率不佳。 Furthermore, since the undercut structure 15' is adhered to the adhesive material 160', in the subsequent process, when the conductive bump having the solder material 153 is formed, the residual adhesive material 160' flows to the conductive bump and Between the gold layers 152, as shown in FIG. 1G, the bonding force between the electrical contact pads 101 and the conductive bumps is poor, resulting in poor bonding between the semiconductor wafer 19 and the germanium interposer 1. Problems such as poor electrical connection, resulting in poor yield of the semiconductor package 1'.

因此，如何克服上述習知技術之底切問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the undercut problem of the above-mentioned prior art has become a problem that is currently being solved.

鑑於上述習知技術之種種缺失，本發明係提供一種具電性連接結構之基板，係包括：板體，係具有複數電性接觸墊；第一鈍化層，係設於該板體上且覆蓋各該電性接觸墊之部分表面；第二鈍化層，係設於該第一鈍化層上且外露各該電性接觸墊；第一金屬層，係設於各該電性接觸墊與第一鈍化層上，並埋設於該第二鈍化層中，而未凸出該第二鈍化層；以及第二金屬層，係設於該第一金屬層上， 並凸出該第二鈍化層。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a substrate having an electrical connection structure, comprising: a plate body having a plurality of electrical contact pads; and a first passivation layer disposed on the plate body and covering a portion of the surface of each of the electrical contact pads; a second passivation layer disposed on the first passivation layer and exposing each of the electrical contact pads; a first metal layer disposed on each of the electrical contact pads and the first a passivation layer embedded in the second passivation layer without protruding the second passivation layer; and a second metal layer disposed on the first metal layer And protruding the second passivation layer.

前述之基板中，該板體係為非導體之板材。 In the aforementioned substrate, the plate system is a non-conductor plate.

前述之基板中，該板體復具有線路部，各該電性接觸墊形成於該線路部上，該第一鈍化層係設於該線路部上。 In the above substrate, the plate body has a line portion, and each of the electrical contact pads is formed on the line portion, and the first passivation layer is disposed on the line portion.

前述之基板中，該板體中復具有導電穿孔，各該電性接觸墊形成於該導電穿孔之孔端上。 In the above substrate, the plate body has conductive perforations, and each of the electrical contact pads is formed on the hole end of the conductive perforation.

前述之基板中，該第一金屬層與第二金屬層係構成凸塊底下金屬層。 In the above substrate, the first metal layer and the second metal layer constitute a under bump metal layer.

前述之基板中，該第一金屬層具有一延伸墊與一外接部，該延伸墊係設於各該電性接觸墊上，該外接部係設於該延伸墊上。 In the above substrate, the first metal layer has an extension pad and an external portion, and the extension pad is disposed on each of the electrical contact pads, and the external portion is disposed on the extension pad.

前述之基板中，該第一金屬層之材質不同於該第二金屬層之材質。 In the above substrate, the material of the first metal layer is different from the material of the second metal layer.

前述之基板中，該第一金屬層係為銅層，且該第二金屬層係為鎳層、金層或其二者之組合。 In the above substrate, the first metal layer is a copper layer, and the second metal layer is a nickel layer, a gold layer or a combination of the two.

前述之基板中，該第二金屬層之材質不同於該晶種層之材質。 In the above substrate, the material of the second metal layer is different from the material of the seed layer.

前述之基板中，復包括設於該金屬部與該導電穿孔之間的晶種層，且該第二金屬層之材質不同於該晶種層之材質，例如，該晶種層之材質係為鈦、銅或其二者之組合。 The substrate further includes a seed layer disposed between the metal portion and the conductive via, and the material of the second metal layer is different from the material of the seed layer. For example, the material of the seed layer is Titanium, copper or a combination of both.

前述之基板中，復包括設於該第二金屬層上之導電凸塊。例如，該導電凸塊係具有銲錫材料。 In the foregoing substrate, the conductive bumps provided on the second metal layer are further included. For example, the conductive bumps have a solder material.

前述之基板中，該第二鈍化層係對應位於各該電性接觸墊之部分表面之上方、或未對應位於各該電性接觸墊之 上方。 In the foregoing substrate, the second passivation layer is corresponding to a portion of the surface of each of the electrical contact pads, or is not corresponding to each of the electrical contact pads. Above.

本發明復提供一種具電性連接結構之基板之製法，係包括：提供一板體，該板體具有複數電性接觸墊、及設於該板體上且外露各該電性接觸墊之第一鈍化層；形成第二鈍化層於該第一鈍化層上，且該第二鈍化層具有對應外露各該電性接觸墊之複數開口；形成第一金屬層於該開口中之電性接觸墊上，且該第一金屬層埋設於該第一與第二鈍化層中，而未凸出該第二鈍化層；以及形成第二金屬層於該第一金屬層上，且該第二金屬層凸出該第二鈍化層。 The invention provides a method for manufacturing a substrate having an electrical connection structure, comprising: providing a plate body having a plurality of electrical contact pads, and providing the same on the plate body and exposing each of the electrical contact pads a passivation layer; a second passivation layer is formed on the first passivation layer, and the second passivation layer has a plurality of openings corresponding to the exposed respective electrical contact pads; forming a first metal layer on the electrical contact pads in the opening And the first metal layer is embedded in the first and second passivation layers without protruding the second passivation layer; and the second metal layer is formed on the first metal layer, and the second metal layer is convex The second passivation layer is removed.

前述之基板及其製法中，該第二鈍化層之厚度係大於該第一鈍化層之厚度。 In the foregoing substrate and the method of manufacturing the same, the thickness of the second passivation layer is greater than the thickness of the first passivation layer.

前述之製法中，復包括於形成該第一金屬層之前，形成晶種層於該第二鈍化層、開口之孔壁與各該電性接觸墊上，以於形成該第一金屬層後，令部分該晶種層設於該第一金屬層與各該電性接觸墊之間，且於形成該第二金屬層之後，移除該第二鈍化層上之晶種層。 In the above method, before forming the first metal layer, forming a seed layer on the second passivation layer, the opening hole wall and each of the electrical contact pads, to form the first metal layer, A portion of the seed layer is disposed between the first metal layer and each of the electrical contact pads, and after forming the second metal layer, removing the seed layer on the second passivation layer.

前述之製法中，該開口之徑寬大於、等於或小於該電性接觸墊之寬度。 In the above method, the opening has a diameter greater than, equal to, or less than the width of the electrical contact pad.

本發明亦提供一種具電性連接結構之基板之製法，係包括：提供一板體，該板體具有複數電性接觸墊、及設於該板體上且外露各該電性接觸墊之鈍化層；形成第一金屬層於各該電性接觸墊與部分該鈍化層上，且該第一金屬層具有無效部；形成第二金屬層於該第一金屬層上，且該第二金屬層未覆蓋於該無效部上；以及移除該無效部。 The invention also provides a method for manufacturing a substrate having an electrical connection structure, comprising: providing a plate body having a plurality of electrical contact pads, and providing passivation on the plate body and exposing each of the electrical contact pads Forming a first metal layer on each of the electrical contact pads and a portion of the passivation layer, and the first metal layer has an ineffective portion; forming a second metal layer on the first metal layer, and the second metal layer Not overwritten on the invalid portion; and the invalid portion is removed.

前述之製法中，復包括於形成該第一金屬層之前，形成晶種層於該鈍化層與各該電性接觸墊上，以於形成該第一金屬層時，令該部分晶種層位於該第一金屬層與各該電性接觸墊之間、及位於該第一金屬層與該鈍化層之間，且於移除該無效部時，一併移除該無效部下之晶種層。 In the above method, before forming the first metal layer, forming a seed layer on the passivation layer and each of the electrical contact pads, so that when the first metal layer is formed, the portion of the seed layer is located The first metal layer and each of the electrical contact pads are located between the first metal layer and the passivation layer, and when the ineffective portion is removed, the seed layer under the ineffective portion is removed.

本發明另提供一種具電性連接結構之基板之製法，係包括：提供一具有複數電性接觸墊之板體；形成一第一阻層於該板體上，且形成一第二阻層於該第一阻層上，其中，該第一阻層上形成有複數第一開口區，而該第二阻層上形成有複數連通該第一開口區之第二開口區，使該第一開口區之開口大於該第二開口區之開口，並使該些電性接觸墊外露於該些第一與第二開口區；形成第一金屬層於該第一開口區中，且該第一金屬層具有無效部；形成第二金屬層於該第一金屬層上，且該第二金屬層位於該第二開口中而未覆蓋於該無效部上；移除該第一與第二阻層；以及移除該無效部。 The invention further provides a method for manufacturing a substrate having an electrical connection structure, comprising: providing a plate body having a plurality of electrical contact pads; forming a first resist layer on the plate body, and forming a second resist layer The first resistive layer is formed with a plurality of first open regions, and the second resistive layer is formed with a plurality of second open regions communicating with the first open regions, such that the first opening The opening of the region is larger than the opening of the second opening region, and the electrical contact pads are exposed to the first and second opening regions; forming a first metal layer in the first opening region, and the first metal The layer has an ineffective portion; a second metal layer is formed on the first metal layer, and the second metal layer is located in the second opening without covering the ineffective portion; removing the first and second resist layers; And remove the invalid part.

前述之製法中，復包括於形成該第一與第二開口區之製程係包括：於形成該第二阻層之前，對該第一阻層進行第一次曝光作業，使部分該第一阻層形成第一曝光區；於形成該第二阻層之後，對該第二阻層進行第二次曝光作業，使部分該第二阻層形成第二曝光區；以及進行一次顯影作業，使該第一曝光區形成該第一開口區，且該第二曝光區形成該第二開口區。 In the foregoing method, the process of forming the first and second open regions includes: performing a first exposure operation on the first resist layer before forming the second resist layer, and partially causing the first resist Forming a first exposure region; after forming the second resist layer, performing a second exposure operation on the second resist layer to partially form the second resist layer to form a second exposure region; and performing a development operation to make the The first exposed area forms the first open area, and the second exposed area forms the second open area.

前述之製法中，復包括於形成該第一與第二開口區之 製程係包括：於形成該第二阻層之後，對該第一與第二阻層進行一次曝光作業，使部分該第一阻層形成第一曝光區，且部分該第二阻層形成第二曝光區；以及進行至少一次顯影作業，使該第一曝光區形成該第一開口區，且該第二曝光區形成該第二開口區。 In the foregoing manufacturing method, the complex is included in forming the first and second open regions The process includes: performing an exposure operation on the first and second resist layers after forming the second resist layer, such that a portion of the first resistive layer forms a first exposed region, and a portion of the second resistive layer forms a second portion And exposing the exposure zone; and performing at least one development operation such that the first exposure zone forms the first open area and the second exposure zone forms the second open area.

前述之製法中，復包括於形成該第一與第二開口區之製程係包括：於形成該第二阻層之前，對該第一阻層進行曝光作業，使部分該第一阻層形成第一曝光區；進行第一次顯影作業，使該第一曝光區形成該第一開口區；於形成該第二阻層之後，對該第二阻層進行曝光作業，使部分該第二阻層形成第二曝光區；以及進行第二次顯影作業，使該第二曝光區形成該第二開口區。 In the above manufacturing method, the process of forming the first and second open regions includes: performing an exposure operation on the first resist layer before forming the second resist layer, so that a portion of the first resist layer is formed a first development operation, the first exposure region is formed into the first opening region; after the second resist layer is formed, the second resist layer is exposed to expose a portion of the second resist layer Forming a second exposure zone; and performing a second development operation such that the second exposure zone forms the second open zone.

前述之製法中，復包括於形成該第一阻層之前，形成晶種層於各該電性接觸墊上，以於形成該第一金屬層時，令該部分晶種層位於該第一金屬層與各該電性接觸墊之間，且於移除該無效部時，一併移除該無效部下之晶種層。 In the above method, before the forming of the first resist layer, a seed layer is formed on each of the electrical contact pads, so that when the first metal layer is formed, the portion of the seed layer is located in the first metal layer. And between each of the electrical contact pads, and when the ineffective portion is removed, the seed layer under the ineffective portion is removed.

前述之三種製法中，移除該晶種層之方式係為蝕刻方式。 In the above three methods, the mode of removing the seed layer is an etching method.

前述之三種製法中，復包括於移除該晶種層後，形成導電凸塊於該第二金屬層上。 In the foregoing three methods, the method further comprises: after removing the seed layer, forming a conductive bump on the second metal layer.

由上可知，本發明之基板及其製法，可藉由第二鈍化層之設計，使該第一金屬層埋設於該第二鈍化層中，而未凸出該第二鈍化層，故於蝕刻該晶種層時，蝕刻液不會侵蝕該第一金屬層，因而該第二金屬層下方不會產生底切結 構。 It can be seen from the above that the substrate of the present invention and the method for fabricating the same can be embedded in the second passivation layer by the design of the second passivation layer without protruding the second passivation layer, so that etching is performed. In the seed layer, the etching solution does not erode the first metal layer, so that undercuts are not generated under the second metal layer. Structure.

或者，藉由該第一金屬層具有無效部之設計，以於蝕刻該晶種層時，該無效部能消耗蝕刻液，而避免蝕刻液過度蝕刻該第一金屬層，故能確保該第二金屬層下方不會產生底切結構。 Alternatively, the first metal layer has a design of an ineffective portion, so that when the seed layer is etched, the ineffective portion can consume the etching liquid, and the etching liquid is prevented from excessively etching the first metal layer, thereby ensuring the second portion. No undercut structure is created below the metal layer.

1‧‧‧矽中介板 1‧‧‧矽Intermediary board

1’‧‧‧半導體封裝件 1'‧‧‧Semiconductor package

10‧‧‧矽板體 10‧‧‧矽板

10a,20a‧‧‧第一表面 10a, 20a‧‧‧ first surface

10b,20b‧‧‧第二表面 10b, 20b‧‧‧ second surface

100,200‧‧‧導電穿孔 100,200‧‧‧Electrical perforation

101,201,401‧‧‧電性接觸墊 101,201,401‧‧‧Electrical contact pads

11,31‧‧‧鈍化層 11,31‧‧‧passivation layer

12‧‧‧電鍍銅層 12‧‧‧Electroplated copper layer

13,23‧‧‧晶種層 13,23‧‧‧ seed layer

14,24‧‧‧阻層 14,24‧‧‧resist

15,25,25’,25”,35‧‧‧金屬部 15,25,25’,25”,35‧‧Member

15’‧‧‧底切結構 15’‧‧‧ undercut structure

15a‧‧‧導電元件 15a‧‧‧Conducting components

150‧‧‧銅層 150‧‧‧ copper layer

151,251a,351a‧‧‧鎳層 151,251a, 351a‧‧‧ Nickel

152,251b,351b‧‧‧金層 152, 251b, 351b‧‧‧ gold layer

153,261‧‧‧銲錫材料 153,261‧‧‧ solder materials

16‧‧‧承載件 16‧‧‧Carrier

160‧‧‧黏著層 160‧‧‧Adhesive layer

160’‧‧‧黏著材 160’‧‧‧Adhesive

17‧‧‧線路重佈結構 17‧‧‧Line redistribution structure

170‧‧‧導電元件 170‧‧‧Conductive components

18‧‧‧封裝基板 18‧‧‧Package substrate

180‧‧‧銲墊 180‧‧‧ solder pads

181,191‧‧‧底膠 181,191‧‧‧Bottom glue

19‧‧‧半導體晶片 19‧‧‧Semiconductor wafer

190‧‧‧電極墊 190‧‧‧electrode pads

190a‧‧‧結合處 190a‧‧‧ joint office

2,3,4‧‧‧基板 2,3,4‧‧‧substrate

20,20’,20”,40‧‧‧板體 20,20’,20”,40‧‧‧ board

202‧‧‧板部 202‧‧‧ Board Department

203‧‧‧線路部 203‧‧‧Line Department

21‧‧‧第一鈍化層 21‧‧‧First passivation layer

210‧‧‧第一開口 210‧‧‧ first opening

22‧‧‧第二鈍化層 22‧‧‧Second passivation layer

220,220’,220”‧‧‧第二開口 220, 220’, 220” ‧ ‧ second opening

240‧‧‧開口區 240‧‧‧Open area

250,250’,250”,350‧‧‧第一金屬層 250, 250’, 250”, 350‧‧‧ first metal layer

250a‧‧‧延伸墊 250a‧‧‧Extension pad

250b‧‧‧外接部 250b‧‧‧External Department

251,251’,251”,351‧‧‧第二金屬層 251,251’,251”, 351‧‧‧second metal layer

26,26’‧‧‧導電凸塊 26,26’‧‧‧Electrical bumps

260‧‧‧塊體 260‧‧‧Block

310,X,Y‧‧‧開口 310, X, Y‧‧‧ openings

32,42‧‧‧第一阻層 32, 42‧‧‧ first resistance layer

320,420‧‧‧第一開口區 320, 420‧‧‧ first open area

34,44‧‧‧第二阻層 34,44‧‧‧second barrier

340,440‧‧‧第二開口區 340,440‧‧‧second open area

350a‧‧‧無效部 350a‧‧Invalid Department

42a‧‧‧第一曝光區 42a‧‧‧First exposure area

44a‧‧‧第二曝光區 44a‧‧‧Second exposure area

D,R‧‧‧孔徑 D, R‧‧‧ aperture

d,d’,d”,r‧‧‧徑寬 d, d’, d”, r‧‧ ‧ path width

t,h‧‧‧厚度 t, h‧‧‧ thickness

w,L‧‧‧寬度 w,L‧‧‧Width

第1A至1E圖係為習知矽中介板之製法的剖面示意圖；第1F圖係為習知半導體封裝件之剖面示意圖；第1G圖係為第1F圖之局部放大圖；第2A至2H圖係為本發明之具電性連接結構之基板之製法之第一實施例的剖面示意圖；其中，第2A’與2A”圖係為本發明之板體之不同態樣之剖面示意圖，第2C’及2C”圖係為第2G圖之其它實施例，第2G’及2G”圖係為第2G圖之其它實施例，第2H’圖係為第2H圖之另一實施例；第3A至3H圖係為本發明之具電性連接結構之基板之製法之第二實施例的剖面示意圖；第4A至4F圖係為本發明之具電性連接結構之基板之製法之第三實施例的剖面示意圖；其中，第4B’圖係為第4B圖之另一實施例；以及第5A至5D圖係為本發明之具電性連接結構之基板之製法之第四實施例的剖面示意圖。 1A to 1E are schematic cross-sectional views showing a conventional method for fabricating an interposer; FIG. 1F is a schematic cross-sectional view of a conventional semiconductor package; FIG. 1G is a partial enlarged view of FIG. 1F; and FIGS. 2A to 2H A cross-sectional view of a first embodiment of a method for fabricating a substrate having an electrical connection structure of the present invention; wherein the 2A' and 2A" drawings are schematic cross-sectional views of different aspects of the plate body of the present invention, 2C' And the 2C" diagram is another embodiment of the 2Gth diagram, the 2G' and 2G" diagrams are other embodiments of the 2Gth diagram, and the 2H' diagram is another embodiment of the 2Hth diagram; 3A to 3H BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4A to FIG. 4F are cross-sectional views showing a second embodiment of a method for manufacturing a substrate having an electrical connection structure according to the present invention; FIGS. 4A to 4F are cross-sectional views showing a third embodiment of a method for manufacturing a substrate having an electrical connection structure of the present invention. FIG. 4B is another embodiment of FIG. 4B; and FIGS. 5A to 5D are cross-sectional views showing a fourth embodiment of the method for fabricating a substrate having an electrical connection structure of the present invention.

以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The embodiments of the present invention are described below by way of specific embodiments. Other advantages and effects of the present invention will be readily apparent to those skilled in the art from this disclosure.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

第2A至2H圖係為本發明之具電性連接結構之基板2之製法之第一實施例的剖面示意圖，其中，該電性連接結構係具有凸塊底下金屬層(Under Bump Metallurgy,UBM)之功能。 2A to 2H are schematic cross-sectional views showing a first embodiment of a method for fabricating a substrate 2 having an electrical connection structure according to the present invention, wherein the electrical connection structure has an under bump metallurgy (UBM). The function.

如第2A圖所示，提供一板體20，該板體20具有相對之第一表面20a與第二表面20b、及設於該第一表面20a上之複數電性接觸墊201，且於該板體20之第一表面20a上形成有一第一鈍化層21，該第一鈍化層21具有複數第一開口210，以令各該電性接觸墊201外露於各該第一開口210。 As shown in FIG. 2A, a board body 20 is provided. The board body 20 has a first surface 20a and a second surface 20b opposite to each other, and a plurality of electrical contact pads 201 disposed on the first surface 20a. A first passivation layer 21 is formed on the first surface 20a of the board body 20. The first passivation layer 21 has a plurality of first openings 210 for exposing each of the electrical contact pads 201 to each of the first openings 210.

於本實施例中，該板體20係為非導體材之板材，且各 該電性接觸墊201係可為銅墊。 In this embodiment, the plate body 20 is a non-conductor material plate, and each The electrical contact pad 201 can be a copper pad.

再者，形成該第一鈍化層21之材質係為無機材質，如氧化矽(SiO2)、氮化矽(SixNy)等；或者，該第一鈍化層21之材質係為有機材質，如聚醯亞胺(Polyimide,PI)、聚對二唑苯(Polybenzoxazole,PBO)、苯環丁烯(Benzocyclclobutene,BCB)等。 Further, the material forming the first passivation layer 21 is an inorganic material such as cerium oxide (SiO 2 ), bismuth nitride (SixNy), or the like; or the material of the first passivation layer 21 is an organic material, such as poly Polyimide (PI), polybenzoxazole (PBO), Benzocycline butane (BCB), and the like.

又，該板體20之材質為半導體材，其可為玻璃板、矽中介板或矽晶圓；或者，該板體20之材質為陶瓷材料、絕緣材或複合材料，其可為封裝基板。 Moreover, the material of the plate body 20 is a semiconductor material, which may be a glass plate, a tantalum interposer or a tantalum wafer; or the material of the plate body 20 is a ceramic material, an insulating material or a composite material, which may be a package substrate.

具體地，以矽中介板為例，如第2A’圖所示，該板體20’復具有連通該第一表面20a與第二表面20b之複數導電穿孔200，且各該電性接觸墊201形成於該導電穿孔200之孔端上。 Specifically, as an example of the bismuth interposer, as shown in FIG. 2A', the board body 20' has a plurality of conductive vias 200 connecting the first surface 20a and the second surface 20b, and each of the electrical contact pads 201 Formed on the hole end of the conductive via 200.

或者，如第2A”圖所示，該板體20”復具有一板部202與設於該板部202上之線路部203，該板部202中具有複數導電穿孔200，且該線路部203電性連接該導電穿孔200，並使各該電性接觸墊201形成於該線路部203上，而該第一鈍化層21設於該線路部203上。其中，該線路部203係以進行線路重佈層(Redistribution layer,RDL)製程完成者。 Alternatively, as shown in FIG. 2A, the board 20" has a board portion 202 and a line portion 203 disposed on the board portion 202. The board portion 202 has a plurality of conductive vias 200 therein, and the line portion 203 The conductive vias 200 are electrically connected to each other, and the electrical contact pads 201 are formed on the line portion 203, and the first passivation layer 21 is disposed on the line portion 203. The line portion 203 is configured to perform a Redistribution Layer (RDL) process.

另外，該板體20之種類可依需求而設計，並不限於上述。 In addition, the type of the board 20 can be designed according to requirements, and is not limited to the above.

如第2B圖所示，形成一第二鈍化層22於該第一鈍化層21上，且該第二鈍化層22具有複數第二開口220，各 該第二開口220之孔徑D大於各該第一開口210之孔徑R，以令各該電性接觸墊210外露於各該第二開口220。 As shown in FIG. 2B, a second passivation layer 22 is formed on the first passivation layer 21, and the second passivation layer 22 has a plurality of second openings 220, each of which has a plurality of second openings 220. The aperture D of the second opening 220 is larger than the aperture R of each of the first openings 210 to expose each of the electrical contact pads 210 to each of the second openings 220.

於本實施例中，該第二鈍化層22之厚度t係大於該第一鈍化層21之厚度h，且該第二鈍化層22之厚度t係為1至5微米(um)。 In this embodiment, the thickness t of the second passivation layer 22 is greater than the thickness h of the first passivation layer 21, and the thickness t of the second passivation layer 22 is 1 to 5 micrometers (um).

再者，形成該第二鈍化層22之材質係為無機材質，如氧化矽(SiO2)、氮化矽(SixNy)等；或有機材質，如聚醯亞胺(Polyimide,PI)、聚對二唑苯(Polybenzoxazole,PBO)、苯環丁烯(Benzocyclclobutene,BCB)等。 Furthermore, the material forming the second passivation layer 22 is an inorganic material such as cerium oxide (SiO 2 ), cerium nitride (SixNy), or the like; or an organic material such as polyimide (PI), poly pair. Polybenzoxazole (PBO), Benzocycline butane (BCB), and the like.

又，該第一鈍化層21之材質與第二鈍化層22之材質可為相同或不相同。 Moreover, the material of the first passivation layer 21 and the material of the second passivation layer 22 may be the same or different.

如第2C圖所示，形成一晶種層(seed layer)23於該第二鈍化層22、該第二開口220之孔壁、該第一開口210之孔壁與各該電性接觸墊201上。 As shown in FIG. 2C, a seed layer 23 is formed on the second passivation layer 22, the hole wall of the second opening 220, the hole wall of the first opening 210, and each of the electrical contact pads 201. on.

於本實施例中，該晶種層23之材質係為鈦、銅或其二者之組合。 In the present embodiment, the material of the seed layer 23 is titanium, copper or a combination of the two.

再者，該第二開口220之徑寬d大於該電性接觸墊201之寬度L，使該第二鈍化層22未對應位於各該電性接觸墊201之上方。 Moreover, the diameter d of the second opening 220 is greater than the width L of the electrical contact pad 201, so that the second passivation layer 22 is not correspondingly located above each of the electrical contact pads 201.

又，於其它實施例中，該第二鈍化層22係對應位於各該電性接觸墊201之部分表面之上方。具體地，如第2C’圖所示，該第二開口220’之徑寬d’小於該電性接觸墊201之寬度L；或者，該第二開口220”之徑寬d”等於該電性接觸墊201之寬度L，如第2C”圖所示。 Moreover, in other embodiments, the second passivation layer 22 corresponds to a portion of the surface of each of the electrical contact pads 201. Specifically, as shown in FIG. 2C', the diameter d' of the second opening 220' is smaller than the width L of the electrical contact pad 201; or the diameter d" of the second opening 220" is equal to the electrical The width L of the contact pad 201 is as shown in the 2Cth view.

如第2D圖所示，形成一阻層24於該第二鈍化層22上之晶種層23上，且該阻層24未覆蓋該第二開口220。 As shown in FIG. 2D, a resist layer 24 is formed on the seed layer 23 on the second passivation layer 22, and the resist layer 24 does not cover the second opening 220.

於本實施例中，該阻層24具有對應該第二開口220之開口區240，且該開口區240之徑寬r等於或略大於該第二開口220之徑寬d。 In the embodiment, the resist layer 24 has an open area 240 corresponding to the second opening 220, and the diameter r of the open area 240 is equal to or slightly larger than the diameter d of the second opening 220.

如第2E圖所示，形成複數金屬部25於各該第二開口220中，使該金屬部25電性連接各該電性接觸墊201與導電穿孔200。 As shown in FIG. 2E, a plurality of metal portions 25 are formed in each of the second openings 220, and the metal portions 25 are electrically connected to the electrical contact pads 201 and the conductive vias 200.

於本實施例中，該金屬部25係由相疊之第一金屬層250與第二金屬層251所構成，故具有凸塊底下金屬層(Under Bump Metallurgy,UBM)之功能。具體地，先形成該第一金屬層250於該第二開口220中之電性接觸墊201之晶種層23上，再形成該第二金屬層251於該第一金屬層250上。 In the present embodiment, the metal portion 25 is composed of the first metal layer 250 and the second metal layer 251 which are stacked, and thus has the function of an Under Bump Metallurgy (UBM). Specifically, the first metal layer 250 is formed on the seed layer 23 of the electrical contact pad 201 in the second opening 220, and the second metal layer 251 is formed on the first metal layer 250.

再者，該第一金屬層250之材質不同於該第二金屬層251之材質。具體地，該第一金屬層250係為銅層，該第二金屬層251係由一鎳層251a與一金層251b所構成，且該鎳層251a結合至該第一金屬層250上，而該金層251b結合至該鎳層251a上。 Furthermore, the material of the first metal layer 250 is different from the material of the second metal layer 251. Specifically, the first metal layer 250 is a copper layer, and the second metal layer 251 is composed of a nickel layer 251a and a gold layer 251b, and the nickel layer 251a is bonded to the first metal layer 250. The gold layer 251b is bonded to the nickel layer 251a.

又，該晶種層23之材質可與該第一金屬層250之材質相同。 Moreover, the material of the seed layer 23 can be the same as the material of the first metal layer 250.

如第2F至2G圖所示，先剝離移除該阻層24，再移除其下之晶種層23(即該第二鈍化層22上之晶種層23)，且該金屬部25凸出該第二鈍化層22。 As shown in FIGS. 2F to 2G, the resist layer 24 is stripped and removed, and the seed layer 23 (ie, the seed layer 23 on the second passivation layer 22) is removed, and the metal portion 25 is convex. The second passivation layer 22 is exited.

於本實施例中，該第一金屬層250係埋設於該第一與第二鈍化層21,22中，而未凸出該第二鈍化層22，而該第二金屬層251係凸出該第二鈍化層22。 In this embodiment, the first metal layer 250 is embedded in the first and second passivation layers 21, 22, and the second passivation layer 22 is not protruded, and the second metal layer 251 is protruded. The second passivation layer 22 is.

再者，移除該晶種層23之方式係為蝕刻方式，且由於該第二金屬層251之材質不同於該晶種層23之材質，故可利用該第二金屬層251作為蝕刻擋層，以蝕刻移除位於該金屬部25周圍之晶種層23，而不會蝕刻移除該第二金屬層251。 Moreover, the manner of removing the seed layer 23 is an etching method, and since the material of the second metal layer 251 is different from the material of the seed layer 23, the second metal layer 251 can be used as an etch stop layer. The seed layer 23 located around the metal portion 25 is removed by etching without removing the second metal layer 251 by etching.

又，若接續第2C’及2C”圖之製程，將改變該金屬部25’,25”之尺寸，即該第一金屬層250’,250”與該第二金屬層251’,251”之尺寸，如第2G’及2G”圖所示。 Moreover, if the processes of the 2C' and 2C" are continued, the dimensions of the metal portions 25', 25", that is, the first metal layers 250', 250" and the second metal layers 251', 251" will be changed. Dimensions, as shown in Figures 2G' and 2G.

另外，於其它實施例中，如第2G”圖所示，當各該電性接觸墊201係為鋁材時，該第一金屬層250”亦可具有一延伸墊250a與一外接部250b，該延伸墊250a係設於各該電性接觸墊201上，該外接部250b係設於該延伸墊250a上。 In addition, in other embodiments, as shown in FIG. 2G", when each of the electrical contact pads 201 is made of aluminum, the first metal layer 250" may have an extension pad 250a and an external portion 250b. The extension pad 250a is disposed on each of the electrical contact pads 201, and the external connection portion 250b is disposed on the extension pad 250a.

如第2H圖所示，形成導電凸塊26於該金屬部25上，且該導電凸塊26係為銲錫球。 As shown in FIG. 2H, a conductive bump 26 is formed on the metal portion 25, and the conductive bump 26 is a solder ball.

再者，該導電凸塊26’亦可具有設於該第二金屬層251上之塊體260與設於該塊體260上之銲錫材料261，如第2H’圖所示。 Furthermore, the conductive bumps 26' may have a block 260 disposed on the second metal layer 251 and a solder material 261 disposed on the block 260, as shown in the second H'.

又，所述之電性連接結構係至少包含該金屬部25與各該電性接觸墊201。 Moreover, the electrical connection structure includes at least the metal portion 25 and each of the electrical contact pads 201.

另外，於後續製程中，將該基板2應用至封裝製程中。 若該板體20係為中介板，復可於該板體20之第二表面20b上進行線路重佈層(Redistribution layer,RDL)製程，即形成一線路重佈結構(圖略，可參考第1D圖之線路重佈結構17)於該板體20之第二表面20b上，且該線路重佈結構係電性連接該導電穿孔200。 In addition, the substrate 2 is applied to the packaging process in a subsequent process. If the board body 20 is an interposer, a circuit re-distribution layer (RDL) process can be performed on the second surface 20b of the board body 20, that is, a line re-distribution structure is formed. The line redistribution structure 17 of the 1D diagram is on the second surface 20b of the board body 20, and the line redistribution structure is electrically connected to the conductive via 200.

本實施例之製法中，藉由該第二鈍化層22之設計，使該第一金屬層250,250’,250”埋設於該第二鈍化層22中，而未凸出該第二鈍化層22，故於蝕刻該金屬部25周圍之晶種層23時，蝕刻液不會向下侵蝕該第一金屬層250,250’,250”，因而該第二金屬層251,251’,251”下方不會產生底切結構。 In the manufacturing method of the embodiment, the first metal layer 250, 250', 250" is buried in the second passivation layer 22 by the design of the second passivation layer 22, and the second passivation layer 22 is not protruded. Therefore, when etching the seed layer 23 around the metal portion 25, the etching liquid does not erodes the first metal layer 250, 250', 250" downward, so that no undercut occurs under the second metal layer 251, 251', 251". structure.

第3A至3H圖係為本發明之基板3之製法之第二實施例的剖面示意圖。 3A to 3H are schematic cross-sectional views showing a second embodiment of the method of manufacturing the substrate 3 of the present invention.

如第3A圖所示，可參照第2A圖之結構，於該板體20之第一表面20a上僅形成有一鈍化層31，且該鈍化層31具有複數開口310，以令各該電性接觸墊201外露於各該開口310。接著，形成一晶種層23於該鈍化層31、該開口310之孔壁與各該電性接觸墊201上。 As shown in FIG. 3A, referring to the structure of FIG. 2A, only one passivation layer 31 is formed on the first surface 20a of the board body 20, and the passivation layer 31 has a plurality of openings 310 for making each electrical contact. The pad 201 is exposed to each of the openings 310. Next, a seed layer 23 is formed on the passivation layer 31, the hole wall of the opening 310, and each of the electrical contact pads 201.

如第3B圖所示，形成一第一阻層32於該晶種層23上，且該第一阻層32具有複數第一開口區320，以外露部分該晶種層23。 As shown in FIG. 3B, a first resist layer 32 is formed on the seed layer 23, and the first resist layer 32 has a plurality of first open regions 320, and the seed layer 23 is exposed.

如第3C圖所示，形成一第一金屬層350於該第一開口區320中，且該第一金屬層350結合至該晶種層23上。 As shown in FIG. 3C, a first metal layer 350 is formed in the first opening region 320, and the first metal layer 350 is bonded to the seed layer 23.

於本實施例中，該第一金屬層350係為銅層，且該第 一金屬層350具有無效部350a(如圖之虛線範圍)，該無效部350a係為特定形成之部分，以於發生底切效應時，可供移除之。 In this embodiment, the first metal layer 350 is a copper layer, and the first A metal layer 350 has an ineffective portion 350a (as shown by the dashed line in the figure), and the ineffective portion 350a is a specially formed portion for removal when an undercut effect occurs.

如第3D圖所示，移除該第一阻層32。 The first resist layer 32 is removed as shown in FIG. 3D.

如第3E圖所示，形成一第二阻層34於該晶種層23與該第一金屬層350上，且該第二阻層34具有複數第二開口區340，以令該第一金屬層350之部分表面外露於該第二開口區340。 As shown in FIG. 3E, a second resist layer 34 is formed on the seed layer 23 and the first metal layer 350, and the second resist layer 34 has a plurality of second open regions 340 to make the first metal. A portion of the surface of layer 350 is exposed to the second open area 340.

如第3F圖所示，形成一第二金屬層351於該第二開口區340中之第一金屬層350上，且該第二金屬層351未覆蓋於該無效部350a上。 As shown in FIG. 3F, a second metal layer 351 is formed on the first metal layer 350 in the second opening region 340, and the second metal layer 351 is not covered on the ineffective portion 350a.

於本實施例中，該第二金屬層351係由一鎳層351a與一金層351b所構成，且該鎳層351a結合至該第一金屬層350上，而該金層351b結合至該鎳層351a上。 In this embodiment, the second metal layer 351 is composed of a nickel layer 351a and a gold layer 351b, and the nickel layer 351a is bonded to the first metal layer 350, and the gold layer 351b is bonded to the nickel. On layer 351a.

如第3G至3H圖所示，先移除該第二阻層34，再移除其下之該第一金屬層350與該晶種層23(即該鈍化層31上之晶種層23)，使相疊之該第一與第二金屬層350,351作為金屬部35，且各該金屬部35係電性連接各該電性接觸墊201與導電穿孔200。 As shown in FIGS. 3G to 3H, the second resist layer 34 is removed first, and the first metal layer 350 and the seed layer 23 (ie, the seed layer 23 on the passivation layer 31) are removed. The first and second metal layers 350, 351 are stacked as the metal portion 35, and each of the metal portions 35 is electrically connected to each of the electrical contact pads 201 and the conductive vias 200.

於本實施例中，移除該晶種層23之方式係為蝕刻方式，且由於該第二金屬層351之材質不同於該晶種層23之材質，故可利用該第二金屬層351作為蝕刻擋層，以蝕刻移除位於該金屬部35周圍之晶種層23，而不會蝕刻移除該第二金屬層351。 In this embodiment, the mode of removing the seed layer 23 is an etching method, and since the material of the second metal layer 351 is different from the material of the seed layer 23, the second metal layer 351 can be used as the etching. The barrier layer is etched to remove the seed layer 23 located around the metal portion 35 without etching to remove the second metal layer 351.

再者，於移除該第二阻層34後，由於該第二金屬層351未覆蓋於該無效部350a上，使該無效部350a會外露於該第二金屬層351之周圍，故於蝕刻該晶種層23時，將一併蝕刻該無效部350a，藉以能避免該第二金屬層351下方形成底切結構之情況。具體地，於該第二金屬層351各側中，該無效部350a之寬度w之較佳值為1微米(um)，如第3G圖所示，且該寬度w之範圍可為0.5微米≦2w≦20微米，以作為蝕刻該金屬部35以外之銅材的底切內縮量。 Moreover, after the second resist layer 34 is removed, since the second metal layer 351 is not covered on the ineffective portion 350a, the ineffective portion 350a is exposed around the second metal layer 351, so etching is performed. In the case of the seed layer 23, the ineffective portion 350a is collectively etched, whereby the undercut structure under the second metal layer 351 can be avoided. Specifically, in each side of the second metal layer 351, a preferred value of the width w of the ineffective portion 350a is 1 micrometer (um), as shown in FIG. 3G, and the width w can be 0.5 micrometer. 2w ≦ 20 μm as the undercut shrinkage amount of the copper material other than the metal portion 35 is etched.

之後，形成導電凸塊(圖略，可參考第2H圖)於該金屬部35上，再將該基板3應用至封裝製程中，其中，該電性連接結構係至少包含該金屬部35與各該電性接觸墊201。 Then, a conductive bump (not shown in FIG. 2H) is formed on the metal portion 35, and the substrate 3 is applied to the packaging process, wherein the electrical connection structure includes at least the metal portion 35 and each The electrical contact pad 201.

本實施例之製法中，藉由先形成較大佈設範圍之第一金屬層350，使該第一金屬層350具有無效部350a，再形成較小佈設範圍之第二金屬層351，以於蝕刻該晶種層23時，該無效部350a能消耗蝕刻液，而避免蝕刻液過度蝕刻該第一金屬層350，因而能確保該第二金屬層351下方不會產生底切結構，故使該金屬部35之完整性符合要求。 In the manufacturing method of the embodiment, the first metal layer 350 has an ineffective portion 350a by forming a first metal layer 350 having a larger layout range, and a second metal layer 351 having a smaller layout range is formed to be etched. In the seed layer 23, the ineffective portion 350a can consume the etching liquid, and the etching liquid is prevented from over-etching the first metal layer 350, thereby ensuring that the undercut structure is not formed under the second metal layer 351, so that the metal is The integrity of Part 35 meets the requirements.

第4A至4F圖係為本發明之基板4之製法之第三實施例的剖面示意圖。本實施例係為第二實施例之另一應用。 4A to 4F are schematic cross-sectional views showing a third embodiment of the method of manufacturing the substrate 4 of the present invention. This embodiment is another application of the second embodiment.

如第4A圖所示，提供一具有複數電性接觸墊401之板體40，且該些電性接觸墊401上已形成有凸塊底下金屬層(Under Bump Metallurgy,UBM)，並選擇性形成晶種層 23於該板體40與各該電性接觸墊401上。於本實施例中，該板體40為矽晶圓。 As shown in FIG. 4A, a board 40 having a plurality of electrical contact pads 401 is provided, and the underlying bump metallurgy (UBM) is formed on the electrical contact pads 401 and selectively formed. Seed layer 23 is on the board 40 and each of the electrical contact pads 401. In this embodiment, the board 40 is a germanium wafer.

接著，形成一第一阻層42於該板體40上(即該晶種層23上)，且該第一阻層42覆蓋該些電性接觸墊401，再對該第一阻層42進行第一次曝光作業，使部分該第一阻層42形成第一曝光區42a。之後，對該第一阻層42進行如烘烤之固化製程。 Then, a first resist layer 42 is formed on the board 40 (ie, the seed layer 23), and the first resist layer 42 covers the electrical contact pads 401, and then the first resist layer 42 is performed. The first exposure operation causes a portion of the first resist layer 42 to form the first exposed region 42a. Thereafter, the first resist layer 42 is subjected to a curing process such as baking.

如第4B圖所示，形成一第二阻層44於該第一阻層42上。接著，對該第二阻層44進行第二次曝光作業，使部分該第二阻層44形成第二曝光區44a。 As shown in FIG. 4B, a second resist layer 44 is formed on the first resist layer 42. Next, the second resist layer 44 is subjected to a second exposure operation to partially form the second resist layer 44 to form the second exposed region 44a.

如第4C圖所示，進行一次顯影作業，使該第一曝光區42a形成第一開口區420，且該第二曝光區44a形成該第二開口區440。 As shown in FIG. 4C, a developing operation is performed such that the first exposure region 42a forms a first opening region 420, and the second exposure region 44a forms the second opening region 440.

於本實施例中，該第一開口區420連通該第二開口區440，且該第一開口區420之開口X大於該第二開口區440之開口Y，並使該些電性接觸墊401(或其上之晶種層23)外露於該些第一與第二開口區420,440。 In the embodiment, the first open area 420 is connected to the second open area 440, and the opening X of the first open area 420 is larger than the opening Y of the second open area 440, and the electrical contact pads 401 are (or a seed layer 23 thereon) is exposed to the first and second open regions 420, 440.

再者，於另一方式中，亦可使用不同光阻(如該第一阻層42與第二阻層44具不同顯影特性)，於形成該第二阻層44之後，再一併對該第一與第二阻層42,44進行一次曝光作業，如第4B’圖所示，之後於相同曝光時間下，可一次顯影形成如第4C圖所示之該些第一與第二開口區420,440；或者，當如第4B’圖所示之對該第一與第二阻層42,44進行一次曝光作業之後，若該第一阻層42與第二阻 層44具相同顯影特性，可進行兩次顯影作業，以先形成該些第二開口區440，再形成該些第一開口區420。 In another aspect, different photoresists (eg, the first resistive layer 42 and the second resistive layer 44 have different developing characteristics) may be used, and after the second resistive layer 44 is formed, The first and second resist layers 42, 44 perform an exposure operation, as shown in FIG. 4B', and then, at the same exposure time, the first and second open regions as shown in FIG. 4C can be formed at one time. 420, 440; or, after performing an exposure operation on the first and second resist layers 42, 44 as shown in FIG. 4B', if the first resist layer 42 and the second resist The layer 44 has the same development characteristics and can be subjected to two development operations to form the second open regions 440 and then form the first open regions 420.

如第4D圖所示，形成一第一金屬層350於該第一開口區420中，且該第一金屬層350結合至該晶種層23上。接著，形成第二金屬層351於該第一金屬層350上，且該第二金屬層351位於該第二開口區440中。 As shown in FIG. 4D, a first metal layer 350 is formed in the first opening region 420, and the first metal layer 350 is bonded to the seed layer 23. Next, a second metal layer 351 is formed on the first metal layer 350, and the second metal layer 351 is located in the second opening region 440.

於本實施例中，該第一金屬層350係為銅層，且該第一金屬層350具有無效部350a(如圖之虛線範圍)。 In the embodiment, the first metal layer 350 is a copper layer, and the first metal layer 350 has an ineffective portion 350a (as shown by the dashed line).

再者，該第二金屬層351未覆蓋於該無效部350a上，且該第二金屬層351係由一鎳層351a與一金層351b所構成，且該鎳層351a結合至該第一金屬層350上，而該金層351b結合至該鎳層351a上。 Furthermore, the second metal layer 351 is not covered on the ineffective portion 350a, and the second metal layer 351 is composed of a nickel layer 351a and a gold layer 351b, and the nickel layer 351a is bonded to the first metal. On layer 350, the gold layer 351b is bonded to the nickel layer 351a.

如第4E圖所示，移除該第一與第二阻層42,44。 The first and second resistive layers 42, 44 are removed as shown in FIG. 4E.

如第4F圖所示，移除該無效部350a與其下之晶種層23，使相疊之該第一與第二金屬層350,351作為金屬部35。 As shown in FIG. 4F, the ineffective portion 350a and the underlying seed layer 23 are removed such that the first and second metal layers 350, 351 are stacked as the metal portion 35.

於本實施例中，移除該晶種層23之方式係為蝕刻方式，且由於該第二金屬層351之材質不同於該晶種層23之材質，故可利用該第二金屬層351作為蝕刻擋層，以蝕刻移除位於該金屬部35周圍之晶種層23，而不會蝕刻移除該第二金屬層351。 In this embodiment, the mode of removing the seed layer 23 is an etching method, and since the material of the second metal layer 351 is different from the material of the seed layer 23, the second metal layer 351 can be used as the etching. The barrier layer is etched to remove the seed layer 23 located around the metal portion 35 without etching to remove the second metal layer 351.

再者，於移除該第二阻層44後，如第4E圖所示，由於該第二金屬層351未覆蓋於該無效部350a上，使該無效部350a會外露於該第二金屬層351之周圍，故於蝕刻該晶種層23與該無效部350a時，能避免該第二金屬層351下 方形成底切結構之情況。具體地，於該第二金屬層351各側中，該無效部350a之寬度w之較佳值為1微米(um)，如第4E圖所示，且該寬度w之範圍可為0.5微米≦2w≦20微米，以作為蝕刻該金屬部35以外之銅材的底切內縮量。 After the second resist layer 44 is removed, as shown in FIG. 4E, since the second metal layer 351 is not covered on the ineffective portion 350a, the ineffective portion 350a is exposed to the second metal layer. Around the 351, when the seed layer 23 and the ineffective portion 350a are etched, the second metal layer 351 can be avoided. The square forms the undercut structure. Specifically, in each side of the second metal layer 351, a preferred value of the width w of the ineffective portion 350a is 1 micrometer (um), as shown in FIG. 4E, and the width w can be 0.5 micrometer. 2w ≦ 20 μm as the undercut shrinkage amount of the copper material other than the metal portion 35 is etched.

之後，形成導電凸塊(圖略，可參考第2H圖)於該金屬部35上，再將該基板4應用至封裝製程中。 Thereafter, conductive bumps (not shown in FIG. 2H) are formed on the metal portion 35, and the substrate 4 is applied to the packaging process.

本實施例之製法中，藉由該第一開口區420之開口X大於該第二開口區440之開口Y，使該第一金屬層350具有無效部350a，以於蝕刻該晶種層23與該無效部350a時，能避免蝕刻液過度蝕刻該第一金屬層350，因而能確保該第二金屬層351下方不會產生底切結構。 In the manufacturing method of the embodiment, the first metal layer 350 has an ineffective portion 350a by the opening X of the first opening region 420 being larger than the opening Y of the second opening region 440, so as to etch the seed layer 23 and In the case of the ineffective portion 350a, the etching solution can be prevented from over-etching the first metal layer 350, so that the undercut structure can be prevented from occurring under the second metal layer 351.

第5A至5D圖係為本發明之基板之製法之第四實施例的剖面示意圖。本實施例係為第三實施例之另一應用。 5A to 5D are schematic cross-sectional views showing a fourth embodiment of the method of manufacturing the substrate of the present invention. This embodiment is another application of the third embodiment.

如第5A圖所示，係提供第4A圖之結構。 As shown in Fig. 5A, the structure of Fig. 4A is provided.

如第5B圖所示，進行第一次顯影作業，使該第一曝光區42a形成第一開口區420。 As shown in Fig. 5B, the first development operation is performed such that the first exposure region 42a forms the first opening region 420.

如第5C圖所示，形成一第二阻層44於該第一阻層42上。接著，對該第二阻層44進行曝光作業，使部分該第二阻層44形成第二曝光區44a。 As shown in FIG. 5C, a second resist layer 44 is formed on the first resist layer 42. Next, the second resist layer 44 is exposed to expose a portion of the second resist layer 44 to form a second exposed region 44a.

如第5D圖所示，進行第二次顯影作業，使該第二曝光區44a形成該第二開口區440。後續製程如同第4D至4F圖所述之製程，故不再贅述。 As shown in Fig. 5D, a second development operation is performed to cause the second exposure region 44a to form the second opening region 440. The subsequent processes are as described in the 4D to 4F drawings, and therefore will not be described again.

本發明係提供一種具電性連接結構之基板2，係包 括：一板體20,20’,20”、一第一鈍化層21、一第二鈍化層22、一晶種層23、第一金屬層250,250’,250”以及第二金屬層251,251’,251”。 The invention provides a substrate 2 with an electrical connection structure, a package a plate body 20, 20', 20", a first passivation layer 21, a second passivation layer 22, a seed layer 23, a first metal layer 250, 250', 250" and a second metal layer 251, 251', 251”.

所述之板體20,20’,20”係為非導體之板材，其具有相對之第一表面20a與第二表面20b、及設於該第一表面20a上之電性接觸墊201。 The plate body 20, 20', 20" is a non-conductor plate having a first surface 20a and a second surface 20b opposite thereto, and an electrical contact pad 201 disposed on the first surface 20a.

所述之第一鈍化層21係設於該板體20,20’,20”之第一表面20a上，且該第一鈍化層21外露各該電性接觸墊201。 The first passivation layer 21 is disposed on the first surface 20a of the board 20, 20', 20", and the first passivation layer 21 exposes each of the electrical contact pads 201.

所述之第二鈍化層22係設於該第一鈍化層21上，且該第二鈍化層22外露各該電性接觸墊201。 The second passivation layer 22 is disposed on the first passivation layer 21 , and the second passivation layer 22 exposes each of the electrical contact pads 201 .

所述之第一金屬層250,250’,250”係設於各該電性接觸墊201與該第一鈍化層21上，並埋設於該第二鈍化層22中，而未凸出該第二鈍化層22。 The first metal layer 250, 250', 250" is disposed on each of the electrical contact pads 201 and the first passivation layer 21, and is buried in the second passivation layer 22 without protruding the second passivation. Layer 22.

所述之第二金屬層251,251’,251”係設於該第一金屬層250,250’,250”上，並凸出該第二鈍化層22，且該第一金屬層250,250’,250”與第二金屬層251,251’,251”係構成凸塊底下金屬層。 The second metal layer 251, 251', 251" is disposed on the first metal layer 250, 250', 250", and protrudes the second passivation layer 22, and the first metal layer 250, 250', 250" and The two metal layers 251, 251', 251" constitute a metal layer under the bump.

所述之晶種層23係設於該第一金屬層250,250’,250”與各該電性接觸墊201之間、及該第一金屬層250,250’,250”與該第一鈍化層21之間，且該晶種層23之材質係為鈦、銅或其二者之組合。 The seed layer 23 is disposed between the first metal layer 250, 250', 250" and each of the electrical contact pads 201, and the first metal layer 250, 250', 250" and the first passivation layer 21 The material of the seed layer 23 is titanium, copper or a combination of both.

於一實施例中，該板體20’,20”中復具有複數連通該第一表面20a與第二表面20b之導電穿孔200，各該電性接觸墊201形成於該導電穿孔200之孔端上。 In one embodiment, the board body 20', 20" has a plurality of conductive vias 200 connecting the first surface 20a and the second surface 20b, and the electrical contact pads 201 are formed at the hole ends of the conductive vias 200. on.

於一實施例中，該板體20”復具有線路部203，各該電性接觸墊201形成於該線路部203上，且該第一鈍化層21係設於該線路部203上。 In one embodiment, the board body 20 ′′ has a line portion 203 , and each of the electrical contact pads 201 is formed on the line portion 203 , and the first passivation layer 21 is disposed on the line portion 203 .

於一實施例中，該第二鈍化層22之厚度t係大於該第一鈍化層21之厚度h。 In one embodiment, the thickness t of the second passivation layer 22 is greater than the thickness h of the first passivation layer 21 .

於一實施例中，該第一金屬層250”具有一延伸墊250a與一外接部250b，該延伸墊250a係設於各該電性接觸墊201上，且該外接部250b係設於該延伸墊250a上。 In one embodiment, the first metal layer 250 ” has an extension pad 250 a and an outer portion 250 b . The extension pad 250 a is disposed on each of the electrical contact pads 201 , and the external portion 250 b is disposed on the extension. On pad 250a.

於一實施例中，該第一金屬層250,250’,250”之材質不同於該第二金屬層251,251’,251”之材質。 In one embodiment, the material of the first metal layer 250, 250', 250" is different from the material of the second metal layer 251, 251', 251".

於一實施例中，該第二金屬層251,251’,251”之材質不同於該晶種層23之材質。 In one embodiment, the material of the second metal layer 251, 251', 251" is different from the material of the seed layer 23.

於一實施例中，該第一金屬層250,250’,250”係為銅層，且該第二金屬層251,251’,251”係為鎳層251a、金層251b或其二者之組合。 In one embodiment, the first metal layer 250, 250', 250" is a copper layer, and the second metal layer 251, 251', 251" is a nickel layer 251a, a gold layer 251b, or a combination thereof.

於一實施例中，該基板2復包括設於該第二金屬層251,251’,251”上之導電凸塊26,26’，且該導電凸塊26,26’係具有銲錫材料。 In one embodiment, the substrate 2 includes conductive bumps 26, 26' disposed on the second metal layer 251, 251', 251", and the conductive bumps 26, 26' have a solder material.

於一實施例中，該第二鈍化層22係未位於各該電性接觸墊201之上方。 In an embodiment, the second passivation layer 22 is not located above each of the electrical contact pads 201.

於一實施例中，該第二鈍化層22係對應位於各該電性接觸墊201之部分表面之上方。 In an embodiment, the second passivation layer 22 is located above a portion of the surface of each of the electrical contact pads 201.

綜上所述，本發明之基板及其製法，由於該金屬部不會形成底切結構，故於後續製程中，該電性連接結構不會 殘留黏著材或其它物質於該金屬部上，以於該半導體晶片覆晶結合至各該電性接觸墊時，各該電性接觸墊與該導電凸塊間的結合性良好，因而該半導體晶片與各該電性接觸墊間之電性連結良好，進而有效提升半導體封裝件之良率。 In summary, the substrate of the present invention and the method for manufacturing the same, since the metal portion does not form an undercut structure, the electrical connection structure does not occur in the subsequent process. Residual adhesive or other material on the metal portion, so that when the semiconductor wafer is crystal-bonded to each of the electrical contact pads, the bonding between the electrical contact pads and the conductive bumps is good, and thus the semiconductor wafer The electrical connection with each of the electrical contact pads is good, thereby effectively improving the yield of the semiconductor package.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

20‧‧‧板體 20‧‧‧ board

20a‧‧‧第一表面 20a‧‧‧ first surface

20b‧‧‧第二表面 20b‧‧‧second surface

201‧‧‧電性接觸墊 201‧‧‧Electrical contact pads

21‧‧‧第一鈍化層 21‧‧‧First passivation layer

22‧‧‧第二鈍化層 22‧‧‧Second passivation layer

23‧‧‧晶種層 23‧‧‧ seed layer

25‧‧‧金屬部 25‧‧‧Metal Department

250‧‧‧第一金屬層 250‧‧‧First metal layer

251‧‧‧第二金屬層 251‧‧‧Second metal layer

251a‧‧‧鎳層 251a‧‧‧ Nickel layer

251b‧‧‧金層 251b‧‧‧ gold layer

Claims (34)

一種具電性連接結構之基板，係包括：板體，係具有複數電性接觸墊；第一鈍化層，係設於該板體上且覆蓋各該電性接觸墊之部分表面；第二鈍化層，係設於該第一鈍化層上且外露各該電性接觸墊；第一金屬層，係設於各該電性接觸墊與第一鈍化層上，並埋設於該第二鈍化層中，而未凸出該第二鈍化層；以及第二金屬層，係設於該第一金屬層上，並凸出該第二鈍化層。 A substrate having an electrical connection structure, comprising: a plate body having a plurality of electrical contact pads; a first passivation layer disposed on the plate body and covering a portion of the surface of each of the electrical contact pads; a layer is disposed on the first passivation layer and exposes each of the electrical contact pads; a first metal layer is disposed on each of the electrical contact pads and the first passivation layer, and is buried in the second passivation layer And not protruding the second passivation layer; and the second metal layer is disposed on the first metal layer and protrudes the second passivation layer. 如申請專利範圍第1項所述之基板，其中，該板體係為非導體之板材。 The substrate of claim 1, wherein the plate system is a non-conductor plate. 如申請專利範圍第1項所述之基板，其中，該板體中復具有複數導電穿孔，供該電性接觸墊形成於該導電穿孔之孔端上。 The substrate of claim 1, wherein the plate body has a plurality of conductive perforations, and the electrical contact pads are formed on the hole ends of the conductive perforations. 如申請專利範圍第1項所述之基板，其中，該板體復具有線路部，供各該電性接觸墊形成於該線路部上、及該第一鈍化層形成於該線路部上。 The substrate of claim 1, wherein the plate body has a line portion, wherein each of the electrical contact pads is formed on the line portion, and the first passivation layer is formed on the line portion. 如申請專利範圍第1項所述之基板，其中，該第二鈍化層之厚度係大於該第一鈍化層之厚度。 The substrate of claim 1, wherein the second passivation layer has a thickness greater than a thickness of the first passivation layer. 如申請專利範圍第1項所述之基板，其中，該第一金屬層與第二金屬層係構成凸塊底下金屬層。 The substrate of claim 1, wherein the first metal layer and the second metal layer constitute a under bump metal layer. 如申請專利範圍第1項所述之基板，其中，該第一金屬層具有一延伸墊與一外接部，該延伸墊係設於各該電性接觸墊上，且該外接部係設於該延伸墊上。 The substrate of claim 1, wherein the first metal layer has an extension pad and an external portion, the extension pad is disposed on each of the electrical contact pads, and the external portion is disposed on the extension On the mat. 如申請專利範圍第1項所述之基板，其中，該第一金屬層之材質不同於該第二金屬層之材質。 The substrate of claim 1, wherein the material of the first metal layer is different from the material of the second metal layer. 如申請專利範圍第1項所述之基板，其中，該第一金屬層係為銅層。 The substrate of claim 1, wherein the first metal layer is a copper layer. 如申請專利範圍第1項所述之基板，其中，該第二金屬層係為鎳層、金層或其二者之組合。 The substrate of claim 1, wherein the second metal layer is a nickel layer, a gold layer or a combination of the two. 如申請專利範圍第1項所述之基板，復包括設於該第一金屬層與各該電性接觸墊之間的晶種層。 The substrate of claim 1, further comprising a seed layer disposed between the first metal layer and each of the electrical contact pads. 如申請專利範圍第11項所述之基板，其中，該第二金屬層之材質不同於該晶種層之材質。 The substrate of claim 11, wherein the material of the second metal layer is different from the material of the seed layer. 如申請專利範圍第11項所述之基板，其中，該晶種層之材質係為鈦、銅或其二者之組合。 The substrate of claim 11, wherein the material of the seed layer is titanium, copper or a combination of the two. 如申請專利範圍第1項所述之基板，復包括設於該第二金屬層上之導電凸塊。 The substrate of claim 1, further comprising a conductive bump disposed on the second metal layer. 如申請專利範圍第14項所述之基板，其中，該導電凸塊係具有銲錫材料。 The substrate of claim 14, wherein the conductive bump has a solder material. 如申請專利範圍第1項所述之基板，其中，該第二鈍化層係對應位於各該電性接觸墊之部分表面之上方。 The substrate of claim 1, wherein the second passivation layer is located above a portion of the surface of each of the electrical contact pads. 如申請專利範圍第1項所述之基板，其中，該第二鈍化層係未對應位於各該電性接觸墊之上方。 The substrate of claim 1, wherein the second passivation layer is not correspondingly located above each of the electrical contact pads. 一種具電性連接結構之基板之製法，係包括： 提供一板體，該板體具有複數電性接觸墊、及設於該板體上且外露各該電性接觸墊之第一鈍化層；形成第二鈍化層於該第一鈍化層上，該第二鈍化層並形成有對應外露各該電性接觸墊之複數開口；形成第一金屬層於各該開口中之電性接觸墊上，以使該第一金屬層埋設於該第一與第二鈍化層中，且該第一金屬層未凸出該第二鈍化層；以及形成第二金屬層於該第一金屬層上，且使該第二金屬層凸出該第二鈍化層。 A method for manufacturing a substrate having an electrical connection structure includes: Providing a plate body having a plurality of electrical contact pads, and a first passivation layer disposed on the plate body and exposing each of the electrical contact pads; forming a second passivation layer on the first passivation layer, a second passivation layer is formed with a plurality of openings corresponding to the exposed respective electrical contact pads; forming a first metal layer on the electrical contact pads in each of the openings to embed the first metal layer in the first and second In the passivation layer, the first metal layer does not protrude the second passivation layer; and the second metal layer is formed on the first metal layer, and the second metal layer is protruded from the second passivation layer. 如申請專利範圍第18項所述之基板之製法，其中，該第二鈍化層之厚度係大於該第一鈍化層之厚度。 The method of fabricating a substrate according to claim 18, wherein the thickness of the second passivation layer is greater than the thickness of the first passivation layer. 如申請專利範圍第18項所述之基板之製法，復包括於形成該第一金屬層之前，形成晶種層於該第二鈍化層、開口之孔壁與各該電性接觸墊上，以於形成該第一金屬層後，令部分該晶種層設於該第一金屬層與各該電性接觸墊之間，且於形成該第二金屬層之後，移除該第二鈍化層上之晶種層。 The method for manufacturing a substrate according to claim 18, further comprising forming a seed layer on the second passivation layer, the opening hole wall and each of the electrical contact pads before forming the first metal layer, so as to After the first metal layer is formed, a portion of the seed layer is disposed between the first metal layer and each of the electrical contact pads, and after the second metal layer is formed, the second passivation layer is removed Seed layer. 如申請專利範圍第20項所述之基板之製法，其中，移除該晶種層之方式係為蝕刻方式。 The method of fabricating a substrate according to claim 20, wherein the method of removing the seed layer is an etching method. 如申請專利範圍第20項所述之基板之製法，復包括於移除該晶種層後，形成導電凸塊於該第二金屬層上。 The method for manufacturing a substrate according to claim 20, further comprising, after removing the seed layer, forming a conductive bump on the second metal layer. 如申請專利範圍第18項所述之基板之製法，其中，該開口之徑寬大於、等於或小於該電性接觸墊之寬度。 The method of fabricating a substrate according to claim 18, wherein the opening has a diameter greater than, equal to, or less than a width of the electrical contact pad. 一種具電性連接結構之基板之製法，係包括： 提供一板體，該板體具有複數電性接觸墊、及設於該板體上且外露各該電性接觸墊之鈍化層；形成第一金屬層於各該電性接觸墊與部分該鈍化層上，且該第一金屬層具有無效部；形成第二金屬層於該第一金屬層上，且該第二金屬層未覆蓋於該無效部上方；以及移除該無效部。 A method for manufacturing a substrate having an electrical connection structure includes: Providing a plate body having a plurality of electrical contact pads, and a passivation layer disposed on the plate body and exposing each of the electrical contact pads; forming a first metal layer on each of the electrical contact pads and partially encapsulating And the first metal layer has an ineffective portion; the second metal layer is formed on the first metal layer, and the second metal layer is not over the ineffective portion; and the ineffective portion is removed. 如申請專利範圍第24項所述之基板之製法，復包括於形成該第一金屬層之前，形成晶種層於該鈍化層與各該電性接觸墊上，以於形成該第一金屬層時，令該部分晶種層位於該第一金屬層與各該電性接觸墊之間、及位於該第一金屬層與該鈍化層之間，且於移除該無效部時，一併移除該無效部下之晶種層。 The method for manufacturing a substrate according to claim 24, further comprising forming a seed layer on the passivation layer and each of the electrical contact pads before forming the first metal layer, so as to form the first metal layer. Having the portion of the seed layer between the first metal layer and each of the electrical contact pads, and between the first metal layer and the passivation layer, and removing the ineffective portion The seed layer under the ineffective portion. 如申請專利範圍第25項所述之基板之製法，其中，移除該晶種層之方式係為蝕刻方式。 The method of fabricating a substrate according to claim 25, wherein the method of removing the seed layer is an etching method. 如申請專利範圍第25項所述之基板之製法，復包括於移除該晶種層後，形成導電凸塊於該第二金屬層上。 The method for manufacturing a substrate according to claim 25, further comprising: after removing the seed layer, forming a conductive bump on the second metal layer. 一種具電性連接結構之基板之製法，係包括：形成一第一阻層於一具有複數電性接觸墊之板體上，再形成一第二阻層於該第一阻層上，其中，該第一阻層形成有複數第一開口區，而該第二阻層上形成有複數連通該第一開口區之第二開口區，且該第一開口區之開口大於該第二開口區之開口，並使該些電性接觸墊外露於該些第一與第二開口區； 形成第一金屬層於該第一開口區中，且該第一金屬層具有無效部；形成第二金屬層於該第一金屬層上，且該第二金屬層位於該第二開口中而未覆蓋該無效部上方；移除該第一與第二阻層；以及移除該無效部。 A method for fabricating a substrate having an electrical connection structure includes: forming a first resist layer on a board having a plurality of electrical contact pads, and forming a second resist layer on the first resist layer, wherein The first resistive layer is formed with a plurality of first open areas, and the second resistive layer is formed with a plurality of second open areas communicating with the first open area, and the opening of the first open area is larger than the second open area Opening, and exposing the electrical contact pads to the first and second open areas; Forming a first metal layer in the first opening region, and the first metal layer has an ineffective portion; forming a second metal layer on the first metal layer, and the second metal layer is located in the second opening Covering the inactive portion; removing the first and second resist layers; and removing the invalid portion. 如申請專利範圍第28項所述之基板之製法，其中，形成該第一與第二開口區之製程係包括：於形成該第二阻層前，對該第一阻層進行第一次曝光作業，使部分該第一阻層形成為第一曝光區；於形成該第二阻層之後，對該第二阻層進行第二次曝光作業，使部分該第二阻層形成為第二曝光區；以及進行至少一次顯影作業，使該第一曝光區形成為該第一開口區，且該第二曝光區形成為該第二開口區。 The method of manufacturing the substrate of claim 28, wherein the forming the first and second open regions comprises: first exposing the first resist layer before forming the second resist layer Working to form a portion of the first resistive layer as a first exposed region; after forming the second resistive layer, performing a second exposure operation on the second resistive layer to form a portion of the second resistive layer to form a second exposure And performing at least one development operation such that the first exposure region is formed as the first opening region, and the second exposure region is formed as the second opening region. 如申請專利範圍第28項所述之基板之製法，其中，形成該第一與第二開口區之製程係包括：於形成該第二阻層之後，對該第一與第二阻層進行至少一次曝光作業，使部分該第一阻層形成為第一曝光區，且部分該第二阻層形成為第二曝光區；以及進行至少一次顯影作業，使該第一曝光區形成為該第一開口區，且該第二曝光區形成為該第二開口區。 The method of fabricating the substrate of claim 28, wherein the forming the first and second open regions comprises: after forming the second resist layer, performing at least the first and second resist layers a first exposure operation, wherein a portion of the first resistive layer is formed as a first exposed region, and a portion of the second resistive layer is formed as a second exposed region; and performing at least one development operation to form the first exposed region as the first An open area, and the second exposed area is formed as the second open area. 如申請專利範圍第28項所述之基板之製法，其中，形成該第一與第二開口區之製程係包括： 於形成該第二阻層之前，對該第一阻層進行曝光作業，使部分該第一阻層形成為第一曝光區；進行第一次顯影作業，使該第一曝光區形成為該第一開口區；於形成該第二阻層之後，對該第二阻層進行曝光作業，使部分該第二阻層形成為第二曝光區；以及進行第二次顯影作業，使該第二曝光區形成為該第二開口區。 The method for manufacturing a substrate according to claim 28, wherein the process system for forming the first and second open regions comprises: Before forming the second resist layer, performing an exposure operation on the first resist layer to form a portion of the first resist layer as a first exposure region; performing a first development operation to form the first exposure region as the first An opening region; after forming the second resist layer, performing an exposure operation on the second resist layer to form a portion of the second resist layer as a second exposure region; and performing a second development operation to make the second exposure A zone is formed as the second open zone. 如申請專利範圍第28項所述之基板之製法，復包括於形成該第一阻層之前，形成晶種層於各該電性接觸墊上，以於形成該第一金屬層時，令該部分晶種層位於該第一金屬層與各該電性接觸墊之間，且於移除該無效部時，一併移除該無效部下之晶種層。 The method for manufacturing a substrate according to claim 28, further comprising forming a seed layer on each of the electrical contact pads before forming the first resist layer, so as to form the first metal layer The seed layer is located between the first metal layer and each of the electrical contact pads, and when the ineffective portion is removed, the seed layer under the ineffective portion is removed. 如申請專利範圍第32項所述之基板之製法，其中，移除該晶種層之方式係為蝕刻方式。 The method of fabricating a substrate according to claim 32, wherein the method of removing the seed layer is an etching method. 如申請專利範圍第32項所述之基板之製法，復包括於移除該晶種層後，形成導電凸塊於該第二金屬層上。 The method for manufacturing a substrate according to claim 32, further comprising: after removing the seed layer, forming a conductive bump on the second metal layer.
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