TWI548090B - Semiconductor device and method of fabricating the same - Google Patents

Description

Semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a trench structure and a method of fabricating the same.

Lateral double-diffused MOS (LDMOS) is widely used in high-voltage operating environments due to its high operating bandwidth and operating efficiency, as well as a planar structure that is easily integrated with other integrated circuits. Such as CPU power supply, power management system, AC/DC converter, and high-power or high-band power amplifiers.

Please refer to FIG. 1 , which illustrates a cross-sectional view of a conventional laterally diffused MOS device. As shown in FIG. 1, the laterally diffused metal oxide semiconductor device (LDMOS) 10 includes a P-type substrate 11, an N-type well 12 disposed in the substrate 11, and a field oxide layer 13 disposed on the substrate 11 and a gate 14 A portion of the field oxide layer 13 is disposed on the side of the gate electrode 14. A P-type doping region 16 is located in the N-type well 12, and a source 17 is located in the P-type doping region 16 on one side of the sidewall sub-flange 15, and a drain electrode 18 is disposed on the other side of the sidewall sub-section N. Well 12 in. The main feature of LDMOS is the low doping concentration and large-area lateral diffusion drift region set by the 汲 terminal. The purpose is to alleviate the high voltage between the source terminal and the 汲 terminal, which can make the LDMOS obtain a higher breakdown voltage. , V _bd ).

Since electronic products and their peripheral products are developing in a light, thin and short direction, how to effectively reduce the area occupied by LDMOS transistor components and maintain the same electrical performance is a problem that the relevant technical experts desire to improve.

It is an object of the present invention to provide a semiconductor device having a trench structure and a method of fabricating the same to save a horizontal area occupied by the semiconductor device.

A preferred embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a buried layer, a deep well region, a first doped region, a well region, a first heavily doped region, and a second A heavily doped region, a gate, a first trench structure, and a second trench structure. The buried layer and the deep well region having the first conductivity type are disposed in the semiconductor substrate, wherein the deep well region is located on the buried layer. A first doped region having a first conductivity type is disposed in the deep well region and contacts the buried layer. A well region having a second conductivity type is disposed in the deep well region. a first heavily doped region having a first conductivity type is disposed in the first doped region, a second heavily doped region having a first conductivity type is disposed in the well region, and the gate is disposed in the first heavily doped region The semiconductor base soil between the second heavily doped region. The first trench structure is disposed in the semiconductor substrate on one side of the gate, and the first trench structure contacts the buried layer. The second trench structure is disposed in the semiconductor substrate opposite to the gate of the first trench structure, wherein one of the depths of the second trench structure is substantially greater than a depth of the buried layer.

Another preferred embodiment of the present invention provides a method of fabricating a semiconductor device comprising the following steps. A semiconductor substrate is provided and a buried layer is formed in the semiconductor substrate. Next, a deep well region having a first conductivity type is formed in the semiconductor substrate, and the deep well region is located on the buried layer. And forming at least one first trench structure in the deep well region, and the first trench structure extends into the buried layer, and at least one second trench structure is formed in the semiconductor substrate, wherein the depth of one of the second trench structures is substantially Greater than one depth of the buried layer.

The present invention replaces the horizontal oxide space by the vertical space by the first trench structure, so that the first trench structure has sufficient insulation effect in addition to the gate of the semiconductor device and the first heavily doped region. The vertical space relaxes the high voltage current introduced by the first heavily doped region to avoid failure of the semiconductor device. Therefore, in the arrangement in which the first trench structure extends vertically to the contact buried layer, the present invention can effectively reduce the horizontal area occupied by the semiconductor device to improve the utilization ratio of the semiconductor substrate.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

The present invention first provides a semiconductor device, please refer to FIG. 2 is a schematic view of a semiconductor device according to a preferred embodiment of the present invention. As shown in FIG. 2, the semiconductor device 20 of the present invention includes a semiconductor substrate 22, a buried layer 24, a deep well region 26, a first doped region 28, a well region 30, and a first heavily doped layer. A region 32, a second heavily doped region 34, a third heavily doped region 36, a gate 38, a first trench structure 40, and a second trench structure 42. The semiconductor substrate 22 can comprise, for example, a substrate comprised of gallium arsenide, a blanket overlying (SOI) layer, an epitaxial layer, a germanium layer, or other semiconductor substrate material. The buried layer 24 is disposed in the semiconductor substrate 22. In this embodiment, the buried layer 24 can be an N-type buried layer, but not limited thereto, and is used for isolation to prevent current signals from being transmitted downward. Leakage is caused to the semiconductor substrate 22. The deep well region 26 having the first conductivity type is disposed in the semiconductor substrate 22, and the deep well region 26 is disposed on the buried layer 24, wherein the semiconductor substrate 22 may further include an epitaxial layer (not shown), and the deep well region 26 is disposed on In the epitaxial layer, for example, the deep well region 26 can be disposed in an epitaxial layer having a thickness of substantially 5 micrometers (um).

The first doped region 28 having the first conductivity type and the well region 30 having the second conductivity type are both disposed in the deep well region 26, the first doped region 28 is in contact with the buried layer 24, and the well region 30 is preferably not The buried layer 24 is contacted, but not limited thereto, wherein the first conductivity type is one of the N type or the P type, and the second conductivity type is the other of the P type or the N type. In addition, the first doping region 28 preferably has a doping concentration increasing in the direction of the interface between the first doping region and the buried layer to the interface between the first doping region and the semiconductor substrate. The first heavily doped region 32 and the second heavily doped region 34 each have a first conductivity type, the first heavily doped region 32 is disposed in the first doped region 28, and the second heavily doped region 34 is disposed in the well In area 30. In the present embodiment, the first heavily doped region 32 includes a drain and the second heavily doped region 34 includes a source. The third heavily doped region 36 is disposed in the well region 30 having the same second conductivity type as the well region 30, and the third heavily doped region 36 can be used to regulate the potential of the well region 30. brake The gate 38 is disposed on the semiconductor substrate 22 between the first heavily doped region 32 and the second heavily doped region 34. The gate 38 may include a gate dielectric layer 44, a gate electrode 46, and a cap layer 48. And a side wall 50, and the material of the gate 38 is well known to those skilled in the art, so it will not be described here. Among them, part of the well area 30 is located below the gate 38.

In addition, the first trench structure 40 is disposed in the semiconductor substrate 22 on one side of the gate 38, between the first heavily doped region 32 and the second heavily doped region 34, and the first trench structure 40 is located in a portion of the gate Below the pole 38, in more detail, the first trench structure 40 is disposed between the first doped region 28 and the well region 30. The first trench structure 40 contacts the buried layer 24 and preferably extends into the buried layer 24 but does not penetrate the buried layer 24. The second trench structure 42 is disposed in the semiconductor substrate 22 on the other side of the gate 38 of the first trench structure 40. The first trench structure 40 and the second trench structure 42 may each comprise an insulating material, and the second trench structure 42 is used to provide a semiconductor device 20 and other semiconductor devices (not shown) disposed in the semiconductor substrate 22. Isolated effect. The width of one of the first trench structures 40 is substantially smaller than the width of one of the second trench structures 42 . The first trench structure 40 only contacts the buried layer 24 but does not pass through the buried layer 24 , and the second trench structure 42 A depth system is substantially greater than a depth of the buried layer 24, that is, a bottom surface of the second trench 42 structure will be located below a bottom surface of the buried layer 24, that is, the depth of the second trench structure 42 is substantially Greater than one of the depths of the first trench structure 40.

The semiconductor device 20 can include a lateral double-diffused MOS (LDMOS). When the semiconductor device 20 is turned on and a high voltage current flows from the first heavily doped region 32, the first trench structure 40 can prevent high The voltage current flows directly through the gate dielectric layer 44 to the gate electrode 46 causing the semiconductor device 20 to fail. It should be noted that the first trench structure 40 of the present invention extends vertically to the contact buried layer 24 such that the high voltage current flows along one of the sidewalls of the first trench structure 40, R1, one of the buried layers 24, and A path R3 along one of the other sidewalls of the first trench structure 40 flows to the gate 38 to mitigate this high voltage current. In contrast to the laterally extending field oxide layer of the prior art, the first trench structure 40 of the present invention replaces a portion of the horizontal space occupied by the field oxide layer with a vertical space, which will increase the available ratio of the semiconductor substrate 20.

The present invention also provides a method of fabricating a semiconductor device, please refer to Figures 3 through 10. 3 to 10 are schematic views showing a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention. As shown in FIG. 3, a semiconductor substrate 22 is provided and an ion implantation process P1 is performed to form a buried layer 24 in the semiconductor substrate 22. The semiconductor substrate 22 can comprise, for example, a substrate of gallium arsenide, a germanium-clad insulating layer, an epitaxial layer, a germanium layer, or other semiconductor substrate material, and the buried layer 24 can include an N-type buried layer. Next, as shown in FIG. 4, after the buried layer 24 is formed, an epitaxial layer 52 may be further formed to thicken the semiconductor substrate 22, for example, by a selective epitaxial growth (SEG) process. An epitaxial layer 52 having a thickness of substantially 5 microns is above the buried layer 24. Accordingly, an ion implantation process P2 is performed to form a deep well region 26 having a first conductivity type in the epitaxial layer 52, that is, the deep well region 26 is located in the semiconductor substrate 22 on the buried layer 24.

Thereafter, as shown in FIG. 5, a patterned mask layer 54 is formed on the semiconductor substrate for defining an area defining a first trench structure (not shown) and a second trench structure (not shown). That is, the first trench structure predetermined region 40A and the second trench structure predetermined region 42A. At this time, the width w1 of one of the first trench structure predetermined regions 40A is substantially smaller than the width w2 of the second trench structure predetermined region 42A, wherein the patterning The material of the mask layer 54 may include a single film layer or a composite film layer such as tantalum oxide or tantalum nitride. Next, as shown in FIG. 6, an etching process is performed to transfer the pattern of the patterned mask layer 54 to the semiconductor substrate 22, and a portion of the semiconductor substrate 22 is removed to simultaneously form at least a first trench 40' and at least a second. The trench 42' is in the semiconductor substrate 22.

It is noted that, since the width w1 of the predetermined region 40A of the first trench structure is substantially smaller than the width w2 of the predetermined region 42A of the second trench structure, the semiconductor substrate 22 exposed in the predetermined region 40A of the first trench structure is in progress during the etching process. The range will be substantially smaller than the extent of the semiconductor substrate 22 exposed by the predetermined region 42A of the second trench structure, and thus, the first trench formed under the same process conditions, for example, the same etchant selection ratio and the same etching time, etc. The depth d1 of 40' will be substantially less than the depth d2 of the second trench 42'. In the present embodiment, one of the depths d3 of the buried layer 24 is substantially between the depth d1 of the first trench 40' and the depth d2 of the second trench structure 42'. In short, the present invention can simultaneously form trenches having different corresponding depths by adjusting the width of the predetermined area of the trench structure, and the width of the formed trenches is proportional to the depth of the formed trenches.

The first trench 40' and the second trench 42' are then filled with an insulating material to form a first trench structure 40 and a second trench structure 42. The method of filling the first trench 40' and the second trench 42' may include the following steps. First, a thermal oxidation process is selectively performed to oxidize the semiconductor substrate 22 exposed by the first trench 40' and the second trench 42' to form an oxide layer (not shown) covering the first trench 40' and the second The bottom and inner sides of the trench 42' are not filled with the first trench 40' and the second trench 42'. Then, a chemical deposition process such as High Density Plasma CVD (HDPCVD), sub-atmospheric CVD (SACVD) or spin-on dielectric (Spin on dielectric) is utilized. , SOD) and the like, and an oxide dielectric layer (not shown) is formed to fill the first trench 40' and the second trench 42'. Next, a chemical mechanical polishing process is performed to remove the excess oxide layer, the excess oxide dielectric layer, and the remaining patterned mask layer to complete the first trench structure 40 and the second trench structure as shown in FIG. 42. At this time, the first trench structure 40 contacts the buried layer 24 but does not pass through the buried layer 24, and one of the bottom surfaces of the second trench structure 42 is located below one of the bottom surfaces of the buried layer 24. In the present embodiment, the first trench structure 40 surrounds a portion of the deep well region 26, and the second trench structure 42 surrounds the deep well region 26 and the first trench structure 40, but is not limited thereto.

The width of the first trench structure predetermined region 40A, the width of the first trench 40', and the width of the first trench structure 40 are substantially equal, and may be represented by w1. The width of the second trench structure predetermined region 42A, the width of the second trench 42', and the width of the second trench structure 42 are substantially equal, both of which may be represented by w2.

An ion implantation process P3 is then performed to form a first doped region 28 in the deep well region 26 on the side of the first trench structure 40, and the first doped region 28 has a first conductivity type. The embodiment may be as shown in FIG. 7 , first forming a patterned mask (not shown), and then performing an ion implantation process P3 to form a first doping in the deep well region 26 surrounded by the first trench structure 40 . Miscellaneous area 28. The first doped region 28 contacts the buried layer, and the first doped region 28 may have a doping concentration along the interface s3 of the first doped region 28 and the buried layer 24 to the first doped region 28 and the semiconductor. The direction of the interface s4 of one of the substrates 22 is increased. The step of ion implantation process P3 includes first implanting a dopant having a first conductivity type into a portion of the deep well region 26, and then further utilizing a heat treatment process to drive-in the dopant. In addition, the ion implantation process P3 can also be a segmented ion implantation process, for example, performing an ion implantation process multiple times to form a plurality of first doped regions having different doping concentrations and different depths respectively (not shown) And the first doped regions may together form a first doped region 28 having a ladder doping concentration profile. In addition, the order of formation of the first trench structure 40 and the second trench structure 42 and the formation of the first doping region 28 is not limited thereto.

As shown in FIG. 8, an ion implantation process P4 is performed to form at least one well region 30 in the deep well region 26 on the other side of the first trench structure 40, wherein the well region 30 has a second conductivity type, and Preferably, the buried layer 24 is not in contact. The first conductivity type is one of N type or P type, and the second conductivity type is the other of P type or N type. In the present embodiment, the first trench structure 40 is located between the well region 30 and the first doped region 28, the first trench structure 40 surrounds the first doped region 28, and the second trench structure 42 surrounds the deep well region 26, A trench structure 40 and a first doped region 28 are not limited thereto. The step of ion implantation process P4 includes first implanting a dopant having a second conductivity type into a portion of the deep well region 26, and further driving the dopant by a heat treatment process. The doping concentration of the well region 30 is substantially equal to the doping concentration of the deep well region 26 and less than the doping concentration of the buried layer 24, but is not limited thereto.

Next, as shown in FIG. 9, at least one gate 38 is formed on the semiconductor substrate 22. The gate 38 may include a gate dielectric layer 44, a gate electrode 46, a cap layer 48, and a sidewall spacer 50. The gate process is well known to those skilled in the art and will not be described here. The gate 38 overlaps a portion of the deep well region 26 between the first trench structure 40 and the second trench structure 42 and partially overlaps the first trench structure 40. Thereafter, at least one first heavily doped region 32 is formed in the first doped region 28, and at least a second heavily doped region 34 is formed in the well region 30, the first heavily doped region 32 and the second heavily doped region. The doped region 34 has a first conductivity type, and the method of forming the first heavily doped region 32 and the second heavily doped region 34 includes using the gate 38 and a patterned mask (not shown) as a mask. An ion implantation process P5 is formed to form the first heavily doped region 32 and the second heavily doped region 34 in the semiconductor substrate 22 on both sides of the gate 38, respectively. The doping concentration of the first heavily doped region 32 and the doping concentration of the second heavily doped region 34 are both substantially greater than the doping concentration of the deep well region 26 and the doping concentration of the well region 30. At this time, the first trench structure 40 is located between the first heavily doped region 32 and the second heavily doped region 34, and the second trench structure 42 is located at the semiconductor substrate opposite to the other side of the gate 38 of the first trench structure 40. 22 in. Additionally, an ion implantation process P6 can be further performed to form at least one third heavily doped region 36 in the well region 30, the third heavily doped region 36 having the same second conductivity type as the well region 30. In the present embodiment, the first heavily doped region 32 includes a common drain, the second heavily doped region 34 includes a source, and the third heavily doped region 36 can be used to regulate the potential of the well region 30. Thus, the structure of the semiconductor device 56 such as LDMOS is completed.

As shown in FIG. 10, in another preferred embodiment, the semiconductor device 56 of the present invention may further include a shallow trench isolation 58 surrounding the periphery to provide an insulating effect of the semiconductor device 56 to prevent the semiconductor device 56 from being on the semiconductor substrate. Other components (not shown) interfere with each other. The formation of the shallow trench isolation 58 can be integrated into the processes of the first trench structure 40 and the second trench structure 42, that is, the shallow trench isolation 58, the first trench structure 40, and the second trench structure 42 can be simultaneously completed, Save production costs, but not limited to this. One of the depth d4 of the shallow trench isolation 58 is substantially smaller than the depth d1 of the first trench structure 40 and the depth d2 of the second trench structure 42.

The present invention replaces the horizontal oxide space by the vertical space by the first trench structure, so that the first trench structure has sufficient insulation effect in addition to the gate of the semiconductor device and the first heavily doped region. The vertical space relaxes the high voltage current introduced by the first heavily doped region to avoid failure of the semiconductor device. Therefore, in the arrangement in which the first trench structure extends vertically to the contact buried layer, the present invention can effectively reduce the horizontal area occupied by the semiconductor device to improve the utilization ratio of the semiconductor substrate.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Laterally diffused MOS device

11. . . Base

12. . . N-type well

13. . . Field oxide layer

14. . . Gate

15. . . Side wall

16. . . P-doped region

17. . . Source

18. . . Bungee

20. . . Semiconductor device

twenty two. . . Semiconductor substrate

twenty four. . . Buried layer

26. . . Deep well area

28. . . First doped region

30. . . Well area

32. . . First heavily doped region

34. . . Second heavily doped region

36. . . Third heavily doped region

38. . . Gate

40. . . First ditch structure

40A. . . First ditch structure predetermined area

40’. . . First ditches

42. . . Second ditch structure

42A. . . Second ditch structure predetermined area

42’. . . Second ditches

44. . . Gate dielectric layer

46. . . Gate electrode

48. . . Cover

50. . . Side wall

52. . . Epitaxial layer

54. . . Patterned mask layer

56. . . Semiconductor device

58. . . Shallow trench isolation

D1, d2, d3, d4. . . depth

S3, s4. . . Interface

W1, w2. . . width

P1, P2, P3, P4, P5, P6. . . Ion implantation process

R1, R2, R3. . . path

FIG. 1 is a schematic cross-sectional view showing a conventional laterally diffused MOS device.

2 is a schematic view of a semiconductor device according to a preferred embodiment of the present invention.

3 to 10 are schematic views showing a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.

20. . . Semiconductor device

twenty two. . . Semiconductor substrate

twenty four. . . Buried layer

26. . . Deep well area

28. . . First doped region

30. . . Well area

32. . . First heavily doped region

34. . . Second heavily doped region

36. . . Third heavily doped region

38. . . Gate

40. . . First ditch structure

42. . . Second ditch structure

44. . . Gate dielectric layer

46. . . Gate electrode

48. . . Cover

50. . . Side wall

R1, R2, R3. . . path

Claims (20)

A semiconductor device comprising: a semiconductor substrate; a buried layer disposed in the semiconductor substrate; a deep well region having a first conductivity type disposed in the semiconductor substrate, wherein the deep well region is located on the buried layer a first doped region having the first conductivity type disposed in the deep well region and contacting the buried layer; a well region having a second conductivity type disposed in the deep well region; a heavily doped region having the first conductivity type disposed in the first doped region; a second heavily doped region having the first conductivity type disposed in the well region; and a gate disposed on the On the semiconductor substrate between the first heavily doped region and the second heavily doped region; a first trench structure disposed in the semiconductor substrate on the gate side, the first trench structure contacting the buried The bottom of the first trench structure does not exceed the bottom of the buried layer, and the first trench structure is disposed under a portion of the gate; and a second trench structure is disposed opposite to the first trench structure In the semiconductor substrate on the other side of the gate, wherein One of the second trench structure one depth is substantially greater than the depth of the buried layer. The semiconductor device of claim 1, wherein the first trench structure is disposed between the first heavily doped region and the second heavily doped region. The semiconductor device of claim 2, wherein the first trench structure is disposed between the first doped region and the well region. The semiconductor device of claim 1, wherein a portion of the well region is located below the gate and the well region does not contact the buried layer. The semiconductor device of claim 1, wherein the semiconductor substrate further comprises an epitaxial layer, and the deep well region is disposed in the epitaxial layer. The semiconductor device of claim 1, wherein one of the first trench structures has a width substantially smaller than a width of the second trench structure. The semiconductor device of claim 1, wherein the first doped region has a doping concentration along the interface between the first doped region and the buried layer to the first doped region and the semiconductor substrate The direction of an interface increases. The semiconductor device according to claim 1, wherein the first conductivity type is one of an N type or a P type, and the second conductivity type is the other one of a P type or an N type. A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a buried layer in the semiconductor substrate; Forming a deep well region having a first conductivity type in the semiconductor substrate, and the deep well region is located on the buried layer; forming at least one first trench structure in the deep well region, wherein the first trench structure extends into the Buried in the layer and the bottom of the first trench structure does not exceed the bottom of the buried layer; forming at least one second trench structure in the semiconductor substrate, wherein one of the second trench structures has a depth greater than the buried layer a depth; and forming at least one gate on the semiconductor substrate, and the gate overlaps a portion of the deep well region between the first trench structure and the second trench structure, the first trench structure being located at a portion Below the gate. The method of fabricating a semiconductor device according to claim 9, wherein the method of forming the deep well region having the first conductivity type comprises: forming an epitaxial layer on the buried layer; and performing an ion implantation process to The deep well region is formed in the epitaxial layer. The method of fabricating a semiconductor device according to claim 9, wherein one of the first trench structures has a width substantially smaller than a width of the second trench structure. The method of fabricating a semiconductor device according to claim 9, wherein the method of forming the first trench structure and the second trench structure comprises: forming a patterned mask layer on the semiconductor substrate for defining a first a predetermined area of the trench structure and a predetermined area of the second trench structure, wherein the first trench structure One of the predetermined regions has a width substantially smaller than a width of the predetermined region of the second trench structure; and an etching process is performed to form at least one first trench and at least one second trench, wherein one of the first trenches is substantially deep Less than one depth of the second trench. The method of fabricating a semiconductor device according to claim 12, wherein the method of forming the first trench structure and the second trench structure further comprises: performing a thermal oxidation process to form an oxide layer over the first trench and the first a bottom and an inner side of the second trench; an oxide dielectric layer is formed to fill the first trench and the second trench; and a chemical mechanical polishing process is performed. The method of fabricating a semiconductor device according to claim 9, further comprising performing an ion implantation process to form a first doping region in the deep well region on a side of the first trench structure, wherein the first doping region The first conductivity type is provided and contacts the buried layer. The semiconductor device of claim 14, wherein the first doped region has a doping concentration along the interface between the first doped region and the buried layer to the first doped region and the semiconductor substrate The direction of an interface increases. The method of fabricating a semiconductor device according to claim 14, further comprising performing an ion implantation process to form a well region in the deep well region on the other side of the first trench structure, wherein the well region has a second conductivity Type and not in contact with the buried layer. The method of fabricating a semiconductor device according to claim 16, further comprising: forming at least one first heavily doped region in the first doped region, and the first heavily doped region has the first conductivity type; Forming at least one second heavily doped region in the well region, and the second heavily doped region has the first conductivity type. The method of fabricating a semiconductor device of claim 17, wherein the first trench structure is between the first heavily doped region and the second heavily doped region. A method of fabricating a semiconductor device according to claim 17, wherein the second trench structure is located in the semiconductor substrate on the other side of the gate of the first trench structure. The method of fabricating a semiconductor device according to claim 16, wherein the first conductivity type is one of an N type or a P type, and the second conductivity type is the other one of a P type or an N type.