TWI537731B - Systems and methods for supporting a plurality of load accesses of a cache in a single cycle - Google Patents

Description

System and method for supporting multiple load accesses of a cache memory in a single cycle

A system and method for supporting a plurality of load accesses of a cache memory in a single cycle.

A data storage structure used by the central processing unit of the cache memory computer in the central processing unit to reduce the average time required to access the memory. The data storage structure is a memory for storing a copy of the data, located at the most frequently used main memory location. Moreover, the cache memory system is smaller than the main memory and can be accessed more quickly. There are several different types of cache memory. These include physically indexed physical tagged (PIPT), virtual indexed virtually tagged (VIVT), and virtual indexed physical tagged (VIPT).

A cache memory that accommodates multiple accesses in a single cycle provides performance advantages. In particular, this cache memory is characterized by reduced access latency. Conventional methods of accommodating multiple accesses in a single cycle include the use of multi-stream caches and provisioning of cache memory including a plurality of tags and banks.

The multi-stream cache system can process more than one requested cache memory at a time. In accessing some conventional cache memory, only a single memory address is requested. However, in a multi-stream memory, N memory addresses can be requested at one time, where N is the multi-stream memory. The number of defects that are available. The advantage of multi-ported cache memory is that it can accommodate larger throughputs (such as larger numbers of load and store requests). However, the amount of cache memory that is required to accommodate increasing levels of throughput may be impractical.

When each tag and database can process at least one request, the cache containing multiple tags and libraries can process more than one request at a time. However, when more than one request attempts to access the same repository, it must be determined whether the request allows access to the library. In a conventional method, arbitration is used to determine which request will be allowed to access a given tag and database. In this conventional method, the time required to perform the arbitration delays access to the tag library and thus delays the triggering of critical loading typically in the processor's level 1 cache. Hit Hit signal.

Conventional methods of accommodating throughput involving multiple loads may result in undesirable delays in receiving the load pull signal. A method of resolving these shortcomings, such as a plurality of load accesses of a data cache from a static random access memory (SRAM) or other type of memory, is disclosed. However, the specific embodiments claimed are not limited to implementations that solve any or all of the aforementioned disadvantages. As part of the method, accessing a plurality of requests to access the data cache memory, and responding to a plurality of requests, accessing a tag memory for maintaining each entry in the data cache memory Multiple pairs of labels this. Identify tags that correspond to individual requests. Data cache memory (for example, formed from SRAM or other types of memory) is divided into a number of databases or "blocks". Accessing data cache memory based on the identified tags. A plurality of requests for accessing the same block of the plurality of blocks of the data cache memory result in access arbitration involving the block. The block access arbitration is performed in parallel with the access of the tags corresponding to the individual access requests. Thus, the penalty of loading the timing of the extracted signal is avoided, and the loss of timing of the load-extracted signal is necessary for arbitration of the access tag and the database in the conventional method.

100‧‧‧Executive computing environment

101‧‧‧ system

103‧‧‧1 (L1) cache memory; L1 cache memory

103a‧‧1st order (L1) data cache memory; L1 data cache memory; data cache memory

103b‧‧‧Data cache memory tag memory

103c‧‧‧L1 cache memory controller; cache memory controller

105‧‧‧Central Processing Unit

107‧‧‧2nd order (L2) cache memory; L2 cache memory

109‧‧‧ main memory

111‧‧‧System interface; main memory

201‧‧‧Load request accessor

203‧‧‧ tag memory accessor

205‧‧‧Cache Memory Accessor

300‧‧‧ Flowchart

301, 303, 305, 307 ‧ ‧ steps

1-N‧‧‧ access request

AR1‧‧‧ first access request; access request

AR2‧‧‧ second access request; access request

(AR1-ARN) ‧‧‧Request

The invention and its further advantages are further understood by the following description in conjunction with the accompanying drawings in which: FIG. 1A shows a plurality of load accesses supporting a data cache in a single cycle in accordance with an embodiment. An exemplary computing environment for the system.

FIG. 1B illustrates a manner in which a plurality of data blocks facilitate access of a data cache by a throughput of multiple load accesses in the same clock cycle, in accordance with an embodiment.

1C shows a data cache memory tag memory that maintains a plurality of copies of a tag corresponding to an entry of a level one data cache in accordance with an embodiment.

1D illustrates an arbitration operation for a first access request and a second access request for an access request 1-N performed in parallel with a search of a data cache memory tag, in accordance with an embodiment.

Figure 1E illustrates a support for a single cycle in accordance with an embodiment. The memory cache performs a number of operations performed by the system that loads the access.

2 shows components of a system that supports a plurality of load accesses of a data cache in a single cycle, in accordance with an embodiment.

3 shows a flow diagram of a method of supporting a plurality of load accesses of a data cache in a single cycle, in accordance with an embodiment.

It should be noted that the same reference numbers refer to the same elements in the drawings.

Although the present invention has been described in connection with a specific embodiment, the invention is not intended to be limited to the specific forms disclosed herein. On the contrary, the invention is intended to cover alternatives, modifications, and equivalents, which are included within the scope of the invention as defined by the appended claims.

In the following embodiments, numerous specific details are set forth, such as the specific method sequences, structures, elements, and connections. It should be understood, however, that the specific embodiments of the invention are not to be In other instances, well-known structures, components, or <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

References to "one embodiment" in this specification are intended to indicate that the particular features, structures, or characteristics described in connection with the specific embodiments are included in at least one embodiment of the invention. The phrase "in one embodiment" or "an" or "an" or "an" In addition, many of the features described may be presented in some specific embodiments and not in other specific embodiments. Similarly, many of the requirements described may be desirable for certain embodiments, but not for other specific embodiments. begging.

Portions of the following embodiments are described in terms of procedures, steps, logic blocks, processing, and other symbolic representations of data bit operations in a computer memory. These instructions and representations are the means used by those skilled in the art to best convey the substance of their work to others skilled in the art. Here, the program, the steps performed by the computer, the logical blocks, the processing, and the like are generally considered to be a consistent sequence of steps or instructions leading to the desired result. These steps require physical manipulation of physical quantities. Typically, but not necessarily, these physical quantities take the form of electrical or magnetic signals of a computer-readable storage medium and can be stored, transferred, combined, compared, or operated in a computer system. It has proven convenient at times (primarily for normal use) to refer to such signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

However, it should be remembered that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient terms for the application. Unless expressly stated otherwise from the following discussion, it should be appreciated that throughout the present invention such as "accessing" or "searching" or "identifying" or "providing" or this The terminology of a class refers to the action and processing of a computer system or similar electronic computing device that is represented and converted in physical (electronic) quantities of data in computer system registers and memory and other computer readable media. Other material similarly represented as physical quantities in a computer system memory or scratchpad or other such information storage, transmission or display device.

An exemplary computing environment for a system that supports multiple load accesses of a cache memory in a single cycle in accordance with one embodiment

1A shows support for multiples in a single clock cycle, in accordance with an embodiment. An exemplary computing environment 100 that accesses a data cache memory is loaded. The system 101 allows for a tag (having a plurality of data blocks containing a plurality of requests) corresponding to the data sought by the first order data cache by a plurality of load requests within a single clock cycle. Moreover, as part of the operation of system 101, block access arbitration involving the plurality of load requests for the first order data cache is performed in the same clock cycle. Therefore, the throughput of a plurality of load accesses is adapted and the loss of the timing of the load extraction signals necessary for arbitration in the conventional method is avoided. 1A shows a system 101, a 1st order (L1) cache memory 103, a 1st order (L1) data cache memory 103a, a data cache memory tag memory 103b, an L1 cache memory controller 103c, and a central processing. A central processing unit (CPU) 105, a level two (L2) cache memory 107, a main memory 109, and a system interface 111.

Referring to FIG. 1A, the L1 cache memory 103 is a 1st order or "primary" cache memory and the L2 cache memory 107 is a 2nd order "secondary" cache memory. In a specific embodiment, the L1 cache memory 103 can be formed as part of the CPU 105. In one embodiment, as shown in FIG. 1A, the L1 cache memory 103 can include an L1 data cache memory 103a, a data cache memory tag memory 103b, and an L1 cache memory controller 103c. In one embodiment, the L1 data cache memory 103a can be divided into a plurality of data blocks. In one embodiment, the L1 data cache memory 103a can be divided into four 8 kilobyte data blocks. In other embodiments, the L1 data cache memory 103a can be divided into other data blocks having a capacity to store other data volumes. In one embodiment, as shown in FIG. 1B, the plurality of data blocks facilitate access to the L1 data cache memory 103a by multiple access flows in the same clock cycle. In a specific embodiment, the use of arbitration can simultaneously resolve conflicting requests for searching for the same block accessing the L1 data cache memory 103a (ignoring it as discussed above) The impact of time). In a specific embodiment, the data blocks may include cache memory line entries accessed by the load.

The data cache memory tag memory 103b is configured to maintain a tag entry for each cache memory line entry stored in the L1 data cache memory 103a. Referring to FIG. 1C, in one embodiment, as part of the configuration, the data cache memory tag memory 103b maintains a plurality of copies of the tags corresponding to the entries of the L1 data cache memory 103a (eg, 1-N). In particular, each request to access the L1 data cache memory 103a conforms to a dedicated copy of the tag corresponding to the entry of the L1 data cache memory 103a. This manner of maintaining tag entries facilitates the identification of tags associated with such cache memory line entries within a single clock cycle. In a specific embodiment, the tag may be completed in the same clock cycle when arbitration involving an access request (e.g., load request) for data associated with the tag in the L1 data cache memory 103a is performed. Identification. In one embodiment, an access request (eg, a load request) to the L1 data cache memory 103a triggers a retrieval of the data cache memory tag 103b for the data corresponding to the load request. s Mark.

Referring to FIG. 1A, the system 101 responds to the L1 cache memory 103 receiving a plurality of requests for accessing the L1 data cache memory 103a of the L1 cache memory 103, and executing the data cache memory tag memory 103b. The search is such that the tags corresponding to the data sought by the plurality of requests are identified in parallel with the execution of any arbitration operations associated with the requests. This is illustrated in FIG. 1D, in which the arbitration operation of the first access request AR1 and the second access request AR2 regarding the access request 1-N is displayed in parallel with the search of the data cache memory tag 103b. carried out. In a specific embodiment, the aforementioned action of system 101 operates to avoid detrimental effects on the arbitration operation of loading the timing of the extracted signals. In particular, the copied data cache memory tag memory The body 101b and the system 101 supported by the L1 data cache memory 103a support a cache memory access by a number of load requests in a clock cycle without loss of cache memory hits. Waiting time and circulation. In a specific embodiment, system 101 can be located in cache memory controller 103c. In other embodiments, system 101 can be detached from cache memory controller 103c, but in conjunction with it.

Referring back to FIG. 1A again, the main memory 111 includes a physical address for storing information copied to the cache memory. In a specific embodiment, when the cached information contained in the physical addresses of the main memory changes, the corresponding cache information is updated to reflect changes in the main memory storage information. At the same time, system interface 111 is also shown in FIG. 1A.

Operation

FIG. 1E illustrates an operation performed by system 101 that supports a plurality of load accesses of a data cache in a single cycle in accordance with an embodiment. For the purposes of clarity of representation and simplification, these operations are described with respect to a plurality of load accesses that support a data cache. It should be appreciated that other operations not illustrated in FIG. 1E may be performed in accordance with a particular embodiment.

Referring to FIG. 1E, at A, a plurality of requests for accessing the data cache memory 103a are received. In the example of FIG. 1E, two of the plurality of requests are received, namely, an access request AR1 and an access request AR2, which attempt to access the same data block of the L1 data cache memory 103a (eg, virtual of AR1 and AR2) Block 0 identified by address bits 6 and 7, such as virtual address bits 7: 6) for the virtual addresses of AR1 and AR2.

At B, the search data cache memory tag memory 103b is identified and associated with the search for the plurality of requests (AR1-ARN) of the L1 data cache memory 103a. The label in which it is located.

At C, during the same clock cycle as the search data cache memory tag memory 103b executed by B, which of the two requests (access request AR1 and access request AR2) is allowed to be initiated and completed is determined. The user accesses the arbitration processing of the block 0 of the L1 data cache memory 103a. As part of this arbitration process, one of the two requests (access request AR1) is selected to continue accessing block 0.

At D, the plurality of access requests (except for the arbitration loser such as AR2 in the example of FIG. 1E) use the tags identified by B to access the data cache memory 103a.

At E, the data sought by the access requests (e.g., "X" corresponding to AR1) is identified and read (e.g., loaded) in the L1 data cache memory 103a.

In one embodiment, system 101 is designed to operate in an environment that provides several load and store instructions in a single cycle. In a specific embodiment, the methodology disclosed herein avoids relying on the use of an excessive number of cache memories that may be impractical. In an exemplary embodiment, throughput is enabled without negatively impacting the timing of the "Load Hit" signal.

In a specific embodiment, as discussed herein, the L1 data cache memory 103a can be organized into a plurality of blocks, and the tags corresponding to the data maintained in the L1 data cache memory 103a can be copied and Stored in the data cache memory tag memory 103b. Moreover, as discussed herein, organizing the data cache memory 103a into blocks allows for multiple loads to be supported in a single cycle, as long as the same data block is not accessed. However, in one embodiment, a single data block can accommodate a plurality of loads as long as the plurality of loads are at the same address. In an exemplary embodiment, the method discussed herein does not perform any arbitration on the tag, and thus avoids the timing associated with the "Load Hit" signal derived from the arbitration operation, etc. Loss of time (increasing waiting time).

A component supporting a system of multiple load accesses of a cache memory in a single cycle in accordance with an embodiment

2 shows components of a system 101 that supports a plurality of load accesses of a cache memory in a single cycle, in accordance with an embodiment. In one embodiment, the components of system 101 implement an algorithm that supports a plurality of load accesses. In the particular embodiment of FIG. 2, components of system 101 include load request accessor 201, tag memory accessor 203, and cache memory accessor 205.

The load request accessor 201 accesses a plurality of load requests to search for data stored in the L1 data cache (e.g., 103a in Fig. 1A). In one embodiment, in some cases, more than one load request of the plurality of load requests may search for the same data block in the L1 data cache. In this case, arbitration is performed to determine which load request will be allowed to access the block of the L1 data cache.

In response to receiving a plurality of load requests, the tag memory accessor 203 searches for an individual copy (eg, 1-N) of a tag of a data cache memory tag (eg, 103b in FIG. 1A) in parallel. The tag corresponds to an entry of an L1 data cache (e.g., 103a of Figure 1A). In a specific embodiment, each load request conforms to a dedicated copy of the tag corresponding to the entry of the L1 data cache. This way of maintaining tag entries helps identify tags associated with cache line entries in a single clock cycle. In one embodiment, the arbitration of an access request (e.g., a load request) for one of the blocks of the L1 data cache associated with the data for a tag is performed during the same clock cycle in which the tag identification is completed.

The cache memory accessor 205 uses the tags to access a plurality of data blocks of the L1 data cache memory, the tags being identifiable by the tag memory accessor 203. In one embodiment, the plurality of data blocks facilitate access by the L1 data cache (eg, 103a of FIG. 1A) by a plurality of accessors in the same clock cycle. . In a specific embodiment, arbitration can be used to resolve conflicting access requests for simultaneous access to the same block of L1 data cache memory (by operation of system 101, as discussed in the text for "Load Hits (Load) Hit)" The time effect of the signal). In a specific embodiment, accessing the data block involves loading of the data.

It should be understood that the foregoing components of system 101 can be implemented in hardware or software or a combination of both. In one embodiment, the components and operations of system 101 may be covered by components and operations of one or more computer components or programs (e.g., cache memory controller 103c in FIG. 1A). In another embodiment, the components and operations of system 101 may be separate from one or more of the aforementioned computer components or programs, but may operate in conjunction with its components and operations.

Method for supporting a plurality of load accesses of a cache memory in a single cycle according to a specific embodiment

3 shows a flowchart 300 of a method of supporting a plurality of load accesses of a data cache memory in a single cycle, in accordance with an embodiment. The flowchart includes processing that can be performed by a processor and electronic components under the control of computer readable and computer executable instructions in a particular embodiment. Although specific steps are disclosed in the flowcharts, this step is exemplary. That is, this particular embodiment is best suited to carry out variations of various other steps or steps recited in the flowchart.

Referring to FIG. 3, in step 301, a plurality of load requests are accessed to access a data cache. In a specific embodiment, the data cache memory can include a plurality of blocks, and the plurality of blocks can accommodate the plurality of load requests. In a specific embodiment, the plurality of load requests may include a plurality of requests to search for the same block of access to the data cache.

In step 303, a tag memory is accessed, the tag memory maintaining a plurality of copies of the tags, the tags being the entries of the corresponding data cache.

At step 305, the tags are identified, the tags corresponding to individual load requests for the plurality of load requests received by the L1 cache. In a specific embodiment, each load request conforms to a dedicated copy of a set of tags that correspond to the entries in the data cache.

At step 307, the blocks of the data cache memory are accessed based on the tags, the tags corresponding to the individual requests. In one embodiment, the access of the plurality of blocks allows for throughput of multiple load accesses in the same clock cycle.

With respect to its exemplary embodiments, systems and methods for accessing data cache memory are disclosed. Accessing a plurality of requests (which access data cache memory), and responding to a plurality of requests to access a tag memory that maintains tags for each entry in the cache memory Multiple copies of it. Tags are identifiable and correspond to individual requests. The data cache memory is accessed based on the tags corresponding to the individual requests. Accessing a plurality of requests for the same block of the plurality of blocks results in an access arbitration that can be performed in the same clock cycle as the tag memory accesses.

Although many of the above components and processes are described in the singular form for convenience, they are familiar with Those skilled in the art will recognize that multiple components and repeated processes can also be used to implement the techniques of the present invention. In addition, the present invention has been particularly shown and described with respect to the specific embodiments thereof, and those skilled in the art can understand the form and details of the disclosed embodiments without departing from the invention. The spirit or scope. For example, specific embodiments of the invention may be employed with a variety of components and should not be limited to the above. It is intended that the present invention cover the modifications and

100‧‧‧Executive computing environment

101‧‧‧ system

103‧‧‧1 (L1) cache memory; L1 cache memory

103a‧‧1st order (L1) data cache memory; L1 data cache memory; data cache memory

103b‧‧‧Data cache memory tag memory

103c‧‧‧L1 cache memory controller; cache memory controller

105‧‧‧Central Processing Unit

107‧‧‧2nd order (L2) cache memory; L2 cache memory

109‧‧‧ main memory

111‧‧‧System interface; main memory

Claims (20)

A method for supporting a plurality of accesses of a data cache memory, comprising: accessing a plurality of requests to access the data cache memory, wherein the data cache memory comprises a plurality of blocks; A plurality of requests accessing the data cache memory, accessing a tag memory to maintain a plurality of copies of the tags of each entry in the data cache, and identifying individual ones corresponding to the plurality of requests a tag of the request; and accessing the data cache based on the tags corresponding to the individual requests, wherein accessing a plurality of requests of an identical block of the plurality of blocks results in an access arbitration ( Arbitration), which is performed in the same clock cycle as the access to the tag memory. The method of claim 1, wherein the accessing the data cache based on the tag comprises a plurality of loads, the loading being performed in a single clock cycle. The method of claim 1, wherein each request for the plurality of requests to access the data cache has a dedicated copy of the tag corresponding to the entry in the load cache. The method of claim 1, wherein the plurality of requests for accessing the data cache access the search for access to the respective blocks. The method of claim 1, wherein the plurality of requests for accessing the data cache memory search for different bits in an identical block of the data cache memory in the same cycle site. The method of claim 1, wherein the plurality of blocks comprise portions of a level one data cache and a cache memory line entry. The method of claim 1, wherein the tag memory comprises a tag static random access memory (SRAM). A cache memory system comprising: a data cache memory divided into a plurality of data blocks; and a tag memory configured to maintain a plurality of copies of tags corresponding to the entries of the load cache memory Corresponding tag; and a cache memory subsystem configured to access the tag memory and the data cache memory, wherein the arbitration operation is performed in the same clock cycle as accessing the tag memory, The arbitration operations are associated with a plurality of requests for accessing the data cache. For example, in the cache memory system of claim 8, wherein the plurality of data blocks accommodate a plurality of loads, the plurality of loads can be executed in a single clock cycle. For example, in the cache memory system of claim 8, wherein the plurality of the plurality of requests for accessing the data cache memory are searched for access to the individual data blocks. A cache system as claimed in claim 8 wherein each request of the plurality of requests has a dedicated copy of the tag corresponding to a cache line entry located in the data cache. . For example, the cache memory system of claim 8 of the patent scope, wherein the data cache memory Into four 8,000 byte data blocks. For example, the cache memory system of claim 8 wherein a plurality of load requests access the same block at different addresses in the same period. The cache memory system of claim 8, wherein the tag memory comprises a tag SRAM. A computer system comprising: a memory; a processor; and a cache memory system comprising: a data cache memory configured to store data; a tag memory configured to store tags, The tags correspond to the units of the data; and a cache memory controller includes a system for supporting a plurality of accesses to the data cache, including: a request access component, for Accessing a plurality of requests to access the data cache memory, wherein the data cache memory comprises a plurality of blocks; and a tag memory access component for accessing a tag memory, the tag memory Maintaining a plurality of copies of the tags of each entry in the data cache and identifying tags corresponding to individual requests for the plurality of requests; and a data cache memory access component for accessing the data cache memory based on the labels, the labels being corresponding to individual requests, wherein accessing a same area of the plurality of blocks The plurality of requests of the block result in an access arbitration that is performed in the same clock cycle as the access to the tag memory. A computer system as claimed in claim 15 wherein the accessing the data cache comprises a plurality of loads, the plurality of loads being performed in a single clock cycle. The computer system of claim 15, wherein each request for the plurality of requests for accessing the data cache has a dedicated copy of the tag corresponding to the bit in the load cache. The entry in . A computer system as claimed in claim 15 wherein the plurality of requests for accessing the data cache memory are searched for access to the respective blocks. The computer system of claim 15 wherein the plurality of requests for accessing the data cache are searched for different addresses of the same block in the same cycle. The computer system of claim 15 wherein the plurality of blocks comprise portions of a first-order data cache and includes a cache line entry.