TWI530869B - Method and apparatus for automatically repainting an external display - Google Patents
Method and apparatus for automatically repainting an external display Download PDFInfo
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- TWI530869B TWI530869B TW100147976A TW100147976A TWI530869B TW I530869 B TWI530869 B TW I530869B TW 100147976 A TW100147976 A TW 100147976A TW 100147976 A TW100147976 A TW 100147976A TW I530869 B TWI530869 B TW I530869B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
- G09G2330/022—Power management, e.g. power saving in absence of operation, e.g. no data being entered during a predetermined time
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/027—Arrangements or methods related to powering off a display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline
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Description
本發明大致上係有關於供以電腦為基礎之裝置用之顯示器。The present invention is generally directed to displays for use with computer based devices.
傳統上電腦可在顯示器上繪製影像。影像可經演色及然後,藉以適當色彩繪製像素在顯示器上繪製成產生該演色影像。影像在圖框內之位置係由其座標決定。該影像可從重疊的影像層中之一成員產生,各層係在該顯示器連續地繪製。Traditionally, computers can draw images on the display. The image can be color-coded and then rendered on the display by the appropriate color rendering pixels to produce the color image. The position of the image within the frame is determined by its coordinates. The image can be generated from one of the overlapping image layers, and the layers are continuously drawn on the display.
但於某些情況下,電腦系統可具有額外顯示器,該等顯示器係透過通用串列匯流排連結而耦接。更特別通用串列匯流排至數位視覺介面連結許可控制多個額外顯示器。此等顯示器稱作為外部或擴延顯示器可以克隆模式操作,其中該等顯示器顯示與主顯示器上顯示的相同資訊,或可以擴延顯示模式操作,其中該等顯示器顯示與顯示在主顯示器上的不同資訊。In some cases, however, the computer system may have additional displays that are coupled through a universal serial bus link. A more special universal serial bus to digital visual interface link control controls multiple additional displays. These displays are referred to as external or extended displays that can operate in clone mode, where the displays display the same information as displayed on the primary display, or can extend display mode operations, where the displays are displayed differently than those displayed on the primary display News.
依據本發明之一實施例,係特地提出一種方法包含檢測一系統懸置至一減低電力耗用態之一指示,及回應於檢測得該指示,自動地再繪製外部顯示器。In accordance with an embodiment of the present invention, a method is specifically provided for detecting an indication of a system suspension to a reduced power consumption state and automatically redrawing the external display in response to detecting the indication.
第1圖為一個實施例之系統說明圖;Figure 1 is a system explanatory diagram of an embodiment;
第2圖為依據本發明之一個實施例之通用串列匯流排至數位視覺介面連結之示意說明圖;及2 is a schematic explanatory diagram of a universal serial bus to digital visual interface connection according to an embodiment of the present invention; and
第3圖為本發明之一個實施例之流程圖。Figure 3 is a flow chart of one embodiment of the present invention.
參考第1圖,電腦系統10可包括含記憶體控制器中樞器14的耦接至晶片組之處理器12。於一個實施例中,記憶體控制器中樞器14可耦接至系統記憶體16。於若干實施例中,記憶體控制器中樞器14也可耦接至輸入/輸出(I/O)控制器中樞器18,後者也屬晶片組之一部分。控制器中樞器18可透過顯示器控制器20而控制主顯示器22。Referring to FIG. 1, computer system 10 can include a processor 12 coupled to a chipset including a memory controller hub 14. In one embodiment, the memory controller hub 14 can be coupled to the system memory 16. In some embodiments, the memory controller hub 14 can also be coupled to an input/output (I/O) controller hub 18, which is also part of the chip set. The controller hub 18 can control the main display 22 through the display controller 20.
也連結至I/O控制器中樞器18者可以是通用串列匯流排24。通用串列匯流排24係透過通用串列匯流排(USB)至數位視覺介面(DVI)鏈路26而耦接至外部或擴延顯示器28。參考數位視覺介面,版本1.0,起始規格,1999年4月2日得自數位顯示器工作群,美國華盛頓州溫哥華98683。Also connected to the I/O controller hub 18 may be a universal serial bus 24. The universal serial bus 24 is coupled to the external or extended display 28 via a universal serial bus (USB) to digital visual interface (DVI) link 26. Reference Digital Visual Interface, Version 1.0, Initial Specification, April 2, 1999 from the Digital Display Working Group, 98683, Vancouver, Washington, USA.
數位視覺介面(DVI)使用針對基本電氣互連體的變遷最小化差分傳訊而攜載未經壓縮的數位視訊資料至顯示器。單一DVI連結包括四對雙絞線分別傳輸紅、綠、藍、及時鐘。The Digital Visual Interface (DVI) carries uncompressed digital video data to the display using minimally differentiated differential signaling for basic electrical interconnects. A single DVI link consists of four pairs of twisted pairs that transmit red, green, blue, and clock respectively.
當然第1圖所示系統架構乃僅只多個可能架構中之一者。全部只需通用串列匯流排或其它連結至外部顯示器。Of course, the system architecture shown in Figure 1 is only one of many possible architectures. All only need a universal serial bus or other link to an external display.
依據本發明之若干實施例,當系統10為關閉或閂鎖時,通用串列匯流排至數位視覺介面連結26自動地採取某些動作來控制外部顯示器28。 In accordance with several embodiments of the present invention, the universal serial bus to digital visual interface link 26 automatically takes certain actions to control the external display 28 when the system 10 is closed or latched.
參考第2圖,通用串列匯流排至數位視覺介面連結26可包括一殼體30,而於若干實施例中,殼體30又轉而可包括插入通用串列匯流排24的通用串列匯流排控制器36(第1圖)。如此,控制器36包括遵守USB之連接器。參考通用串列匯流排3.0規格,得自USB體現者論壇,美國奧勒岡州比佛敦97006。然後於一個實施例中,通用串列匯流排控制器36耦接至殼體30內部的繪圖橋接器48。繪圖橋接器48選擇性地包括繪圖引擎38、韌體42、先進先出控制器44、及數位視覺介面變換裝置40。 Referring to FIG. 2, the universal serial bus bar to digital visual interface link 26 can include a housing 30, and in several embodiments, housing 30 can in turn include a universal serial confluence that is inserted into universal serial bus bar 24. Row controller 36 (Fig. 1). As such, the controller 36 includes a connector that adheres to the USB. Refer to the Universal Serial Bus 3.0 specification, available from the USB Innovator Forum, Beaverton, 97006, Oregon, USA. In one embodiment, the universal serial bus controller 36 is coupled to the drawing bridge 48 inside the housing 30. The drawing bridge 48 selectively includes a graphics engine 38, a firmware 42, a first in first out controller 44, and a digital visual interface conversion device 40.
繪圖引擎38及通用串列匯流排控制器36也係連結至復置脈衝產生電路46。於登入與登出中斷期間,復置脈衝產生電路46檢測得何時系統10為關閉或閂鎖,及回應之,自動地再繪製該外部或擴延顯示器28,如第1圖所示。(藉按下CTRL+ALT+DEL系統可被畫面閂鎖,提供中斷)。此外,電路可自動地儲存由作用中應用程式所顯示的畫面影像目前座標及層於圖框緩衝器。 The graphics engine 38 and the universal serial bus controller 36 are also coupled to the reset pulse generation circuit 46. During the login and logout interrupts, the reset pulse generation circuit 46 detects when the system 10 is off or latched, and in response, automatically redraws the external or extended display 28, as shown in FIG. (The system can be latched by the CTRL+ALT+DEL system to provide an interrupt). In addition, the circuit can automatically store the current coordinates of the picture image displayed by the active application and layer the picture buffer.
數位視覺介面變換裝置40連結至數位視覺介面埠控制器32,該埠控制器32可以在殼體30外側。埠控制器32包括連結至外部或擴延顯示器28的埠連接器34,只顯示於第1圖。連接器34可以是遵守DVI之連接器。 The digital visual interface transducer 40 is coupled to a digital visual interface controller 32, which may be external to the housing 30. The cymbal controller 32 includes a 埠 connector 34 coupled to the external or extended display 28, shown only in FIG. Connector 34 can be a DVI compliant connector.
於一個實施例中,當系統10進入S3休眠電力耗用態,相當於電力被拔除,復置脈衝產生電路46檢測得S3態。參考進階組態及電力介面規格版本4.0,2009年6月16日。S3休眠態乃低喚醒延遲休眠態,於該處全部系統脈絡皆喪失只有系統記憶體除外。處理器、快取記憶體、及晶片組脈絡在此狀態皆喪失。硬體維持記憶體脈絡,及復原某個處理器及L2快取記憶體組態脈絡。在喚醒事件後控制係始於處理器的復置向量。In one embodiment, when system 10 enters the S3 sleep power consumption state, equivalent to the power being removed, reset pulse generation circuit 46 detects the S3 state. Refer to Advanced Configuration and Power Interface Specification Version 4.0, June 16, 2009. The S3 sleep state is a low wake-up delay sleep state where all system contexts are lost except for system memory. The processor, cache memory, and chipset context are lost in this state. The hardware maintains the memory network and restores a processor and L2 cache memory configuration context. The control system begins with the processor's reset vector after the wake event.
S3信號係由晶片組宣告,諸如輸入/輸出控制器中樞器18或記憶體控制器中樞器14來指示系統即將進入低電力耗用態。S3信號可藉外部USB-DVI連結26監視來從普通再新模式切換成懸置模式或S3再新模式。S3態也由其它周邊USB裝置作為指示來指示須隔離其輸入,該輸入即將進入電力關閉平面。USB-DVI連結26的電力維持來自系統10的開啟狀態來允許於S3態期間檢測喚醒事件。The S3 signal is asserted by the chipset, such as the input/output controller hub 18 or the memory controller hub 14 to indicate that the system is about to enter a low power consumption state. The S3 signal can be switched from the normal regeneration mode to the suspend mode or the S3 renew mode by external USB-DVI link 26 monitoring. The S3 state is also indicated by other peripheral USB devices as indicating that the input must be isolated, which is about to enter the power-off plane. The power of the USB-DVI link 26 is maintained from the on state of the system 10 to allow detection of wake events during the S3 state.
一旦晶片組(例如中樞器14或18中之一者)宣告S3信號給USB-DVI連結26,理想上該晶片組讓USB-DVI連結26有時間準備進入懸置電力耗用模式。但因USB-DVI連結26富含媒體,故經常沒有足夠時間來在配置的時間內完成懸置模式處理程序。因此任一個開啟的應用程式可能仍維持開啟,但主機系統10已經懸置進入S3休眠態。Once the chipset (e.g., one of the hubs 14 or 18) announces the S3 signal to the USB-DVI link 26, the chipset desirably has time for the USB-DVI link 26 to be ready to enter the suspended power drain mode. However, since the USB-DVI link 26 is rich in media, there is often not enough time to complete the suspend mode handler within the configured time. Therefore, any open application may still remain open, but the host system 10 has been suspended into the S3 sleep state.
但復置脈衝產生電路46允許即便系統10已經傳訊S3態後仍然繼續懸置模式處理程序。一旦宣告S3休眠信號,USB-DVI連結26可維持電力啟動,微軟視窗(Windows)標準驅動程式可與復置脈衝產生電路46協作來將當懸置被傳訊時作用中的各個應用程式層及該等應用程式各自的座標儲存入圖框緩衝器。然後,復置脈衝產生電路46自動地再繪製該外部顯示器28之畫面及完成懸置模式處理程序。當出現S3休眠態恢復時,藉從該圖框緩衝器召回座標及層在S3懸置時在USB-DVI連結上的任何內容皆被恢復。如此,各個應用程式被恢復至在S3懸置時的相同狀態,具有相同的畫面影像顯示。However, the reset pulse generation circuit 46 allows the suspend mode processing routine to continue even after the system 10 has transmitted the S3 state. Once the S3 sleep signal is asserted, the USB-DVI link 26 can maintain power-on, and the Microsoft Windows (Windows) standard driver can cooperate with the reset pulse generation circuit 46 to apply the various application layers that are active when the suspension is being transmitted. The respective coordinates of the application are stored in the frame buffer. The reset pulse generation circuit 46 then automatically redraws the picture of the external display 28 and completes the suspend mode processing routine. When the S3 sleep state recovery occurs, any content on the USB-DVI link is recalled by the frame buffer recall coordinates and layers when the S3 is suspended. In this way, each application is restored to the same state when S3 is suspended, and has the same screen image display.
於若干實施例中,主機微軟視窗驅動程式自動地開關復置脈衝來復置任何未被清除的圖形緩衝器。同時,微軟視窗登出圖框可重疊在前一個畫面頂上。於若干實施例中,此點不具裝置特異性,原因在於係來自於通用串列匯流排至數位視覺介面連結26內部。比較若操作並非直接在連結26內部處置時須通過多個組件,登出圖框重疊可給予更多延遲來寫至外部通用串列匯流排、數位視覺介面圖框緩衝器。In several embodiments, the host Microsoft Windows driver automatically switches the reset pulse to reset any graphics buffer that has not been cleared. At the same time, the Microsoft Windows logout frame can be overlaid on top of the previous screen. In some embodiments, this point is not device specific because it comes from the universal serial busbar to the interior of the digital visual interface link 26. Comparison If the operation is not directly through the internal processing of the link 26 through multiple components, the logout overlap can give more delay to write to the external universal serial bus, digital visual interface frame buffer.
如此,依據若干實施例,軟體、韌體、或硬體可體現第3圖之順序50。於軟體實施例中,一序列指令可藉以處理器為基礎之裝置執行。該等指令可儲存於半導體、磁性、或光學記憶體。舉例言之,順序50可以是儲存在繪圖橋接器48內部的韌體42之一部分。韌體42可藉繪圖引擎38執行,於若干實施例中,繪圖引擎38可以是以處理器為基礎之裝置。As such, in accordance with several embodiments, the software, firmware, or hardware may embody the sequence 50 of FIG. In a software embodiment, a sequence of instructions can be executed by a processor-based device. These instructions can be stored in semiconductor, magnetic, or optical memory. For example, the sequence 50 can be part of the firmware 42 stored inside the drawing bridge 48. The firmware 42 can be executed by the graphics engine 38. In some embodiments, the graphics engine 38 can be a processor-based device.
如此,順序50初始地決定主機系統10是否為閂鎖或關閉。由於電路46動作的結果,外部顯示器28可被再繪製,及應用程式層及應用程式座標分別地可被檢測,如於第3圖中方塊56及54顯示。As such, the sequence 50 initially determines whether the host system 10 is latched or closed. As a result of the operation of circuit 46, external display 28 can be redrawn, and application layer and application coordinates can be detected separately, as shown in blocks 56 and 54 of FIG.
於若干實施例中,前文描述之操作為優異,原因在於否則當使用通用串列匯流排至數位視覺介面連結時,外部螢幕上的影像之清除或再繪製將要求用戶使用滑鼠跑遍外部螢幕或關閉外部螢幕的電源。於本發明之若干實施例中,用戶無需關閉外部電流或手動藉滑鼠來清除外部螢幕上的影像或重新繪製影像。當系統被閂鎖或關閉電力時,復置脈衝產生電路自動地修復外部螢幕。In some embodiments, the operations described above are superior because otherwise the image clearing or redrawing on the external screen will require the user to run through the external screen using the universal serial bus to the digital visual interface link. Or turn off the power to the external screen. In some embodiments of the invention, the user does not need to turn off the external current or manually use the mouse to clear the image on the external screen or redraw the image. The reset pulse generation circuit automatically repairs the external screen when the system is latched or powered off.
本說明書中述及「一個實施例」或「一實施例」表示聯結該實施例所述特定特徵、結構、或特性係含括於涵蓋於本發明內部至少一項體現的該實施例。如此,出現「一個實施例」或「於一實施例中」等詞並非必要全部皆係指相同實施例。此外,該等特定特徵、結構、或特性可以所例示說明之特定實施例以外的其它適當方式組合,及全部此等形式皆係涵蓋於本案之申請專利範圍內。The description of "one embodiment" or "an embodiment" in this specification means that the specific features, structures, or characteristics described in connection with the embodiment are included in the embodiment of the invention. Thus, the words "in one embodiment" or "in an embodiment" are not necessarily all referring to the same embodiment. In addition, the specific features, structures, or characteristics may be combined in any suitable manner other than the specific embodiments illustrated, and all such forms are included in the scope of the present application.
雖然已經就有限數目的實施例敘述本發明,但熟諳技藝人士將瞭解從其中可做出無數修改及變化。預期隨附之申請專利範圍涵蓋落入於本發明之精髓及範圍內的全部此等修改及變化。Although the present invention has been described in terms of a limited number of embodiments, those skilled in the art will appreciate that numerous modifications and changes can be made therein. All such modifications and variations that come within the spirit and scope of the invention are intended to be included.
10...電腦系統10. . . computer system
12...處理器12. . . processor
14...記憶體控制器中樞器(MCH)14. . . Memory controller hub (MCH)
16...系統記憶體16. . . System memory
18...輸入/輸出(I/O)控制器中樞器18. . . Input/output (I/O) controller hub
20...顯示器控制器20. . . Display controller
22...主顯示器twenty two. . . Main display
24...通用串列匯流排(USB)twenty four. . . Universal Serial Bus (USB)
26...USB-數位視覺介面(DVI)連結26. . . USB-Digital Visual Interface (DVI) link
28...外部顯示器28. . . External display
30...殼體30. . . case
32...DVI埠控制器32. . . DVI controller
34...埠連接器34. . .埠 connector
36...USB控制器36. . . USB controller
38...繪圖引擎38. . . Drawing engine
40...DVI介面控制器裝置40. . . DVI interface controller device
42...韌體42. . . firmware
44...先進先出(FIFO)控制器44. . . First in first out (FIFO) controller
46...復置脈衝產生電路46. . . Reset pulse generating circuit
48...繪圖橋接器48. . . Drawing bridge
50...順序50. . . order
52、54、56...處理方塊52, 54, 56. . . Processing block
第1圖為一個實施例之系統說明圖;Figure 1 is a system explanatory diagram of an embodiment;
第2圖為依據本發明之一個實施例之通用串列匯流排至數位視覺介面連結之示意說明圖;及2 is a schematic explanatory diagram of a universal serial bus to digital visual interface connection according to an embodiment of the present invention; and
第3圖為本發明之一個實施例之流程圖。Figure 3 is a flow chart of one embodiment of the present invention.
10...電腦系統10. . . computer system
12...處理器12. . . processor
14...記憶體控制器中樞器(MCH)14. . . Memory controller hub (MCH)
16...系統記憶體16. . . System memory
18...輸入/輸出(I/O)控制器中樞器18. . . Input/output (I/O) controller hub
20...顯示器控制器20. . . Display controller
22...主顯示器twenty two. . . Main display
24...通用串列匯流排(USB)twenty four. . . Universal Serial Bus (USB)
26...USB-數位視覺介面(DVI)連結26. . . USB-Digital Visual Interface (DVI) link
28...外部顯示器28. . . External display
Claims (20)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US13/027,650 US9081573B2 (en) | 2010-02-19 | 2011-02-15 | Method and apparatus for automatically repainting an external display during transitioning to a low power state |
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TW201246057A TW201246057A (en) | 2012-11-16 |
TWI530869B true TWI530869B (en) | 2016-04-21 |
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TW100147976A TWI530869B (en) | 2011-02-15 | 2011-12-22 | Method and apparatus for automatically repainting an external display |
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TW (1) | TWI530869B (en) |
WO (1) | WO2012112221A2 (en) |
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KR100498941B1 (en) * | 2003-02-04 | 2005-07-04 | 삼성전자주식회사 | Composite personal digital assistant for controlling external display and method therein |
US20100079444A1 (en) * | 2008-09-30 | 2010-04-01 | Apple Inc. | Displayport sleep behavior |
US8207974B2 (en) * | 2008-12-31 | 2012-06-26 | Apple Inc. | Switch for graphics processing units |
US8238979B2 (en) * | 2009-04-14 | 2012-08-07 | Qualcomm Incorporated | System and method for mobile device display power savings |
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WO2012112221A3 (en) | 2012-11-01 |
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