TWI528287B - Server system - Google Patents

Description

Server system

The present invention relates to the field of server technology, and more particularly to a server system.

The server is an important foundation of the network architecture. Usually in the server, the Basic Input/Output System (BIOS) is an extremely important module. At the time of power-on, it is necessary to initialize the respective hardware devices according to the settings of the basic input/output system, so that after the operating system starts operating, it is possible to operate the respective hardware devices.

At present, most of the BIOS chips are set in the server system. If the power on self-test (POST) fails, the firmware of the BIOS chip needs to be repaired or updated offline, which will cause inconvenience to the user. . If another BIOS chip is set in the server system, when one of the BIOS chips fails to perform boot self-test (POST) or its firmware itself is defective, the server system automatically switches to another BIOS chip to make the servo The system can start normally. As a result, this greatly facilitates the data center or the organization that uses a large number of servers. The above-mentioned backup BIOS chip design is also used in the conventional desktop computer, but it must be manually intervened to achieve the effect of switching the BIOS chip.

In the conventional design, the BIOS chip to be monitored is electrically powered by using a Baseboard Management Controller (BMC) installed in the server system. The serial interface is connected to the Serial Peripheral Interface (SPI) of the baseboard management controller to implement the purpose of monitoring whether the BIOS chip is normally booted and self-detected. However, if two BIOS chips are simultaneously electrically connected to the substrate management controller, there is a problem in how to distinguish the above two BIOS chips to determine that one of the BIOS chips can be used to enable the server system to start normally.

Therefore, there is an urgent need to provide an innovative server system to solve the above problems.

In order to solve the above problems of the prior art, it is an object of the present invention to provide a server system for automatically booting from another BIOS when the server system fails to boot from one of the first BIOS chip and the second BIOS chip. The wafer is booted, and further, the firmware of the failed BIOS chip can be updated simultaneously through the substrate management controller to ensure the security and reliability of the server system.

To achieve the above object, the present invention provides a server system including a first BIOS chip, a second BIOS chip, a platform controller, and a substrate management controller. The platform controller is electrically connected to a first multiplexer, and the first multiplexer is electrically connected to the first BIOS chip and the second BIOS chip, respectively. The substrate management controller is electrically connected to a second multiplexer, and the second multiplexer is electrically connected to the first BIOS chip and the second BIOS chip, respectively.

As an alternative embodiment, when the server system fails to boot from one of the first BIOS chip and the second BIOS chip, it will automatically boot from another BIOS chip.

As an alternative embodiment, when the server system is from the first BIOS chip and When one of the BIOS chips of the second BIOS chip fails to boot, it will automatically boot from another BIOS chip, and the substrate management controller simultaneously updates the firmware of the failed BIOS chip.

As an optional embodiment, the server system updates the firmware of the failed BIOS chip through the firmware of the BIOS chip included in the baseboard management controller.

As an alternative embodiment, the server system receives an external update command to update the firmware of the first BIOS chip or the second BIOS chip.

In an optional embodiment, the substrate management controller includes at least one third GPIO pin, and the at least one third GPIO pin is electrically connected to the selection pin of the first multiplexer and the second multiple The selector pin of the way selector.

As an alternative embodiment, the first multiplexer and the second multiplexer each comprise a plurality of sets of output pins.

In an optional embodiment, the at least one third GPIO pin includes a fourth GPIO pin; the fourth GPIO pin is electrically connected to the select pin of the first multiplexer through an inverter. And the fourth GPIO pin is electrically connected to the selection pin of the second multiplexer.

In an optional embodiment, the at least one third GPIO pin includes a fifth GPIO pin and a sixth GPIO pin; the fifth GPIO pin is electrically connected to the first multiplexer. The pin, and the sixth GPIO pin are electrically connected to the select pin of the second multiplexer.

In an optional embodiment, the platform controller is connected to the first BIOS chip through the first group of output pins of the first multiplexer in a predetermined state, thereby starting the servo through the first BIOS chip. System.

As an optional embodiment, when the substrate management controller detects the first If the BIOS chip fails to self-test, the baseboard management controller automatically sends a control command to the first multiplexer, and the platform controller transmits the second set of output pins of the first multiplexer and the second The BIOS chip is turned on, and the substrate management controller sends a reset command to enable the second BIOS chip to perform boot automatic detection to start the server system.

In an optional embodiment, after the baseboard management controller sends the control command to the first multiplexer, the baseboard management controller transmits the first set of output pins of the second multiplexer with the first The BIOS chip is turned on and the substrate management controller updates the firmware of the first BIOS chip.

In an optional embodiment, when the substrate management controller sends the control command to the first multiplexer, the control command switches a high potential signal to a low potential signal.

As an optional embodiment, the base management controller performs a dedicated command of the baseboard management controller through a remote or local mode to update the firmware of the first BIOS chip.

In an optional embodiment, the platform controller is electrically connected to the baseboard management controller for communication of control messages.

In an optional embodiment, the platform controller includes at least one first GPIO pin, the at least one first GPIO pin is electrically connected to the selection pin of the first multiplexer, and the substrate management controller includes The at least one second GPIO pin is electrically connected to the selection pin of the second multiplexer.

In an optional embodiment, the first multiplexer and the second multiplexer each comprise a plurality of sets of output pins, and the first multiplexer and the second multiplexer select a communication number The default is a valid signal, and the first set of output pins of the multiple sets of output pins are selected.

In an optional embodiment, the platform controller communicates with the first multiplexer via a first SPI signal and at least one first GPIO signal, and the substrate management controller transmits a second SPI signal and at least a second The GPIO signal communicates with the second multiplexer.

In an optional embodiment, the platform controller selects to enable the selection signal of the first multiplexer by using the first GPIO signal to transmit the first SPI signal to the first BIOS chip or the second BIOS. a chip, the substrate management controller selects, by using the second GPIO signal, to enable a selection communication number of the second multiplexer to transmit the second SPI signal to the first BIOS chip or the second BIOS chip, and the When the platform controller selects to enable the selection communication number of the first multiplexer through the first GPIO signal, the baseboard management controller prohibits selection of the selection communication number of the second multiplexer by using the second GPIO signal.

An advantage of the present invention is that it can be automatically initiated from another BIOS chip when the server system fails to boot from one of the first BIOS chip and the second BIOS chip. Further, the firmware of the failed BIOS chip can be updated simultaneously through the substrate management controller, thereby not affecting the normal operation of the server system, thereby improving the security and reliability of the server system. In addition, the first BIOS chip and the second BIOS chip can be further distinguished and controlled by the GPIO pins of the substrate management controller to implement the function of the backup BIOS.

110, 210‧‧‧ platform controller

120, 220‧‧‧Base management controller

130, 230‧‧‧ first multiplexer

131, 141‧‧‧ first set of output pins

132, 142‧‧‧Second group of output pins

140, 240‧‧‧ second multiplexer

150, 250‧‧‧ first BIOS chip

160, 260‧‧‧ second BIOS chip

270‧‧‧Inverter

The above and other objects, features, and advantages of the present invention will become more apparent from the description of the accompanying drawings. Functional block diagram.

Figure 2 shows a functional block diagram of a server system in accordance with another preferred embodiment of the present invention.

The specific implementation of the server system provided by the present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1, there is shown a functional block diagram of a server system including a first BIOS chip 150, a second BIOS chip 160, and a platform controller 110 in accordance with a preferred embodiment of the present invention. And a substrate management controller 120. The platform controller 110 is electrically connected to a first multiplexer 130. The first multiplexer 130 is electrically connected to the first BIOS chip 150 and the second BIOS chip 160, respectively. The substrate management controller 120 is electrically connected to a second multiplexer 140, and the second multiplexer 140 is electrically connected to the first BIOS chip 150 and the second BIOS chip 160, respectively. When the server system fails to boot from one of the first BIOS chip 150 and the second BIOS chip 160, it will automatically boot from another BIOS chip. In detail, when the boot failure from the first BIOS wafer 150 fails, it will automatically boot from the second BIOS wafer 160. When the boot failure from the second BIOS wafer 160 fails, it will automatically boot from the first BIOS wafer 150. The present invention is capable of providing automatic switching between two BIOS chips as compared to conventional techniques requiring manual switching. Further, when the server system fails to boot from one of the first BIOS chip 150 and the second BIOS chip 160, the server system will be automatically booted from another BIOS chip, and the substrate management controller 120 can be updated simultaneously. The firmware (version) of the failed BIOS chip is initiated, which is not implemented in the prior art. The process of simultaneously updating the firmware (version) of the BIOS chip that failed to boot the substrate management controller 120 will be further described below.

In addition, the server system is included in the firmware of the baseboard management controller 120. The firmware update of the BIOS chip initiates the firmware of the failed BIOS chip. In this embodiment, the firmware of the first BIOS chip 150 and the firmware of the second BIOS chip 160 are included in the substrate management controller 120, and the firmware of the first BIOS chip 150 and the firmware of the second BIOS chip 160 are The same firmware ensures that when the boot failure of any of the above BIOS chips fails, the server system can be booted from another BIOS chip without affecting the operation of the original server system, thereby ensuring the reliability of the server system. Before the baseboard management controller 120 can simultaneously update the firmware of the failed BIOS chip, the server system receives an externally issued update command to perform firmware on the failed first BIOS chip 150 or the second BIOS chip 160. Update. In this embodiment, when the GPIO (General-purpose input/output) pin of the substrate management controller 120 is electrically connected to the second multiplexer 140, in this configuration, it can be transmitted. A remote client or a local client and a dedicated instruction (eg, an IPMI command) of the baseboard management controller 120 is used to send an update command to the first BIOS chip 150 or the second BIOS chip 160 that failed to be initiated via the baseboard management controller 120. The firmware is updated. In other embodiments, when the GPIO pin of the platform controller 110 is electrically connected to the first multiplexer 130, in this configuration, the update command may also pass through the platform controller 110 to the first BIOS chip. The firmware of 150 or the second BIOS chip 160 is updated. It should be noted that, in this embodiment, the update instruction is to update the firmware of the first BIOS chip 150 or the second BIOS chip 160 that failed to start. Similarly, in other embodiments, the update instructions are also applicable to firmware updates to the normal first BIOS chip 150 or the second BIOS chip 160. In addition, in the above two different configurations, the process of updating the firmware of the first BIOS chip 150 or the second BIOS chip 160 through the substrate management controller 120 or through the platform controller 110 respectively will be described in further detail below.

Continuing to refer to FIG. 1 , in the embodiment, the platform controller 110 is electrically connected to The substrate management controller 120 performs communication of control messages. In detail, the platform controller 110 is electrically connected to the baseboard management controller 120 through an LPC (Low Pin Count) communication link to perform control message transmission.

The platform controller 110 includes at least one first GPIO pin, the at least one first GPIO pin is electrically connected to the selection pin of the first multiplexer 130, and the substrate management controller 120 includes at least one second GPIO pin. The at least one second GPIO pin is electrically connected to the select pin of the second multiplexer 140. Further, the first multiplexer 130 and the second multiplexer 140 each include a plurality of sets of output pins (eg, two sets of output pins), and the first multiplexer 130 and the second multiplexer The default communication number of 140 is the opposite signal, that is, the selected communication number of the first multiplexer 130 is a valid signal, and the selected communication number of the second multiplexer 140 is an invalid signal, first The first set of output pins 131 of the plurality of sets of output pins of the multiplexer 130 are selected, and the second set of output pins 142 of the plurality of sets of output pins of the second multiplexer 140 are selected. In this embodiment, such a default setting is made. Certainly, the opposite setting may also be performed, that is, the selected communication number of the first multiplexer 130 is an invalid signal, and the selected communication number of the second multiplexer 140 is a valid signal, and the first multiplexer 130 is A second set of output pins 132 of the plurality of sets of output pins are selected, and a first set of output pins 141 of the plurality of sets of output pins of the second multiplexer 140 are selected. In this case, the other logic that follows will also need to change.

In this embodiment, the platform controller 110 communicates with the first multiplexer 130 via a first SPI signal and at least one first GPIO signal, and the substrate management controller 120 transmits a second SPI signal and at least a second GPIO. The signal communicates with the second multiplexer 140. It should be noted that in this configuration, the platform controller 110 and the baseboard management controller 120 are connected through an LPC communication link for control message transmission.

Further, the platform controller 110 transmits the first SPI signal to the first BIOS chip 150 or the second BIOS chip 160 by using the first GPIO signal to enable the selection communication number of the first multiplexer 130, and the substrate management controller 120 The second SPI signal is transmitted to the first BIOS chip 150 or the second BIOS chip 160 by the selection signal of the second multiplexer 140 being selected by the second GPIO signal, and the platform controller 110 selects the first GPIO signal through the first GPIO signal. When the selection communication number of the first multiplexer 130 is turned on, the substrate management controller 120 prohibits selection of the selection communication number of the second multiplexer 140 by the second GPIO signal. In this embodiment, at least one first GPIO pin of the platform controller 110 and at least one second GPIO pin of the substrate management controller 120 communicate through the LPC to the first multiplexer 130 and the second plurality. The way selector 140 makes an alternative selection to achieve an alternative to the first BIOS chip 150 and the second BIOS chip 160. More specifically, when the platform controller 110 selects to open the selected communication number of the first multiplexer 130 through the first GPIO signal and turns on the first BIOS chip 150, the substrate management controller 120 selects according to one or the other. The second BIOS chip 160 is turned on by the second multiplexer 140. When the platform controller 110 selects the selected multiplex number of the first multiplexer 130 and turns on the second BIOS chip 160 through the first GPIO signal, The substrate management controller 120 turns on the first BIOS chip 150 through the second multiplexer 140 according to the selection principle of either or both.

For example, in a normal state, the platform controller 110 communicates with the first multiplexer 130 through the first SPI signal and the at least one first GPIO signal, and the substrate management controller 120 transmits the second The SPI signal and the at least one second GPIO signal communicate with the second multiplexer 140. When the first BIOS chip 150 fails to perform the boot self-detection, the platform controller 110 finds that the first BIOS chip 150 fails to start, and the platform controller 110 transmits a control message to the baseboard management controller 120 through the LPC communication link. At the same time, the platform controller 110 is based on (software) The predetermined setting sends the first GPIO signal to the first multiplexer 130. After receiving the first GPIO signal, the selection pin of the first multiplexer 130 selects the first GPIO signal as the selected communication number, and determines whether the selected communication number is For the valid signal, if it is a valid signal, the first set of output pins 131 of the first multiplexer 130 is selected, and if it is an invalid signal, the second set of output pins 132 of the first multiplexer 130 is chosen. When it is determined that the selected communication number is an invalid signal, the second group of output pins 132 of the first multiplexer 130 is selected, and the platform controller 110 transmits the first SPI signal to the first multiplexer. The second set of output pins 132 of the 130 are transmitted to the second BIOS chip 160 electrically connected to the second set of output pins 132. When the first BIOS chip 150 is started normally, the platform controller 110 selects the first GPIO signal. Turning on the selected communication number of the first multiplexer 130 as a valid signal, the first group of output pins 131 of the first multiplexer 130 is selected, and the platform controller 110 transmits the first SPI signal through the first multiplexer The first set of output pins 131 of the selector 130 are passed to a first BIOS chip 150) that is electrically coupled to the first set of output pins 131. Since the baseboard management controller 120 receives a control message transmitted from the platform controller 110, the baseboard management controller 120 sends a reset command to cause the second BIOS chip 160 to perform boot self-detection to activate the server system. At the same time, the substrate management controller 120 sends the second GPIO signal to the second multiplexer 140. The selection pin of the second multiplexer 140 receives the second GPIO signal, uses it as the selection communication number, and determines whether the selected communication number is a valid signal. If it is a valid signal, the second multiplexer The first set of output pins 141 of 140 is selected, and if it is an invalid signal, the second set of output pins 142 of the second multiplexer 140 is selected. When it is determined that the selected communication number is a valid signal, the first group of output pins 141 of the second multiplexer 140 is selected, and the substrate management controller 120 transmits the second SPI signal to the second multiplexer 140. The first set of output pins 141 are transferred to the first BIOS chip 150 electrically connected to the first set of output pins 141, and the substrate management controller 120 updates the first The firmware of the BIOS chip 150 (when the first BIOS chip 150 is started normally, the substrate management controller 120 sends the second GPIO signal to the second multiplexer 140. It is determined that the second GPIO signal is selected to be turned on by the second GPIO signal. The selected communication number of the multiplexer 140 is an invalid signal, the second set of output pins 142 of the second multiplexer 140 is selected, and the substrate management controller 120 transmits the second SPI signal through the second multiplexer. The second set of output pins 142 of 140 is transferred to a second BIOS die 160) that is electrically coupled to the second set of output pins 142. In addition, when the platform controller 110 selects to enable the selection communication number of the first multiplexer 130 through the first GPIO signal, the substrate management controller 120 prohibits selection and enables the second multiplex selection through the second GPIO signal. Selecting the communication number of the device 140, thereby realizing the purpose of the platform controller 110 and the substrate management controller 120 to logically select the first BIOS chip 150 or the second BIOS chip 160 through software preset, and the selection has one or the other effect.

Referring to FIG. 2, in another preferred embodiment, the substrate management controller 220 includes at least one third GPIO pin, and the at least one third GPIO pin is electrically connected to the first multiplexer 230. The pin and the select pin of the second multiplexer 240. The first multiplexer 230 and the second multiplexer 240 each include multiple sets of output pins, for example, two sets of output pins, specifically the first set of output pins of the first multiplexer 230 ( For example, reference numeral 230 in Figure 2 corresponds to the 1B1 pin, 2B1 pin, 3B1 pin, and 4B1 pin shown in the component, the following are the same) and the second group of output pins (such as the corresponding component 230 in Figure 2) The 1B2 pin, the 2B2 pin, the 3B2 pin, and the 4B2 pin are shown as follows; and the first set of output pins of the second multiplexer 240 (as indicated by the corresponding component of the reference numeral 240 in FIG. 2) 1B1 pin, 2B1 pin, 3B1 pin and 4B1 pin, the following are the same) and the second group of output pins (such as the 1B2 pin, 2B2 pin, 3B2 shown in the corresponding component of the reference numeral 240 in Fig. 2) Pin and 4B2 pin, the same applies below). First multiplexer 230 and The two-way selector 240 uses a 74CBT3257 type selector, and the model of the multiplexer is not intended to limit the present invention.

In the preferred embodiment, the at least one third GPIO pin includes a fourth GPIO pin, and the fourth GPIO pin is electrically connected to the first multiplexer 230 through an inverter 270. The pin, and the fourth GPIO pin are electrically connected to the select pin of the second multiplexer 240. In other embodiments, the at least one third GPIO pin may also include a fifth GPIO pin and a sixth GPIO pin; the fifth GPIO pin is electrically connected to the first multiplexer 230. The select pin, and the sixth GPIO pin are electrically connected to the select pin of the second multiplexer 240. If the GPIO pin and the inverter 270 are configured in the preferred embodiment, only one GPIO pin is needed, thereby saving GPIO pins. Inverter 270 is a common inverter and its structure and function will not be described in detail herein. In the default state, the platform controller 210 transmits the first set of output pins of the first multiplexer 230 (such as the 1B1 pin, the 2B1 pin, the 3B1 pin, and the 4B1 pin shown in FIG. 2). The first BIOS chip 250 is turned on to activate the server system through the first BIOS chip 250.

When the substrate management controller 220 detects that the first BIOS wafer 250 fails to start, the substrate management controller 220 automatically sends a control command to the first multiplexer 230, and the platform controller 210 transmits the first multiplexer 230. Two sets of output pins (such as the 1B2 pin, the 2B2 pin, the 3B2 pin, and the 4B2 pin shown in FIG. 2) are connected to the second BIOS chip 260, and the substrate management controller 220 sends a reset command. In order for the second BIOS chip 260 to perform boot self-detection to activate the server system, when the server system fails to boot from one of the first BIOS chip 250 and the second BIOS chip 260, the BIOS will automatically boot from another BIOS. The purpose of wafer startup. Further, since the first multiplexer 230 and the second multiplexer 240 are independent of each other, Therefore, the firmware of the failed BIOS chip can be simultaneously updated through the substrate management controller 220, thereby not affecting the normal operation of the server system, thereby improving the security and reliability of the server system.

In detail, since the platform controller 210 and the baseboard management controller 220 communicate through the LPC communication link to obtain control information, when the first BIOS chip 250 starts up normally, the platform controller 210 sends a control message to the baseboard management. Controller 220. When the first BIOS chip 250 fails to perform the boot self-detection, the platform controller 210 that is originally connected to the first BIOS chip 250 finds that the first BIOS wafer 250 fails to start, and the platform controller 210 transmits the control message to the baseboard management controller. 220. The baseboard management controller 220 detects that the first BIOS chip 250 fails to start, and automatically sends a control command to the first multiplexer 230. When the substrate management controller 220 sends the control command to the first multiplexer 230, the control command switches a high potential signal to a low potential signal (ie, the selection pin of the first multiplexer 230 receives the The potential signal is switched from a high level to a low level, and the potential signal received by the selection pin of the second multiplexer 240 is switched from a low level to a high level). It should be noted that in the preferred embodiment, the selection pin of the first multiplexer 230 and the selection pin of the second multiplexer 240 have a constant high potential, and the first selection is performed when the high potential is active. Group output pins (such as 1B1 pin, 2B1 pin, 3B1 pin, and 4B1 pin shown in Figure 2), and select the second set of output pins at low potential (as shown in Figure 2) 1B2 pin, 2B2 pin, 3B2 pin, and 4B2 pin). Then, after the substrate management controller 220 sends the control command to the first multiplexer 230, the platform controller 210 transmits the second set of output pins of the first multiplexer 230 (as shown in FIG. 2). The 1B2 pin, the 2B2 pin, the 3B2 pin and the 4B2 pin are connected to the second BIOS chip 260, and the substrate management controller 220 controller sends a reset command to enable the second BIOS chip 260 to perform boot self-detection. Start the server system. At the same time, the substrate management controller 220 transmits the first set of output pins of the second multiplexer 240. (1B1 pin, 2B1 pin, 3B1 pin, and 4B1 pin as shown in FIG. 2) are connected to the first BIOS chip 250, and the substrate management controller 220 updates the firmware of the first BIOS chip 250 ( version). The firmware of the first BIOS chip 250 may be updated by the substrate management controller 220 and by a remote or local manner to execute a dedicated command (eg, an IPMI command) of the baseboard management controller 220.

In addition, the baseboard management controller 220 includes a temporary storage unit (not shown) for storing the first BIOS chip 250 or the second BIOS chip 260 to perform a boot self-detection failure (or startup failure) record message. In order to be able to determine which of the first BIOS chip 250 and the second BIOS chip 260 has failed to boot self-test or has a defect in itself, so as to be updated to the failed BIOS chip through the firmware included in the substrate management controller 220. The firmware improves maintenance efficiency.

In the above preferred embodiment, only the failure of the first BIOS chip 250 to boot self-test is taken as an example to illustrate that when the first BIOS chip 250 fails to boot self-test and fails to start the server system, it will automatically be from the first BIOS. The wafer 250 switches to the second BIOS wafer 260 and passes through the second BIOS wafer 260 to initiate the server system and simultaneously update the firmware of the first BIOS wafer 250.

Of course, in another embodiment of the present invention, reference may be made to FIG. 2, the structure of the embodiment is the same as that of the preferred embodiment shown in FIG. 2, and the multiplexers of the two (first The selection of the select pin of the multiplexer 230 and the second multiplexer 240) and the setting of the corresponding output pin when active are different. In this embodiment, the default state is that the platform controller 210 transmits the second set of output pins of the first multiplexer 230 (such as the 1B2 pin, the 2B2 pin, the 3B2 pin, and the 4B2 shown in FIG. 2). Pin) is connected to the second BIOS chip 260, if When the second BIOS chip 260 fails to boot self-test, the platform controller 210, which is originally connected to the second BIOS chip 260, finds that the second BIOS chip 260 fails to start, the platform controller 210 transmits a control message to the substrate management controller 220. When the substrate management controller 220 detects that the second BIOS chip 260 fails to start, it automatically sends a control command to the first multiplexer 230. When the substrate management controller 220 sends the control command to the first multiplexer 230, the control command switches a low potential signal to a high potential signal (ie, the selection pin of the first multiplexer 230 receives the The potential signal is switched from a low level to a high level, and the potential signal received by the selection pin of the second multiplexer 240 is switched from a high level to a low level). It should be noted that, in this embodiment, the select pin of the first multiplexer 230 and the select pin of the second multiplexer 240 are internally asserted low, and the second set of outputs is selected when the low potential is active. Pins (such as 1B2 pin, 2B2 pin, 3B2 pin, and 4B2 pin shown in Figure 2), and select the first set of output pins at high potential (such as 1B1 shown in Figure 2) Pin, 2B1 pin, 3B1 pin, and 4B1 pin). Then, after the substrate management controller 220 automatically sends the control command to the first multiplexer 230, the platform controller 210 transmits the first set of output pins of the first multiplexer 230 (as shown in FIG. 2). The 1B1 pin, the 2B1 pin, the 3B1 pin, and the 4B1 pin are connected to the first BIOS chip 250, and the substrate management controller 220 controller sends a reset command to enable the first BIOS chip 250 to perform boot self-detection. To start the server system. After the baseboard management controller 220 sends the control command to the first multiplexer 230, the baseboard management controller 220 transmits the second set of output pins of the second multiplexer 240 (as shown in FIG. 2BB). The pins, 2B2 pins, 3B2 pins, and 4B2 pins are turned on with the second BIOS chip 260, and the substrate management controller 220 updates the firmware (version) of the second BIOS chip 260.

In the above, the setting of the multiplexer's selection pin is valid and the setting of the corresponding output pin when it is valid can be set according to the actual situation, not to limit the hair. Therefore, as long as the use of the GPIO pin and the selection pin of the multiplexer is ensured, the platform controller 210 is either connected to the first BIOS chip 250 or connected to the second BIOS chip 260, and the substrate management is performed. The controller 220 can be viewed as a one-or-one effect, either for the purpose of being connected to the second BIOS chip 260 or for the first BIOS chip 250.

It should be noted that the preferred embodiment is compared to the previous embodiment. The preferred embodiment implements the multiplexer through a single GPIO pin of the substrate management controller 220 (in conjunction with an inverter 270). Either or the other, the previous embodiment is that the respective GPIO pins of the platform controller 210 and the baseboard management controller 220 pass through the LPC communication link to achieve an effect of either or both.

In addition, it should be noted that CS0# in FIG. 2 represents the chip selection signal; MOSI represents the serial data input; MISO represents the serial data output; CLK represents the clock signal; VCC represents the voltage of the access voltage; GND represents the ground. ;S indicates the select pin; OE_N indicates the enable pin.

While the invention has been described above in terms of the preferred embodiments, the invention is not intended to limit the invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

110‧‧‧ platform controller

120‧‧‧Baseboard management controller

130‧‧‧First Multiplexer

131‧‧‧First set of output pins

132‧‧‧Second group of output pins

140‧‧‧Second multiplexer

141‧‧‧First set of output pins

142‧‧‧Second set of output pins

150‧‧‧First BIOS chip

160‧‧‧Second BIOS chip

Claims (18)

A server system includes: a first BIOS chip; a second BIOS chip; a platform controller electrically connected to a first multiplexer, wherein the first multiplexer is electrically connected to the first a BIOS chip and the second BIOS chip; and a substrate management controller electrically connected to the platform controller, the substrate management controller is electrically connected to a second multiplexer, the second multiplexer Electrically connecting to the first BIOS chip and the second BIOS chip, wherein the substrate management controller includes at least one third GPIO pin, and the at least one third GPIO pin is electrically connected to the first multi-channel The selector pin of the selector and the select pin of the second multiplexer. The server system of claim 1, wherein the server system automatically boots from another BIOS chip when the server system fails to boot from one of the first BIOS chip and the second BIOS chip. The server system of claim 2, wherein when the server system fails to boot from one of the first BIOS chip and the second BIOS chip, the BIOS system automatically starts from another BIOS chip. And the baseboard management controller simultaneously updates the firmware of the failed BIOS chip. The server system of claim 3, wherein the server system updates the firmware of the failed BIOS chip through the firmware of the BIOS chip included in the baseboard management controller. The server system of claim 1, wherein the server system receives an external update command to update the firmware of the first BIOS chip or the second BIOS chip. The server system of claim 1, wherein the first multiplexer and the second multiplexer each comprise a plurality of sets of output pins. The server system of claim 1, wherein the at least one third GPIO pin comprises a fourth GPIO pin; the fourth GPIO pin is electrically connected to the first plurality through an inverter A select pin of the path selector, and the fourth GPIO pin is electrically connected to the select pin of the second multiplexer. The server system of claim 1, wherein the at least one third GPIO pin comprises a fifth GPIO pin and a sixth GPIO pin; the fifth GPIO pin is electrically connected to the first A select selector pin of the multiplexer, and the sixth GPIO pin is electrically coupled to the select pin of the second multiplexer. The server system of claim 6, wherein the platform controller is connected to the first BIOS chip through the first set of output pins of the first multiplexer in a predetermined state, thereby transmitting The first BIOS chip activates the server system. The server system of claim 9, wherein the substrate management controller automatically sends a control command to the first multi-channel when the base management controller detects that the first BIOS chip fails to self-detect. a selector, the platform controller is coupled to the second BIOS chip via a second set of output pins of the first multiplexer, the substrate management controller transmitting a reset command to cause the second BIOS to perform Boot the automatic detection to start the server system. The server system as described in claim 10, wherein the substrate management control After the controller sends the control command to the first multiplexer, the baseboard management controller is connected to the first BIOS chip through the first set of output pins of the second multiplexer, and the baseboard management controller The firmware of the first BIOS chip is updated. The server system of claim 11, wherein when the substrate management controller sends the control command to the first multiplexer, the control command switches a high potential signal to a low potential signal. The server system of claim 11, wherein the command of the baseboard management controller is executed by using a remote communication mode or a local mode to update the firmware of the first BIOS chip. The server system of claim 1, wherein the platform controller is electrically connected to the baseboard management controller for communication of control messages. The server system of claim 14, wherein the platform controller includes at least one first GPIO pin, and the at least one first GPIO pin is electrically connected to the selection of the first multiplexer. And the substrate management controller includes at least one second GPIO pin electrically connected to the selection pin of the second multiplexer. The server system of claim 15, wherein the first multiplexer and the second multiplexer each comprise a plurality of sets of output pins, and the first multiplexer and the second plurality The selection signal of the path selector is internally determined to be a valid signal, and the first group of output pins of the plurality of sets of output pins are selected. The server system of claim 16, wherein the platform controller communicates with the first multiplexer via a first SPI signal and at least a first GPIO signal, and the substrate management controller transmits a first Two SPI signals and at least one second GPIO signal and the second multiple channel selection Communicate with the device. The server system of claim 17, wherein the platform controller selects to enable the selection signal of the first multiplexer through the first GPIO signal to transmit the first SPI signal to the first a BIOS chip or the second BIOS chip, the substrate management controller selects to enable the selection signal of the second multiplexer through the second GPIO signal to transmit the second SPI signal to the first BIOS chip or The second BIOS chip, and the platform controller selects to enable the selection message of the first multiplexer by using the first GPIO signal, the substrate management controller prohibits the selection of the second plurality by using the second GPIO signal The routing number of the road selector.