TWI523437B - Encoding and syndrome computing co-design circuit for bch code and method for deciding the same - Google Patents

Description

BCH code encoding and symptom calculation share the design circuit and determine the total Method of designing circuits

The present invention relates to a shared design circuit and a method for determining the same, and more particularly to a BCH code encoding and symptom calculation sharing design circuit and a method for determining the same.

The BoSe-Chaudhuri-Hocquenghem (BCH) code is a very common error correction code used in storage and communication equipment. The BCH code can detect and correct random errors due to noise and defects in the memory device channel. The encoding of the BCH code is often implemented by a combination of a linear feedback shift register and some logic integrated circuits. For the decoding of BCH codes, it is much more complicated than coding. Referring to Fig. 1, the decoding process can be explained as follows: After receiving a codeword (S01), the symptom code of the codeword is calculated according to a specific polynomial (S02). Then, according to the symptom code, an error position polynomial can be found (S03). Next, by calculating the root of the error position polynomial, an error position number can be obtained (S04). Finally, the error code word is corrected to obtain the correct signal data (S05).

The conventional linear feedback shift register circuit design is as shown in Fig. 2. Show. In order to speed up the operation, the circuit design is usually parallelized while calculating multiple input bit data. In the figure, p indicates that p-bit data in R'(j) of the j-th clock input can be simultaneously calculated, and after encoding, the result Z(j) is output. If the code length has n bits, the encoding process will be completed after [n/p] clocks.

In a decoder for a BCH code, there is also a similar iterative computational architecture, such as a symptom code calculation unit. For a symptom code calculation unit having t error correction capabilities, each symptom code S _i can be calculated by the following equation.

Where r(α ⁱ⁺¹ ) represents the received codeword polynomial. In order to implement the above equation, the general decoding circuit is processed using the symptom code calculation unit, and the common symptom code calculation unit is as shown in FIG. Similar to the aforementioned encoder, in the figure, p denotes the number of codeword bits received in each clock (p parallelization calculations), and g _i (j) is the intermediate generation data in the jth iteration calculation.

The above equations can be expressed in the form of a matrix, so the same sub-expression can be found in the process of derivation. In terms of circuit implementation, the same sub-expressions can be refined by appropriate shared hardware while achieving the goal of reducing hardware complexity. In addition, since the encoder of the BCH code is also operated by a similar iterative operation mode, if the codec is not simultaneously performed, the encoder and the symptom code calculation unit can share the register, which can further Save on area costs. Many of the previous cases have revealed similar designs, such as U.S. Patent Nos. 6,405,339, 7,743,311, 8,418,021, and the like. However, the hardware complexity of these patents is still too high, and there is still room for improvement in the pursuit of thinner, lighter and shorter electronic devices.

As described above, in the conventional scheme of the shared design circuit for encoding and character code calculation of the BCH code, the complexity of the hardware is high and the area cost is large. Therefore, a common design circuit suitable for the shared design circuit can reduce the complexity of the hardware, and it is better to effectively reduce the coding and syndrome calculation of the BCH code of the same sub-operation unit.

According to an aspect of the present invention, a common design circuit for BCH code encoding and symptom calculation can perform p parallel operations, including: a coding unit for transmitting a message having k bits through a first iteration Encoded into a BCH code codeword having n bits, the first iterative operation sequentially receives p bits in each clock, and outputs the BCH code codeword after [n/p] clock; a symptom code a calculating unit, configured to obtain a symptom code of 2t m bits after a second iterative operation by using a BCH code codeword having n bits, wherein the second iterative operation sequentially receives p bits in each clock. And outputting the symptom code after the [n/p] clock; a plurality of multiplexers, each multiplexer is configured to receive a first intermediate calculation result generated by the first iterative operation and the second iterative operation a second intermediate calculation result, when the first iterative operation is performed, outputting the first intermediate calculation result; when the second iteration operation is performed, outputting the second intermediate calculation result; and a plurality of temporary registers, each temporary The register is configured to receive the first intermediate calculation result from the corresponding multiplexer Or a second intermediate calculation result, or a second intermediate calculation result from the corresponding symptom code calculation unit, and outputting the first intermediate calculation result in a time after receiving the first intermediate calculation result or the second intermediate calculation result Go to the coding unit or the second intermediate calculation result to the symptom code calculation unit. Where k, n, p and t are positive integers and n is greater than k. m is the power of 2 in GF(2 ^m ).

According to the present concept, the first iterative operation obtains the computed value of Z(j) and the complete BCH codeword, where Z(j)=F ^p ×[ Z ( j -1)+ R' ( j )], where Z( 0) All elements are 0.

Z(j) is the first intermediate calculation result calculated by the jth iteration of the first iterative operation; the initial processing data of an n-bit having a k-bit message is cut in units of p bits, R'(j) Is the j-th divided p-bit; R=n-k+1; g' _R-1 , g' _R-2 ... g' ₀ is a generator polynomial g(x)=x ^R +g ' _{R -1} x ^R-1 +g ' _R-2 x ^R-2 +...+g ' ₂ x ² +g ' ₁ x ¹ +g ' ₀ coefficient.

According to the present concept, the first iterative operation satisfies a matrix F" operation, wherein , F ' = [F ^p 's first P column | F ^p ], m is a positive integer.

According to the concept of the present case, the second iterative operation obtains the calculated value of G(j) and the complete symptom code, wherein , where G(j)=[g ₁ (j)g ₃ (j)...g _2t-1 (j)], G(j) represents the j-th iteration calculation of the second iteration operation, m×t Second intermediate calculation result, R(j)=[ r ₀ (j) r ₁ (j)... r _{p -1} (j)], R(j) represents the symptom code calculation unit in the jth iterative calculation Receiving p bits of the codeword, S(j) represents the symptom code calculated value in the jth iteration calculation; matrix X _R is a p×mt binary matrix, and X _G is a mt×mt Binary matrix, X _S is a binary matrix of mt × 2mt.

According to the present concept, the matrices X _R , X _G and X _{G are} defined as follows: X _R = [C ₁ C ₃ ... C _2t-1 ], , α ₀ ... α _{m -1} are elements in GF(2 ^m ) , I is the identity matrix, B _w represents the operation matrix outside the zero matrix and the unit matrix, and w is a positive integer power of 2 but less than or equal to

According to the concept of the case, the number of multiplexers is larger than the coding unit. The R value of the BCH code that can be programmed, where R = n - k + 1. The number of registers is greater than or equal to m × t. The first intermediate calculation result and the second intermediate calculation result are 1-bit signals.

According to another aspect of the present invention, a method for determining a common design circuit for BCH code encoding and symptom calculation includes the steps of: establishing X _R , X _{G ,} and X _S according to the number of parallel calculations p and the number of symptom codes 2t; F ^P ; establish F '; establish F "; establish matrix [X _SRG F"]; and design a circuit that satisfies the matrix [X _SRG F"] operation, where k, n, p, and t are positive integers, n is greater than k, X _R =[C ₁ C ₃ ... C _2t-1 ], C _2t-1 = , α ₀ ... α _{m -1} are elements in GF(2 ^m ) , I is the identity matrix, B _w represents the operation matrix outside the zero matrix and the unit matrix, and w is a positive integer power of 2 but less than or equal to , F ' = [F ^p 's first P column | F ^p ], R=n-k+1,g' _R-1 ,g' _R-2 ...g' ₀ is a generator polynomial g(x)=x ^R +g ' _R-1 x ^R-1 +g ' _{R -2} x ^R-2 +...+g ' ₂ x ² +g ' ₁ x ¹ +g ' The coefficient of ₀ .

10‧‧‧Shared design circuit

100‧‧‧ coding unit

200‧‧‧ symptom code calculation unit

300‧‧‧Multiplexer

400‧‧‧ register

Figure 1 is a decoding flow of a conventional BCH code.

Figure 2 shows a conventional linear feedback shift register circuit design.

Figure 3 shows a conventional symptom code calculation unit.

Figure 4 is a diagram showing a common design circuit for BCH code encoding and symptom calculation in accordance with the present invention.

Figure 5 depicts the operation of the shared design circuit at the time of encoding.

Figure 6 depicts the operation of the shared design circuit during symptom code calculation.

Figure 7 is a diagram of the method of determining the shared design circuit.

The invention will be more specifically described by reference to the following examples.

First, let us further understand the encoding process of the BCH code. For a BCH code codeword with n bits, it contains a k-bit message. In the encoding process, the following generator polynomial is applied: g(x)=x ^R +g ' _R-1 x ^R-1 +g ' _R-2 x ^R-2 +...+g ' ₂ x ² +g ' ₁ x ¹ +g ' ₀ where R=n-k+1. When encoding with an encoder capable of performing p parallel operations at the same time, an n-bit initial processing data having the k-bit message is cut into R'(1), R'(2) in units of p-bits.. .R'(n/p) (R'(n/p) is not necessarily a p-bit), and is input to the encoder for calculation in each clock. In terms of a general formula, the operation value of the output in the jth clock (1≦j≦n/p) is: Z(j)=F ^p ×[ Z ( j -1)+ R' ( j ) It should be noted that all elements in Z(0) are 0. Here, in order to facilitate the calculation, R'(j) is the jth p-bit, and Z(j) contains R bits, which are represented by Z ₀ (j), Z ₁ (j)...Z _R-1 (j), respectively.

The expressions in the other formulas are further described as follows: Let F ' =[F ^p 's first P column|F ^p ], you can get the Z(j) transposed matrix: The circuit that satisfies this operation can achieve the coding operation in Figure 2.

Look back at the symptom code calculation. Yungjoo Lee et al., published in the IEEE International Journal in 2012, entitled "Small-area parallel syndrome calculation for strong BCH decoding," which discusses a solution for the symptom code calculation unit to find and delete the same sub-expression. According to the paper, a symptom code calculation unit having p symptom code parallel computing capabilities would require [n/p] clock completion symptom code calculations, which also contained 2t subunits to simultaneously generate 2t symptom codes. In the jth clock, the symptom code S(j) calculated by the symptom code calculation unit can be expressed by the following equation: In the above formula, S(j) is a 1×2mt binary matrix representing the calculated value of 2t symptom codes output in the jth iteration calculation. Each symptom code has a m-bit value and m is non-zero positive. An integer is the power of 2 in GF(2 ^m ). G(j) is a 1×mt binary matrix representing m×t temporary intermediate calculation results in the jth iteration calculation. G(j) can be expressed as follows: G(j)=[g ₁ (j)g ₃ (j)...g _2t-1 (j)]g ₁ (j), g ₃ (j)...g _{2t -1} (j) represents the odd-numbered temporary results from the iterative calculation, each of which is a 1 x m binary matrix containing m bits.

R(j) is a 1×p binary matrix, indicating that in the jth iterative calculation, the symptom code calculation unit receives the p bits r ₀ (j), r ₁ (j) of the codeword... r _{p -1} (j), expressed in a matrix such as: R(j) = [ r ₀ (j) r ₁ (j)... r _{p -1} (j)].

X _R is a binary matrix of p × mt with respect to the input codeword. X _R can be expressed as: X _R = [C ₁ C ₃ ... C _2t-1 ], and C _2t-1 can be expressed as: α ₀ ... α _{m -1} is an element in GF(2 ^m ).

X _G is a binary matrix of mt x mt representing a fixed multiplication operation in the method. X _G can be expressed as: Where A _(2t-1)p can be expressed as

X _S is a binary matrix of mt × 2 mt, which in turn contains a number of m × m unit matrix and m × m operation matrix. Xs can be represented by a matrix: I denotes an identity matrix, B _w is a general formula of the operation matrices B ₂ , B ₄ , etc., and w is a positive integer power of 2 but less than or equal to 2 t. Each B _w can be expressed as:

In the paper by Yungjoo Lee et al., it is obvious that According to the symptom code calculation unit implemented by the method, many identical sub-expressions have been reduced. At this time, if the BCH coding unit can be combined, there is an opportunity to reduce the area cost of the circuit design.

According to the above inference, , plus X _SRG can get Y = [X _SRG F"] _{(P + mt) × (3mt + Rt)} . Apply the circuit of matrix Y, with appropriate buffer and circuit switching, a BCH code encoding and symptom code calculation A shared design circuit can be implemented.

Therefore, the present invention proposes the above BCH code coding and symptom code meter. Calculate the shared design circuit. See Figure 4, which depicts a BCH code encoding and symptom code calculation sharing design circuit 10 architecture. The shared design circuit 10 includes a coding unit 100, a symptom code calculation unit 200, R multiplexers 300, and t×m registers 400. The shared design circuit 10 has the capability of performing p parallel operations simultaneously, and can be used to encode a message having a k-bit into a BCH code codeword having n bits, or to receive an n-bit message. The BCH code code word can be used to calculate the symptom code. The BCH code encoding and symptom code calculations do not conflict with each other under appropriate circuit switching.

The encoding unit 100 can perform the operation value of Z(j) and the complete BCH codeword Z, so that F" is satisfied. Therefore, in the jth clock (the jth iteration calculation), R'(j) p inputs r' ₀ (j), r' ₁ (j), r' ₂ (j)...r' _(p-1) (j) are sequentially input to the common design circuit 10. Through iterative calculation, at the After [n/p] operations, the complete BCH codeword Z (Z ₀ , Z ₁ ... Z _R-1 ) can be output by the shared design circuit 10. The multiplexer that shares the iterative operation is shared due to the coding operation and the symptom code. 300 and the register 400, when receiving the input signal, it is necessary to distinguish whether the operation is coding or symptom code calculation, and this work is performed by the multiplexer 300. See Figure 5. When R'(j) is input, the middle The calculation results Z ₀ (j), Z ₁ (j)...Z _R-1 (j) are each input into different multiplexers 300; and each multiplexer 300 selects only the signal output from the encoding unit 100 (middle) The result of the calculation is not selected from the signal of the symptom code calculation unit 200 (ie, the portion of the dotted arrow). The signals respectively output by the multiplexer 300 are input to a corresponding one of the registers 400. 400 in the j+1th clock, the signals 100 computes the input to the encoding unit.

The symptom code calculation unit 200 operates when symptom code calculation is performed. The symptom code calculation unit 200 can execute the operation value of G(j) and the complete symptom code S, so that X _SRG is satisfied. Therefore, in the jth clock (jth iteration calculation), p inputs r ₀ (j), r ₁ (j), r ₂ (j)...r _{(p-1) of} R ₍ j ₎ (j) is sequentially input to the shared design circuit 10. Through iterative calculation, after the [n/p]th operation, the complete symptom code S(S ₁₍₁₎ , S ₁₍₂₎ , ...S ₁₍₂₎ ... S _2t(m) ) can be The shared design circuit 10 outputs. The number or letter in the subscript of S in the subscript indicates the bit corresponding to the number or letter of a symptom code. For example, S _2t(m) is the mth bit of the symptom code S _2t . Since the coding operation and the symptom code calculate the multiplexer 300 and the temporary memory 400 which share the partial iteration operation, when the input signal is received, it is necessary to distinguish whether it is an operation code or a symptom code calculation, and this work is also performed by the multiplexer 300. See Figure 6. When R(j) is input, the intermediate calculation results g ₁₍₁₎ (j), g ₁₍₂₎ (j)...g _2t-1(m) (j) are respectively input into different multiplexers 300. And each multiplexer 300 selects only the signal output from the encoding unit 100 (intermediate calculation result), and does not select the signal from the symptom code calculation unit 200 (ie, the portion of the dotted arrow). The signals respectively output by the multiplexer 300 are input to a corresponding one of the registers 400. The buffers 400 are again input to the symptom code calculation unit 200 for calculation in the j+1th clock. Since the number of bits of one output is m × t, it is greater than R. Therefore, some output values can be directly output to the scratchpad 400 without going through the multiplexer 300. Therefore, the number of registers 400 must be at least m×t.

Please refer to Figure 4 again. There are a few things to note. First, the present invention can be applied to different BCH codes, that is, the code length n and the number of bits carrying the message k are variable, and the R value also varies. Also, since the number of multiplexers 300 is closely related to the R value, when designing the multiplexer 300, its number is preferably larger than the R value of the BCH code that can be programmed. The number of multiplexers 300 shown in Figs. 4 to 6 is only R, and the implementation is not limited thereto. In addition, the number of symptom code bits, 2tm, has no corresponding relationship with the code length n. FIG. 4 shows that 2tm is greater than n and is only exemplary, and 2tm may be smaller than n. Finally, Figure 4 shows that Z _R-1 (j) shares a multiplexer 300 with g ₃₍₂₎ (j), and R = m + 2 can be derived. However, this is only a situation of many combinations, and it is not static. The difference between R and m may be any number.

From the above description of the common design circuit for BCH code encoding and symptom calculation, the following method for determining the shared design circuit can be obtained: First, X _R , X _G and X _{S are} established according to the number of parallel calculations and the number of symptom codes. (Step S11). Then, F ^P (steps S2), F' (steps S13) and F" are sequentially established (step S14). Based on the above-established data, a matrix [X _SRG F" is established (step S15). Finally, a circuit that satisfies the matrix [X _SRG F"] operation is designed (step S16).

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Shared design circuit

100‧‧‧ coding unit

200‧‧‧ symptom code calculation unit

300‧‧‧Multiplexer

400‧‧‧ register

Claims (9)

A common design circuit for BCH code encoding and symptom calculation, which can perform p parallel operations, comprising: a coding unit for encoding a message having k bits into a n-bit after a first iterative operation The BCH code codeword, the first iterative operation sequentially receives the p-bit in each clock, and outputs the BCH code codeword after the [n/p] clock; a symptom code calculation unit for having n A BCH code code word of a bit bit obtains a symptom code of 2t m bits after a second iterative operation, and the second iterative operation sequentially receives p bits in each clock, and at [n/p] The symptom code is output after the pulse; a plurality of multiplexers, each multiplexer is configured to receive a first intermediate calculation result generated by the first iterative operation and a second intermediate calculation result generated by the second iterative operation, When the first iterative operation is performed, outputting the first intermediate calculation result; when the second iteration operation is performed, outputting the second intermediate calculation result; and a plurality of temporary registers, each of the temporary registers is configured to receive from the corresponding multiplexing The first intermediate calculation result or the second intermediate calculation result, or a second intermediate calculation result from the corresponding symptom code calculation unit, and in a time after receiving the first intermediate calculation result or the second intermediate calculation result, outputting the first intermediate calculation result to the coding unit or the second The intermediate calculation results to the symptom code calculation unit, where k, n, p, and t are positive integers, n is greater than k, and m is the power of 2 of GF(2 ^m ). The shared design circuit of claim 1, wherein the first iterative operation obtains an operation value of Z(j) and a complete BCH codeword, where Z(j)=F ^p ×[ Z ( j -1) + R' ( j )], all elements in Z(0) are 0, where Z(j) is the first intermediate calculation result calculated by the jth iteration of the first iterative operation; the initial processing data of an n-bit having a k-bit message is cut in units of p bits, and R'(j) is The jth divided p-bit; R=n-k+1; g' _R-1 , g' _R-2 ... g' ₀ is a generator polynomial g(x)=x ^R +g ' _{R- 1} x ^R-1 +g ' _R-2 x ^R-2 +...+g ' ₂ x ² +g ' ₁ x ¹ +g ' ₀ coefficient. A shared design circuit as described in claim 2, wherein the first iterative operation satisfies a matrix F" operation, wherein F ' = [F ^p 's first P column | F ^p ], m is a positive integer. The shared design circuit according to claim 1, wherein the second iterative operation obtains the calculated value of G(j) and the complete symptom code, wherein Where G(j)=[g ₁ (j)g ₃ (j)...g _2t-1 (j)], G(j) represents the j-th iteration calculation of the second iteration operation, m×t second Intermediate calculation result, R(j)=[ r ₀ (j) r ₁ (j)... r _{p -1} (j)], R(j) indicates that in the j-th iteration calculation, the symptom code calculation unit receives To the p bits of the codeword, S(j) represents the symptom code calculated value in the jth iteration calculation; the matrix X _R is a p×mt binary matrix, and X _G is a mt×mt binary The matrix, X _S is a binary matrix of mt × 2mt. A shared design circuit as described in claim 4, wherein the matrices X _R , X _G and X _{G are} defined as follows: X _R =[C ₁ C ₃ ... C _2t-1 ], , α ₀ ... α _{m -1} is an element in GF(2 ^m ), , I is the identity matrix, B _w represents the operation matrix outside the zero matrix and the unit matrix, and w is a positive integer power of 2 but less than or equal to 2t, A shared design circuit as described in claim 1, wherein the number of the multiplexers is greater than an R value of a BCH code that can be programmed by the coding unit, where R = n - k + 1. The shared design circuit according to claim 1, wherein the number of the registers is greater than or equal to m×t. The shared design circuit of claim 1, wherein the first intermediate calculation result and the second intermediate calculation result are 1-bit signals. A method for determining a common design circuit for BCH code encoding and symptom calculation, comprising the steps of: establishing X _R , X _G and X _S according to the number of parallel calculations p and the symptom code number 2t; establishing F ^P ; establishing F′; establishing F "Building a matrix [X _SRG F"]; and designing a circuit that satisfies the operation of the matrix [X _SRG F"], where k, n, p, and t are positive integers, n is greater than k, X _R = [C ₁ C ₃ ... C _2t-1 ], , α ₀ ... α _{m -1} is an element in GF(2 ^m ), , I is the identity matrix, B _w represents the operation matrix outside the zero matrix and the unit matrix, and w is a positive integer power of 2 but less than or equal to 2t, F ' =[F ^p 's first column|F ^p ], R=n-k+1,g' _R-1 ,g' _R-2 ...g' ₀ is a generator polynomial g(x)=x ^R +g ' _R-1 x ^R-1 +g ' _{R -2} x ^R-2 +...+g ' ₂ x ² +g ' ₁ x ¹ +g ' The coefficient of ₀ .