TWI514405B - Method, controller, and memory device for correcting data bit(s) of at least one cell of flash memory - Google Patents

Description

Method and control for correcting data bits of at least one storage unit of flash memory Device and memory device

The present invention relates to a data correction mechanism for a flash memory, and more particularly to a method, a controller and a memory device for correcting data bits of at least one storage unit of a flash memory.

In general, the flash memory controller of the prior art may be provided with an error correction code processing circuit for correcting the data bit of the code word data read by the flash memory by using the error correction code processing circuit. The correct code word data. When the error correction code processing circuit can process the maximum number of error bits (that is, the processing capability) is greater than the number of error bits actually occurring in one codeword data, it indicates that the error correction code processing circuit can effectively correct the code. The error bit of the word data can get the correct code word data content. However, the existing error correction code processing circuit is mainly used to correct the bit error caused by the data reading operation, if it is because of data writing or When the potential traction caused by other factors causes the storage voltage and the stored data bit to have a larger error amount, the existing error correction code processing circuit cannot effectively perform the bit error phenomenon caused by the situation. Corrected, so the correct information could not be obtained.

Therefore, one of the objects of the present invention is to provide a method, a controller and a memory device for correcting data bits of a storage unit of a flash memory to reduce the bit error rate and solve the above-mentioned problems encountered by the prior art.

According to an embodiment of the invention, a method of modifying data bits of at least one storage unit of a flash memory is disclosed. The method includes: determining a potential cause type corresponding to a storage potential of a first storage unit to generate a first determination result; and correcting the storage potential of the first storage unit according to the first determination result Data bit.

In addition, according to the above embodiments, a controller for correcting data bits of at least one storage unit of the flash memory is further disclosed. The controller includes an access unit and an error code correction unit, wherein the access unit is configured to read the data bit corresponding to the storage potential of the first storage unit, and the error code correction unit is coupled to the access unit and used to determine the A type of electrical cause corresponding to the storage potential of the storage unit is used to generate a first determination result, and the data bit corresponding to the storage potential of the first storage unit is corrected according to the first determination result.

Further, according to an embodiment of the present invention, a memory device is further disclosed. The memory device comprises a flash memory and a memory controller, the flash memory has a storage unit, the storage unit has a storage potential, the storage potential corresponds to a data bit, and the memory controller is coupled to the memory controller The flash memory is used to read the data bit corresponding to the storage potential of the storage unit, determine a potential cause type corresponding to the storage potential of the storage unit, to generate a judgment result, and correct the storage unit storage according to the judgment result. The data bit corresponding to the potential.

Furthermore, an embodiment of the present invention has the advantages of classifying the type of the potential cause of the current storage unit according to the data bit/storage state of the adjacent storage unit, and then correcting the data bit according to the judgment result of the classification to reach the bit element. The effect of the interchange effectively reduces the occurrence of error bits.

100‧‧‧ memory device

110‧‧‧ memory controller

112‧‧‧Microprocessor

112C‧‧‧ Code

112M‧‧‧Reading memory

114‧‧‧Control logic

118‧‧‧Interface logic

120‧‧‧Flash memory

130‧‧‧Error correction code unit

135‧‧‧access unit

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.

Figure 2 is a schematic diagram showing the operation flow of the control logic shown in Figure 1.

FIG. 3A is a schematic diagram showing an example of an ideal potential statistical distribution of a conventional storage unit having a fourth-order state.

Fig. 3B is a schematic diagram showing an example of the potential distribution of the potential shown in Fig. 3A.

Figure 3C is a schematic diagram showing partial overlap of statistical distributions of two actual potentials.

FIG. 4A is a schematic diagram of data bits of different storage units having different potential generations respectively determined by bit swapping operations by using different reference voltage levels TH1 and TH2 in the embodiment of the present invention.

Fig. 4B is a schematic diagram showing an example of the expanded potential statistical distribution shown in Fig. 4A after the bit swapping operation.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 of the present embodiment is specifically a portable memory device (eg, conforming to SD/MMC, CF, MS, XD standard memory card). The memory device 100 includes a flash memory 120 and a controller, which can be a memory memory controller 110 and is used to access the flash memory 120. According to the embodiment, the memory memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic. 118. The read-only memory system is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory 120. In addition, control logic 114 includes an Error Correcting Code (ECC) unit 130. The flash memory 120 includes a plurality of blocks, and the controller (for example, the memory memory controller 110 executing the program 112C through the microprocessor 112) copies and erases the flash memory 120. , combined data and other operations. The memory memory controller 110 executing the code 112C through the microprocessor 112 can perform various control operations using its own internal components, for example, using the control logic 114 to control the access operation of the flash memory 120 (especially Accessing at least one block or at least one data page, performing buffer processing required by buffer memory 116, and utilizing interface logic 118 to interface with a host device (Host Device) communication.

The memory controller 110 can receive a command from a host (not shown in FIG. 1) to access the flash memory 120. The data of the flash memory 120 corresponds to a plurality of word lines, each word line is connected to a plurality of floating gates of the transistor, and each floating gate corresponds to a basic storage cell (cell). When data is written to a storage unit, the charge is applied to the corresponding floating gate, and when the data is read from the storage unit, the charge is read by the corresponding floating gate to obtain the voltage value, and the obtained value is obtained. The voltage value determines the data bit. A storage unit itself can be a single-level cell (SLC) or a multiple-level cell (MLC). The single-stage storage unit has two states. A data bit is stored, and the multi-level storage unit has multiple (for example, four or eight) states to store two or three data bits respectively. In this embodiment, for convenience of explanation, the system has four storage states. The multi-level storage unit is illustrated as an example. However, this example is not a limitation of the present invention. A single-stage storage unit or other multi-level storage unit may also be used to implement the storage unit of the embodiment of the present invention. The control logic 114 further includes an access unit 135 for accessing the data bit (value) of the storage state corresponding to the storage potential of the storage unit from the flash memory 105, and then the error correction code. The unit 130 determines whether to re-interpret the data bit stored in the storage unit and the error correction operation of the subsequent code word according to the read data bit value.

In this embodiment, the data content of each codeword is composed of data bits stored in a plurality of storage units in the flash memory 120, and the error correction code unit 130 is configured to perform an error correction code operation first. To determine whether the read codeword data has an error, and to determine whether the wrong bit can be corrected, and when the error bit of the codeword can be effectively corrected, the error correction error unit 130 performs an error. The correct code operation will immediately correct the error bit and get the correct code word data content. Conversely, when the error bit of the code word cannot be effectively corrected, the error correction code unit 130 will not re-read immediately. Flash memory 120, but based on current storage unit At least one data bit adjacent to the storage unit performs re-interpretation of the data bit of the current storage unit, and the operation is to re-interpret the read part of the data bit and determine to perform bit flipping. Correcting the data bit that is prone to error, for example, swapping (or changing) the data bit corresponding to one or more storage potentials near a reference voltage level, for example, changing the bit '0' to Bit '1' or bit '1' is replaced by bit '0'. Since the data corresponding to the storage potential is changed by bit swapping, it can be regarded as micro-adjusting the flash memory 120 equivalently. The reference voltage level and the equivalent result obtained by re-reading the data bit according to the voltage level, wherein the reference voltage level is used to distinguish a storage state corresponding to the storage potential of the storage unit Which storage state is used to determine which data bit corresponds to, for example, in the second-order storage state, a voltage level can be used to determine that the storage potential of the storage unit corresponds to In addition to the state (state '0') or a data write state (state '1'). Therefore, by performing the bit swapping operation on the data bits of the partial storage unit, the effect of dynamically adjusting the voltage level for different storage units can be achieved equivalently, in other words, by correcting the data bit distribution of the part, the equivalent The effect of correcting the partial potential distribution can be achieved. In the fourth-order storage state, three different voltage levels are used to determine which storage state the storage potential of the storage unit corresponds to (state '0'~state'3 'One of the ', by performing the bit swapping operation on the data bits of some of the storage units, even if the three different voltage levels are not actually corrected or adjusted, the operation of the bit swapping equivalently has a fine adjustment. The three voltage levels or at least one of the voltage levels and the data bit result are re-performed by adjusting the voltage level. Therefore, the data bit swapping operation can reduce the bit error rate.

Specifically, the way in which the error correction code unit 130 re-determines the potential cause type corresponding to the potential of a storage unit is based on the storage state or the corresponding data bit of an adjacent storage unit (served as an adjacent storage unit) of the storage unit. The source determines the cause type of the storage potential of the storage unit, and classifies according to the storage state of the adjacent storage unit or the indication of the data bit. When the storage status indicates the erase status '0' or the data status '2', the error is The correction code unit 130 determines that it is the first Type (first genesis type), and when the storage state is indicated as erase state '1' or data state '3', error correction code unit 130 determines to be the second type (second cause type), wherein the first type is It means that the storage potential of the adjacent storage unit has a lower influence on the potential traction caused by the storage potential of the current storage unit, and the second type refers to the potential caused by the storage potential of the adjacent storage unit to the storage potential of the current storage unit. The traction effect is higher, that is, the effect of the potential offset indicated by the second type is higher than the potential offset indicated by the first type. In other words, when the error correction code unit 130 performs data re-interpretation on two different storage units, there may be different results. For example, the error correction code unit 130 re-determines the storage potential corresponding to the potential of the first storage unit. Determining the type of the storage potential of the first storage unit according to the storage state of the adjacent storage unit (serving as a first adjacent storage unit) or the corresponding data bit of the first storage unit, Sorting according to the storage state of the first adjacent storage unit or the indication of the data bit, for example, when the storage status of the first adjacent storage unit is indicated as the erase status '0' or the data status '2', the error correction code The unit 130 determines that the potential cause type of the first storage unit is the first type (first cause type); when the error correction code unit 130 re-determines the potential cause type corresponding to the potential of the second storage unit, according to the Determining the storage state of a neighboring storage unit (serving as a second adjacent storage unit) or the corresponding data bit of the second storage unit The type of the storage potential of the second storage unit is classified according to the storage state of the second adjacent storage unit or the indication of the data bit. For example, the storage status of the second adjacent storage unit is indicated as the erased state '1' or When the data state is '3', the error correction code unit 130 determines that the potential cause type of the data bit of the second storage unit is the second type (second genetic type). When determining the potential cause type of the data bit of the current storage unit, the error correction code unit 130 may determine the bit swapping of the data bit of the current storage unit according to the type, which will be described later. .

In order to facilitate the reader's understanding of the operation of the embodiment of the present invention, please refer to FIG. 2, which is a schematic diagram of the operation of the control logic 114 shown in FIG. If the same result can be achieved in general, it is not necessary to follow the sequence of steps in the process shown in Figure 2, The steps shown in FIG. 2 do not have to be performed continuously, that is, other steps may be inserted therein: Step 205: Start; Step 210: The access unit 135 reads the storage potential of a storage unit from the flash memory 120. a corresponding data bit and a data bit corresponding to the storage potential of the at least one adjacent storage unit; Step 215: The error correction code unit 130 determines the storage potential of the current storage unit according to the storage state or the data bit of the at least one adjacent storage unit Generating the type of the cause, and classifying the cause type accordingly, and generating a judgment result indicating whether the cause type is the first type or the second type; Step 220: the error correction code unit 130 according to the judgment result Determining the type of cause, determining to perform data bit correction operation on the data bit of the current storage unit, to correct the distribution of the data bit, to achieve bit swapping, and to reduce the effect of the bit error; and step 225: end.

As described above, in step 215, the error correction code unit 130 determines the cause type of the storage potential of the current storage unit according to the storage state or the data bit of at least one adjacent storage unit. In this embodiment, the error correction code is used. The unit 130 determines the genetic type of the storage potential of the current storage unit according to the data bit of a neighboring storage unit. The selection of the adjacent storage unit may be an adjacent storage unit directly below the current storage unit, or may be currently stored. One of the other seven adjacent storage units of the unit, in addition, the error correction code unit 130 may also determine the cause type of the storage potential of the current storage unit according to the storage state or data bit of the plurality of adjacent storage units; The embodiments are all variations of the embodiments of the invention and are within the scope of the invention.

In order to make the reader more able to understand the highlights of the spirit of the present invention, the following brief description The principles and related operations of the inventive spirit of the present invention are described. In a prior art flash memory storage unit, the storage potential of the storage unit is an analog signal. Therefore, different storage units of data bits having the same storage state may have a storage potential substantially due to the offset. Differently, although the storage potential may be different, as long as the storage level is still between the two reference voltage levels for distinguishing a storage state, the storage potentials corresponding to different voltage values may be correctly determined to be the same storage state. However, once the stored potential after the offset exceeds or falls below any of the above voltage levels, the original storage state/data bit will be misjudged as another different storage state/data bit, thus occurring. The bit is wrong, therefore, the storage potential corresponding to the same storage state/data bit is ideally allowed to be different between the two reference voltage levels. Statistically speaking, one flash memory includes multiple memories. Unit, if each storage unit has a fourth-order state, then for the fourth-order state, there will be four different potential statistical distributions (corresponding to each In four storage states / data bits).

Please refer to FIG. 3A. FIG. 3A is a schematic diagram showing an example of an ideal potential statistical distribution of a conventional storage unit having a fourth-order state. For convenience of explanation, the horizontal axis of Fig. 3A represents different storage potential values, the vertical axis represents the number of storage units, and D0~D3 represent storage state '0' to state '3' (representing different data bits). The potential statistical distribution shown in FIG. 3A shows that the potential value corresponding to the distribution center point corresponds to a larger number of storage units, and the number of storage units corresponding to the potential value away from the distribution center point is Less, it means that for the storage unit, the ideal potential has a higher probability of falling at the center point of the statistical distribution. However, this only shows one of the ideal example diagrams, which is not a limitation of the present invention. Yes, the D0~D3 series represent the ideal potential statistical distribution, and the potential statistical distribution does not overlap between the two. Therefore, the fourth-order potential statistical distribution can be distinguished by three different reference voltage levels T1~T3. Different storage states, it should be noted that, in fact, when the data of another storage unit is written/accessed, the storage potential of the current storage unit is written by the data of the other storage unit/ Traction taken to generate an offset potential so that the potential value corresponding to unduly increase, and therefore, a four-stage state of the storage unit The corresponding ideal potential statistical distribution will be offset. In addition, when the different data bits of the other storage unit are written/accessed, the traction potential of the current storage unit will be affected to some extent. Differently, therefore, for all the storage units of a flash memory, different degrees of potential traction will not only cause the offset of the different potential statistical distributions corresponding to the fourth-order different storage states, but also the statistical distribution. For the expansion effect, please refer to FIG. 3B. FIG. 3B is an example diagram of the potential statistical distribution shown in FIG. 3A. The statistical distribution D0′~D3′ indicated by the dotted line respectively indicates the potential distribution of the potential after the offset. The ideal statistical distributions D0~D3 and D0'~D3' form an actual expanded statistical distribution (such as the dotted line portion shown in Fig. 3B). Please refer to Figure 3C. Figure 3C is a schematic diagram showing partial overlap of the actual potential statistical distribution. As shown in Figure 3C, M0 represents the ideal two-potential statistical distribution, M1 represents the two-potential statistical distribution after the offset, and M2 represents The extended two-potential statistical distribution, as shown in the figure, the end of the extended two-potential statistical distribution partially overlaps at the intermediate position, so that if the storage potential of a storage unit falls in the middle part, it may belong to two different stores. The statistical distribution of the potential corresponding to the state, therefore, cannot be correctly determined in the storage state or data bit interpretation, and the result of the bit error is highly likely to occur.

In order to reduce the bit error rate, in the embodiment of the present invention, the memory controller 110 takes the storage unit of the fourth-order storage state (having two data bits) as an example in the data writing/accessing, and writes first. Entering the lowest bit LSB of the same word line, and then writing to the highest bit MSB of the word line, so that the storage unit is divided into two stages of voltage value increase when the data is written, for example, for the data of the state "3" When the data is written to the storage unit, the storage unit of the flash memory 120 first raises the voltage value of the corresponding floating gate to the potential range corresponding to the state “2”, and then raises to the state “3”. The corresponding potential range is to avoid directly increasing the voltage value of the floating gate to the potential range corresponding to the state '3' to generate a greater degree of potential traction effect. Further, the error correction code unit 130 as described above. The memory controller 110 uses the error correction code unit 130 to refer to the data bits of the adjacent storage unit, classifies the potential causes of the current storage unit, and classifies them into at least two types, respectively, with less impact ( Minimum) a first type and greater impact (or most The second type of large, after classification, according to different types, decide to perform different bit modification on the data bits of the current storage unit to achieve bit swapping, and reduce the bit error rate.

Please refer to FIG. 4A. FIG. 4A is a diagram showing different storage units having different potential generations by different reference voltage levels TH1 and TH2 by different bit correction operations in the embodiment of the present invention. The schematic diagram of the data bit, as shown in Fig. 4, assumes that the reference voltage level originally used to distinguish the two storage states is located in the TH shown in Fig. 4A, that is, when the statistical distribution of the two potentials respectively expands. The respective tail portions overlap each other. In this case, the general flash memory 120 uses the reference voltage level TH and operates with the error correction code in the controller to obtain the correct data bit. However, the control The number of bits that can be solved by the error correction code operation is limited. When the corresponding potential value of most of the data bits of a code word falls near the voltage level TH, it is highly probable that an error will be judged. The bit error rate is caused to be high. In order to solve this problem, the error correction code unit 130 in the memory controller 110 knows that the individual error correction code operation cannot obtain the correct data bit. The error correction code unit 130 performs the type determination of the potential cause. For example, when the error correction code unit 130 determines that the storage potential of the current storage unit is subjected to the storage state of the adjacent storage unit as the state '0' or the state '2' When affected, the error correction code unit 130 classifies the current storage unit into a first type, that is, a type that is affected to be smaller or smallest. Conversely, when the error correction code unit 130 determines that the storage potential of the current storage unit is When the storage state of the adjacent storage unit is affected by the state '1' or the state '3', the error correction code unit 130 classifies the storage unit into the second type, that is, the type that is affected by the largest or largest, and according to different Classification type, perform different bit modification to achieve bit swapping, equivalently achieve the effect of using the reference voltage level of different voltage values to distinguish the storage state of the current storage unit, as shown in Figure 4A, due to errors The correction code unit 130 can perform the classification of the expanded potential statistics by two different types, so that the originally expanded statistical distribution can be Divided into the part shown by the solid curve and the part shown by the dashed curve, where the part shown by the solid curve represents the first classification type that is affected less, and the part shown by the dotted curve represents the larger affected part. Second classification Type, for the first type shown by the solid curve, when a storage unit is classified into the first type, the error correction code unit 130 determines that the storage potential of the storage unit is subjected to less or less Improper lifting, in the actual potential distribution as shown in the solid curve section, if the voltage level TH1 is used as the reference voltage level to distinguish the storage state / data bit, the storage state of the storage unit can be correctly obtained / The data bit, and if the voltage level TH in the prior art is used as the reference voltage level, the data bit corresponding to the potential between TH1 and TH is misjudged. Therefore, when the error correction code unit 130 finds the current When the data cannot be correctly decoded, and the current storage unit is classified into the first type, it indicates that the storage potential of the current storage unit may fall between TH1 and TH, so that the data bit is misjudged. At this time, the error correction code unit 130 By performing data bit correction, the correct data bit can be obtained, and the bit error rate can be effectively reduced. For the data bit correction, for example, it is assumed that the left side of TH in FIG. 4A is It should be in the data bit '01', and the right side of TH corresponds to the data bit '10'. When the error correction code unit 130 finds that the current data cannot be correctly decoded and classifies the current storage unit into the first type, It indicates that the storage potential of the current storage unit may fall between TH1 and TH (the distribution indicated by the solid line), and the data bit is misjudged as '01'. At this time, the error correction unit 130 will be misjudged data bit' If 01' is changed to '10', the bit error can be reduced to achieve effective correction; the above examples of data bits '01' and '10' are for illustrative purposes only and are not limiting of the present invention. On the other hand, the storage state/data bit corresponding to the potential between TH1 and TH is corrected to another storage state/data bit, although the reference voltage is not actually adjusted for data rereading. Taking and interpreting, however, the same result can be obtained equivalently as to gradually down-regulate the voltage value from the voltage level TH to obtain the voltage level TH1 and use the voltage level TH1 to perform the re-reading of the data.

On the other hand, when the error correction code unit 130 finds that the current data cannot be correctly decoded and classifies the current storage unit into the second type, it indicates that the storage potential of the current storage unit may fall between TH and TH2, so that the data bit It is misjudged. At this time, the error correction code unit 130 performs data bit correction to obtain the correct data bit, effectively reducing the bit error rate, and Bit modification, for example, the left side of TH in Figure 4A corresponds to the data bit '01', and the right side of TH corresponds to the data bit '10'. When the error correction code unit 130 finds that the current data cannot be correctly Decoding, and classifying the current storage unit into the second type, indicates that the storage potential of the current storage unit may fall between TH and TH2 (distribution represented by a broken line), and the data bit is misjudged as '10'. When the error correction code unit 130 changes the misjudged data bit '10' to '01', the bit error can be reduced to achieve effective correction; the above data bits '01', '10' are just examples. The description is not intended to be a limitation of the invention. On the other hand, the storage state/data bit corresponding to the potential between TH and TH2 is corrected to another storage state/data bit, although the reference voltage is not actually adjusted for data rereading. Taking and interpreting, however, the same result can be obtained equivalently as to gradually fine-tune the voltage value from the voltage level TH to obtain the voltage level TH2 and use the voltage level TH2 to perform the re-reading of the data. It should be noted that in the above example, an incorrect data bit '01' is corrected to the correct data bit '10' and another wrong data bit '10' is corrected to the correct data bit ' 01' is the bit swapping operation referred to in the embodiment of the present invention.

For the bit swapping operation, an embodiment of the present invention provides: determining a potential cause type corresponding to a storage potential of a first storage unit to generate a first determination result, and correcting according to the first determination result The data bit corresponding to the storage potential of the first storage unit. In addition, the embodiment also provides: determining a potential cause type corresponding to a storage potential of a second storage unit to generate a second determination result, and correcting the second storage unit according to the second determination result. The data bit corresponding to the storage potential, wherein the original data bit of the first storage unit is equal to the modified data bit of the second storage unit, and the modified data bit of the first storage unit The data bit equal to the original data bit of the second storage unit and the operation unit for modifying the data bits of the first and second storage units respectively form the above-mentioned data bit swapping operation.

Please refer to FIG. 4B, and FIG. 4B is an expanded potential statistic score shown in FIG. 4A. The equivalent diagram of the cloth after the bit swapping operation, as shown in FIG. 4B, after the processing of the bit swapping, the error storage state/data bit corresponding to the potential between the upper and lower original TH1~TH can be Corrected to another correct storage state/data bit, as shown in the figure, the solid curve part of the equivalent upper part is re-drawn on the right side of TH, and the error corresponding to the potential between the original TH~TH2 The storage state/data bit can also be modified to another correct storage state/data bit. As shown, the dotted curve portion of the equivalent upper portion is redrawn on the left side of TH, thus reducing The central point of the overall potential statistical distribution and the number of nearby storage units, so that the number of storage units corresponding to the codeword data bits falling in the center point and its vicinity is less or almost zero, in other words, the code can be greatly reduced The error rate of word data bits. Therefore, in the preferred embodiment, when the existing error correction code operation cannot effectively correct the bit error of the codeword (representing the number of bit errors is too high), the error correction code unit 130 can perform the bit swapping operation described above. The number of error bits in the codeword is reduced. When the number of error data bits in the codeword is reduced, the error correction code unit 130 can effectively correct the bit error of the codeword, and obtain the correct codeword data content. Therefore, the probability of not being able to effectively correct the codeword bit error can be alleviated by the above-described bit swapping operation.

Furthermore, the spatial relationship between the storage unit and the adjacent storage unit in the above paragraph may be on the same word line in the flash memory 120, or may be on different word lines, in other words, if the two storage units are in position On the same word line, the adjacent storage unit will be located on the left and right sides of the storage unit currently reading data, and if the two storage units are located on different word lines, the adjacent storage unit can be located in the current data reading. The upper position or the lower position of the storage unit, that is, the adjacent storage unit can be located at the previous word line of the word line currently reading data or the next word line of the word line currently reading the data. If the adjacent storage unit is in the previous word line, the memory controller 110 may buffer the read data to facilitate the subsequent classification of the cause of the potential statistical distribution after the previous data reading by the access unit 135. In addition, if the adjacent storage unit is in the next word line, the memory controller 110 can use the access unit 135 to perform the next word line. Reading, after then based on the information of the next electrically subsequent word line The operation of the classification of the statistical distribution of bit statistics.

Moreover, in the above preferred embodiment, although the implementation of the storage unit having the fourth-order storage state is taken as an illustration, this is not a limitation of the present invention. In other embodiments, the storage unit having the second-order storage state may also be utilized. Or a storage unit having a storage state of eight or more orders is realized, in other words, the technical spirit of the present invention can be applied to any kind of storage unit. Furthermore, the technical spirit of the present invention is to classify the storage potential of one storage unit into different genetic types according to different degrees of potential traction effects (ie, the first type that is less affected and the second type that is affected more). After that, the data bits are interchanged or modified according to different genetic types, and equivalently, the same voltage level can be adjusted to adjust the same technical effect of the data bits, and in the preferred embodiment, The two-stage data writing (that is, the two-stage voltage boosting) is taken as an illustration, but this is not a limitation of the present invention. In other embodiments, the above operation can also be applied to a single stage of data writing (ie, only One stage voltage boost).

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧ memory device

110‧‧‧ memory controller

112‧‧‧Microprocessor

112C‧‧‧ Code

112M‧‧‧Reading memory

114‧‧‧Control logic

118‧‧‧Interface logic

120‧‧‧Flash memory

130‧‧‧Error correction code unit

135‧‧‧access unit

Claims (15)

A method for modifying a data bit of at least one storage unit of a flash memory, comprising: (a) determining a potential cause type corresponding to a storage potential of a first storage unit to generate a first Determining a result; and (b) correcting the data bit corresponding to the storage potential of the first storage unit according to the first determination result, wherein the potential cause type indicates that one of the other storage units stores a charge for the first The potential draw caused by the stored charge of the storage unit. The method of claim 1, wherein the step of generating the first determination result comprises: determining, according to a data bit of a first adjacent storage unit, the storage potential corresponding to the first storage unit This potential cause type. The method of claim 2, wherein the first storage unit has a fourth-order storage state, and the step of determining the potential cause type corresponding to the storage potential of the first storage unit comprises: when the data When the bit indicates a erase state '0' or a data state '2', it is determined that the potential cause type is a first type; and when the data bit indicates a data state '1' or a data state '3' And determining that the potential cause type is a second type; wherein a potential offset effect indicated by the second type is higher than a potential offset effect indicated by the first type. The method of claim 2, wherein the first storage unit and the first adjacent storage unit are located on different word lines, and the first adjacent storage unit is located in the first storage unit Below position. The method of claim 2, wherein the first storage unit and the first adjacent storage unit are located on different word lines, and the first adjacent storage unit is located above the first storage unit. The method of claim 1, further comprising: determining a potential cause type corresponding to a storage potential of a second storage unit to generate a second determination result; and according to the second determination result, Correcting the data bit corresponding to the storage potential of the second storage unit; wherein the original data bit of the first storage unit is equal to the modified data bit of the second storage unit, the first storage unit The modified data bit is equal to the original data bit of the second storage unit, and the operation system for modifying the data bits of the first and second storage units respectively forms a data bit swapping operation. The method of claim 1, comprising: performing an error correction code (ECC) operation, determining whether an error bit of a codeword can be corrected; and when the codeword is incorrect Steps (a) through (b) are performed when the bit cannot be effectively corrected. A controller for modifying a data bit of at least one storage unit of a flash memory, comprising: an access unit for reading a data bit corresponding to a storage potential of a first storage unit And an error code correction unit coupled to the access unit for determining the first storage unit Storing a potential cause type corresponding to the potential to generate a first determination result, and correcting the data bit corresponding to the storage potential of the first storage unit according to the first determination result, wherein the potential cause type indication One of the other storage units stores a potential draw caused by the stored charge of the first storage unit. The controller of claim 8, wherein the error code correction unit determines the potential cause type corresponding to the storage potential of the first storage unit according to a data bit of a first adjacent storage unit. . The controller of claim 9, wherein the first storage unit has a fourth-order storage state, and the error code is when the data bit indicates an erase state '0' or a data state '2' The correction unit determines that the potential cause type is a first type; and when the data bit indicates a data status '1' or a data status '3', the error code correction unit determines the potential cause type The second type; wherein a potential offset effect indicated by the second type is higher than a potential offset effect indicated by the first type. The controller of claim 9, wherein the first storage unit and the first adjacent storage unit are located on different word lines, and the first adjacent storage unit is located below the first storage unit. The controller of claim 9, wherein the first storage unit and the first adjacent storage unit are located on different word lines, and the first adjacent storage unit is located above the first storage unit. The controller of claim 8, wherein the error code correction unit is: determining a potential cause type corresponding to a storage potential of a second storage unit to generate a second judgment And determining, according to the second determination result, the data bit corresponding to the storage potential of the second storage unit; wherein the original data bit of the first storage unit is equal to the corrected of the second storage unit Data bit, the corrected data bit of the first storage unit is equal to the original data bit of the second storage unit, and the operating system for correcting the data bits of the first and second storage units respectively A data bit swap operation. The controller of claim 8, wherein the error code correction unit performs an error correction code operation to determine whether an error bit of a code word can be corrected; and when the error bit of the code word cannot be When the error correction unit is validated, the error code correction unit determines the potential cause type corresponding to the storage potential of the first storage unit to generate the first determination result, and corrects the first storage according to the first determination result. The data bit corresponding to the storage potential of the unit. A memory device comprising: a flash memory having a storage unit, the storage unit having a storage potential corresponding to a data bit; and a memory controller coupled to the flash a memory for reading the data bit corresponding to the storage potential of the storage unit, determining a potential cause type corresponding to the storage potential of the storage unit, to generate a determination result, and according to the determination result, Correcting the data bit corresponding to the storage potential of the storage unit, wherein the potential cause type indicates that one of the other storage units stores a potential pull caused by the stored charge of the storage unit.