TWI509995B - Injection-locked phase-locked loop circuitry, integrated circuit thereof, and method thereof - Google Patents

Description

Injection locking phase-locked loop circuit, integrated circuit thereof, and method thereof

The present invention relates to electronic circuits, and more particularly to self-timing correction injection lock phase-locked loops, integrated circuits, and methods thereof suitable for use in high speed circuits.

Injection locking technology is widely used in microwave and millimeter wave frequency bands. The basic principle is: when an injection clock is injected into an oscillator, and the frequency of the injection clock injection, or the integer multiplication of the injection clock, When the local oscillator signal frequency of the oscillator is close, and the power of the injection clock is large enough, the oscillator will be injected and locked. At this time, the output clock frequency of the oscillator will be synchronized by the injected clock frequency, so the output clock is output. The phase noise of the frequency will be further improved.

When the frequency of the injection clock and the local oscillation signal are very different, the effect of injecting the clock to synchronize the local oscillation signal is weakened or even invalid.

Based on the above object, the present invention discloses an injection lock phase-locked loop circuit including a lock-locked loop circuit and an analog delay phase-locked loop circuit. The locked phase-locked loop circuit receives a reference clock to generate an output clock, and divides the output clock to provide a feedback signal. The analog phase-locked loop circuit is coupled to the locked phase-locked loop circuit, and automatically generates an injection clock according to the reference clock and the feedback signal, wherein the injection clock is synchronized with the reference clock to complete high-speed injection locking. , thereby reducing the phase noise of the output clock shake. The locked phase-locked loop circuit couples the injection clock to the output clock to synchronize an output phase of the output clock to an injection phase of the injection clock and generate an updated output clock.

The invention further discloses an integrated circuit comprising a locked phase locked loop circuit and an analog delay phase locked loop circuit. The locked phase-locked loop circuit receives a reference clock to generate an output clock, and divides the output clock to provide a feedback signal. The analog phase-locked loop circuit is coupled to the locked phase-locked loop circuit, and automatically generates an injection clock according to the reference clock and the feedback signal, wherein the injection clock is synchronized with the reference clock to complete high-speed injection locking. , thereby reducing the phase noise and jitter of the output clock. The locked phase-locked loop circuit couples the injection clock to the output clock to synchronize an output phase of the output clock to an injection phase of the injection clock and generate an updated output clock.

The invention further discloses a clock generation method, which is suitable for injecting a lock-locked loop circuit, comprising: receiving a reference clock by a locked phase-locked loop circuit to generate an output clock; and the locked phase-locked loop a circuit that divides the output clock to provide a feedback signal; and an analog delay phase-locked loop circuit automatically generates an injection clock according to the reference clock and the feedback signal, wherein the injection clock and The reference clock synchronization; and the locked phase-locked loop circuit couples the injection clock to the output clock to synchronize an output phase of the output clock to an injection phase of the injection clock and generate a Update the output clock.

10‧‧‧ Clock Generator

12‧‧‧Injection lock-in phase-locked loop

14‧‧‧DSP/MCU

16‧‧‧Transmission analog front-end circuit

160‧‧‧DAC

164‧‧‧ filter

166‧‧‧PA

18‧‧‧Receive analog front-end circuit

180‧‧‧LNA

182‧‧‧ filter

186‧‧‧ADC

30‧‧‧PLL

300‧‧‧PD+(V/I) _PD

302‧‧‧FD+(V/I) _FD

304‧‧‧VCO

306‧‧‧Delephone

32‧‧‧ analog DLL

320‧‧‧PD

322‧‧‧VCDL

40‧‧‧Multiplier

S700, S702..., S706‧‧‧ steps

1 is a block diagram of a wireless communication system 1 to which a lock-lock phase loop is applied in accordance with an embodiment of the present invention.

Fig. 2 is a view showing the principle of injection locking phase-locked loop in the embodiment of the present invention.

Figure 3 is a block diagram of an injection lock phase locked loop 12 in accordance with an embodiment of the present invention.

Figure 4 is a block diagram of another injection lock phase locked loop 12 in accordance with an embodiment of the present invention.

Figure 5 is a block diagram of another injection lock phase locked loop 12 in accordance with an embodiment of the present invention.

Figure 6 is a diagram showing the operation of the injection lock phase locked loop 12 in the embodiment of the present invention.

Fig. 7 is a flow chart showing the clock generation method 7 in the embodiment of the present invention.

The various embodiments and examples set forth in the following disclosure are intended to illustrate various technical features disclosed herein, and the specific examples or arrangements described herein are used to simplify the invention. It is not intended to limit the invention. In addition, the same reference numerals and symbols may be used in the different embodiments or examples, and the repeated reference numerals and symbols are used to illustrate the disclosure of the present invention, and are not intended to represent different embodiments or The relationship between the examples.

1 is a block diagram of a wireless communication device 1 for injecting a lock-locked loop in accordance with an embodiment of the present invention, having a transceiver for transmitting high-frequency wireless data, including a clock generator 10, and an injection-locked phase-locked loop. (Phase-Locked Loop, hereinafter referred to as PLL) 12, digital signal processor or microcontroller (Digital Signal Processor/Micro Control Unit, hereinafter referred to as DSP/MCU) 14, The transmission analog front end circuit 16 and the receiving analog front end circuit 18 (Receiving Analog Front End).

The wireless communication device 1 can be a mobile phone, a tablet, a laptop, a handheld game console, a remote control device, a consumer electronic device, or other electronic device. The wireless communication device 1 can communicate with an external service network (not shown) to transmit and receive wireless signals S _tx and S _rx using different wireless frequencies.

The injection lock phase-locked loop 12 receives the reference clock CK _ref to generate an output clock CK _VCO1 , CK _{VCO2 is} distributed to the transmission analog front end circuit 16 and the receiving analog front end circuit 18 to respectively modulate the generated wireless signal S _tx and demodulate the variable Wireless signal S _rx . The reference clock CK _ref can be generated by an external crystal oscillation circuit. The injection lock phase locked loop 12 can be implemented with an integrated circuit or discrete circuit components. In some embodiments, the injection-locked phase-locked loop 12 can also be used to generate an output clock CK _VCO3 (not shown) for transmission to the DSP/MCU 14 or other digital circuitry (not shown) as a synchronization clock for the digital circuitry, Synchronize digital signals in digital circuits. In the case of a modulated/demodulated time-varying or synchronous clock, the jitter of the signal in the output clock causes signal interference, loss of transmitted data, and reduced circuit performance. The injection lock phase locked loop 12 therefore employs an injection locking technique to reduce or remove signal jitter in the output clock.

The injection locking phase-locked loop 12 includes a phase-locked loop and a delay-locked loop, wherein the phase-locked loop is a loop circuit including a Voltage Controlled Oscillator (VCO), and the delay-locked loop is included A loop circuit of a Voltage Controlled Delay Line (VCDL). The injection-locked phase-locked loop 12 first locks the correct frequency of the output clocks CK _VCO1 , CK _VCO2 using a phase-locked loop, and then automatically generates an injection clock CK _INJ synchronized with the reference clock CK _ref using an analog delay-locked loop, which will be injected. The pulse CK _{INJ is} coupled to the output clock CK _VCO1 , CK _VCO2 to synchronize the phase of the output clock CK _VCO1 , CK _{VCO2 to} the phase of the injection clock CK _INJ , thereby reducing or removing the original output clock CK _VCO1 , CK Signal jitter inside the _VCO2 . Figures 2 through 7 have a detailed description of the low jitter injection lock phase locked loop 12.

Figure 2 shows the phase noise of several clock signals injected into the lock-locked loop 12, where the vertical axis represents the signal frequency f and the vertical axis represents the phase noise S _Φ (ω). Figure 2 shows four curves, the dotted line S _free-running indicating the phase noise of the VCO output clock of the voltage controlled oscillator, the dotted line S _PLL indicating the phase noise of the phase-locked loop PLL output clock, indicating the delay lock phase The loop DLL injects the dotted line S _INJ of the phase noise of the clock, and the solid line S _IL-PLL indicating the phase noise of the injection clock phase-locked loop 12 output clock.

First, the dotted line S _free-running shows that the phase noise output by the free-running signal of the voltage controlled oscillator VCO increases as the frequency decreases.

Displaying a broken line S _PLL output clock of the phase-locked loop PLL phase noise will be suppressed, respectively, high-pass and low-pass transfer function, so S phase noise of the _PLL phase-locked loop PLL output representing the phase of a voltage controlled oscillator VCO _S free- _Running is low. When the phase noise S _{PLL is} at the offset center frequency of the loop bandwidth, the phase noise S _{PLL of the} output clock is mainly contributed by the voltage controlled oscillator VCO of the phase locked loop PLL and the phase frequency detector. Although the phase-locked loop PLL can suppress the noise of the voltage controlled oscillator VCO in the loop bandwidth, there are other components contributing noise in the vicinity of the in-band. In addition, when the frequency of the VCO is higher, the noise contributed by itself increases, although a wider loop bandwidth can be selected to suppress the phase noise of the voltage controlled oscillator, but the maximum loop bandwidth f _{The BW} is limited by the reference frequency of the reference clock CK _ref . In general, in order to stabilize the phase locked loop, the maximum loop bandwidth f _{BW is} at least less than one tenth of the reference frequency.

Next, please refer to the phase noise S _{INJ of the} delay phase-locked loop DLL injection clock, the phase noise S _{INJ is} lower than the phase noise S _{free-running of the} voltage controlled oscillator VCO and the phase noise S PLL of the phase _- locked loop _PLL . When the injection clock and the output clock of the phase-locked loop PLL are combined by the sub-harmonic injection-locked oscillator, an injection-locked phase-locked loop 12 phase noise S _IL-PLL is generated between the phase noises of the two. Therefore, the output phase noise of the phase locked loop PLL is improved. In the injection locking range f _L , the phase noise is the phase noise (S _INJ ) of the subharmonic signal plus 20log(n), where n is the ratio of the output frequency to the injected clock frequency, as in equation (1). Show:

Outside the lock range f _L , the operating mode is the output phase noise of the phase locked loop. Although the injection clock CK _INJ has a good phase noise curve S _INJ , the sub-harmonic injection-locked oscillator is usually designed in a high-quality resonance cavity, resulting in a narrow injection locking range, so it is susceptible to temperature variations. The free oscillation frequency is changed, causing the subharmonic injection lock oscillator to operate in an unlocked state. Therefore, the injection clock CK _INJ must be synchronized with the output clock CK _VCO , otherwise the injection lock phase-locked loop 12 will operate in an unstable state.

The injection-locked phase-locked loop 12 in the embodiment synchronizes the injection clock CK _INJ and the reference clock CK _ref such that the output phases of the two are coincident, and the injection clock CK _INJ is substantially synchronized with the output clock CK _VCO , thus injecting when the clock CK _INJ harmonic injection locked within the locking range of the oscillator, when the clock CK _iN and then injection injection locking voltage-controlled oscillator VCO to the output of the phase locked loop PLL _VCO pulse CK, to further improve the phase noise. The injection-locked phase-locked loop 12 achieves low phase noise and jitter improvement, and is easily implemented in the microwave and millimeter-wave bands. It is insensitive to process variations and is well suited for use in receivers that require low jitter.

3 is a block diagram of an injection-locked phase-locked loop 12 in accordance with an embodiment of the present invention, including a phase-locked loop PLL circuit 30 and an analog delay-locked loop DLL circuit 32.

The injection locking phase-locked loop 12 is a dual-loop phase-locked loop architecture. The phase-locked loop PLL circuit 30 first tracks the output clock CK _VCO to the correct output frequency, and then uses the analog delay phase-locked loop DLL circuit 32 to adjust the injection signal CK _INJ . The phase is made to coincide with the output phase of the reference clock CK _ref and the output clock CK _VCO , and the injection signal CK _{INJ is} injected into the voltage controlled oscillator 304 in the phase locked loop PLL circuit 30 to output an updated output clock CK _VCO In order to reduce or remove the signal jitter in the output clock CK _VCO .

The phase locked loop PLL circuit 30 includes a Phase Detector (PD) 300, a Frequency Detector (FD) 302, a filter including a resistor R2 and capacitors C1 and C2, a voltage controlled oscillator 304, and a frequency divider. 306. The phase detector 300 and the frequency detector 302, the filter, the voltage controlled oscillator 304, and the frequency divider 306 are sequentially coupled to form a loop.

The PLL circuit 30 receives and synchronizes the input reference signal CK _ref and the feedback signals CK _{DIV, I} and CK _{DIV, Q} . The feedback signals CK _{DIV, I} and CK _{DIV, Q} are the in-phase and quadrature signals generated by the output clock CK _VCO of the voltage controlled oscillator 304 after being divided by the frequency divider 306. The entire feedback mechanism changes the phase of the voltage-controlled oscillator 304 output clock CK _VCO by comparing the phase between the feedback signals CK _{DIV, I} and CK _{DIV, Q} and the reference signal CK _ref , and finally makes the loop lock. The reference signal CK _ref and the output clock CK _VCO maintain a fixed phase and multiplier relationship, wherein the frequency of the output clock CK _VCO is substantially equal to the frequency of the reference signal CK _ref after being divided by the frequency divider 306.

In practice, the phase detector 300 and the frequency detector 302 receive the input reference signal CK _ref and the feedback signals CK _{DIV, I} and CK _{DIV, Q} to detect the phase difference between the reference signal and the feedback signal, respectively. And the frequency difference, the detected phase difference and the frequency difference are converted into corresponding currents, and the current is converted into a voltage V _tune through the filter _{, and the PLL} filters out the noise and transmits it to the voltage controlled oscillator 304 for controlling the output. The frequency and phase of the clock CK _VCO . The voltage controlled oscillator 304 is a sub-harmonic injection locked oscillator that can be coupled to the injection clock CK _INJ and the output clock CK _VCO whose output clock CK _VCO frequency and phase can be controlled by the voltage V _{tune, PLL} . When the phase difference and the frequency difference between the reference signal and the feedback signal differ greatly, the voltage V _{tune, the PLL} changes accordingly, thereby changing the frequency and phase of the output clock CK _VCO . When the phase difference and the frequency difference between the reference signal and the feedback signal are substantially the same, the voltage V _{tune, the PLL} will remain substantially unchanged, and the frequency and phase of the output clock CK _VCO are locked to a stable state. When the reference signal CK _ref generates the output clock CK _VCO through the internal circuit of the PLL circuit 30, the internal circuit of the PLL circuit 30 including the phase detector 300, the phase detector 302, the filter and the voltage controlled oscillator 304 all contribute some Phase noise to the output clock CK _VCO , causing signal jitter.

The injection lock phase-locked loop 12 uses the analog delay phase-locked loop DLL circuit 32 as a self-timing correction loop to synchronize the injection clock CK _INJ with the reference clock CK _ref so that the output phases of the two are identical, and the injection clock CK _{IN is} coupled. Injecting into the voltage controlled oscillator VCO to lock the phase of the phase-locked loop PLL output clock CK _VCO further improves phase noise and reduces signal jitter on the output clock CK _VCO . The analog DLL circuit 32 includes a phase detector 320, a voltage controlled delay line 322, a frequency divider 306, and a capacitor C3. The phase detector 320, the capacitor C3, the voltage-controlled delay line 322, and the frequency divider 306 are sequentially coupled to form a loop.

The analog DLL circuit 32 receives the reference signal CK _ref and automatically locks the injection clock CK _INJ after a certain signal period. First, the phase detector 320 compares the phase difference between the reference signal CK _ref and the feedback signal (CK _{DIV, I} , CK _{DIV, Q} ) and converts the detected phase difference into a corresponding current through the filter. C3 converts the current to voltage V _{tune, DLL} and filters the noise and transmits it to voltage controlled delay line 322 for adjusting the delay to change the phase of the injection clock CK _INJ . The voltage controlled delay line 322 is controlled by an analog voltage and allows fast and immediate phase adjustment of the injection clock CK _INJ .

When the injection clock CK _{INJ is} locked, it is synchronized with the reference signal CK _ref . The reference clock CK _{ref is} relative to the output clock CK _VCO is a signal with relatively stable frequency, lower phase noise and smaller signal jitter, so the injection clock CK _INJ synchronized with the reference signal CK _ref also has less phase Noise and signal jitter. When the injection clock CK _{INJ is} injected into the output clock CK _VCO , the voltage controlled oscillator 304 couples the injection clock CK _INJ and the output clock CK _VCO . When the injection clock CK _INJ and the output clock CK _VCO are close in frequency and the power of the injection clock CK _INJ is strong enough, the output phase of the output clock CK _VCO is substantially synchronized or phase-aligned with the injection phase of the injection clock CK _INJ and An updated output clock CK _{VCO is} generated, which in turn reduces or removes the phase noise or signal jitter of the output clock CK _VCO . The updated output clock CK _VCO can be supplied to receivers or clock applications that require low jitter.

In addition, because the analog DLL circuit 32 compares the reference signal CK _ref with the feedback signal (CK _{DIV, I} , CK _{DIV, Q} ) and the feedback signal (CK _{DIV, I} , CK _{DIV, Q} ) is the output clock CK _VCO frequency division. After N times the signal, so the injection clock CK _INJ and the output clock CK _VCO will clear the jitter and update once at the 1/N times output clock CK _VCO frequency. In some embodiments, the injection-locked phase-locked loop 12 can be placed more frequently between the voltage-controlled delay line 322 and the voltage-controlled oscillator 304 by a frequency greater than 1/N times the output clock CK _VCO frequency. The frequency clears the jitter as shown in Figure 4. Compared with FIG. 3, the voltage-controlled delay line 322 of the injection-locked phase-locked loop 12 shown in FIG. 4 and the voltage-controlled oscillator 304 have an additional frequency multiplier 40 which can generate an injection clock into the analog DLL circuit 32. The CK _{INJ is} multiplied and coupled to the voltage controlled oscillator 304. The frequency multiplier 40 is an N multiplier, and the generated injection clock CK _INJ is the same frequency as the output clock CK _VCO . Therefore, the voltage controlled oscillator 304 will clear the jitter and phase noise at each output clock to generate a high frequency and low jitter update output clock CK _VCO .

The injection-locked phase-locked loop 12 of FIGS. 3 and 4 automatically synchronizes the injection clock CK _INJ with the reference signal CK _ref by the analog DLL circuit 32, and then injects the injection clock CK _INJ into the output clock CK _VCO to obtain a low phase miscellaneous Signal and low jitter output clock CK _VCO .

5 is a block diagram of another injection locking phase-locked loop 12 in the embodiment of the present invention, wherein the reference clock CK _{ref has} a frequency of 2.5 GHz, and the output clock CK _{VCO has} a frequency of 10 GHz, and the frequency divider 306 The multiple is 4.

The frequency divider 306 divides the frequency of the output clock CK _VCO by 4 to generate a 2.5 GHz feedback signal (CK _{DIV, I} , CK _{DIV, Q} ). As described in the preceding paragraph, the analog DLL circuit 32 compares the reference signal CK _ref and the feedback signal (CK _{DIV, I} , CK _{DIV, Q} ) with a phase difference of 2.5 GHz, and adjusts the injection clock CK according to the phase difference. _INJ synchronizes the injection clock CK _INJ with the reference signal CK _ref . The injection clock CK _INJ is injected into the output clock CK _VCO at a frequency of 2.5 GHz to cause phase synchronization between the two, thereby reducing phase noise and signal jitter. Please refer to FIG. 6 together. FIG. 6 shows the operation mode of the injection locking phase-locked loop 12 of FIG. Initially the PLL circuit 30 first tracks the correct output frequency of 10 GHz, however, due to the internal circuitry of the PLL circuit 30, the output clock CK _VCO will have signal jitter. The voltage V _tune of the upper half of Fig. 6 _, the initial fluctuation of the _PLL shows that the PLL circuit 30 is tracking the correct output frequency after the injection lock phase-locked loop 12 is turned on, and the latter stable control voltage shows that the PLL circuit 30 locks the correct output frequency. Then, the analog DLL circuit 32 will automatically compare the phase of the reference signal CK _ref and the feedback signal (CK _{DIV, I} , CK _{DIV, Q} ), so that the injection clock CK _{INJ is} synchronized with the reference signal CK _ref , so that the entire self timing injection is locked. The output phase noise of the phase locked loop 12 can be further improved. The initial control voltage of the voltage V _{tune, DLL} shows that the analog PLL circuit 32 tracks the correct reference phase after the injection lock phase-locked loop 12 is turned on, while the latter stable control voltage shows that the analog PLL circuit 323 locks the correct reference phase. The lower half of Fig. 6 shows the process of synchronizing the injection clock CK _INJ with the reference signal CK _ref and the phase synchronization of the injection clock CK _INJ injection output clock CK _VCO phase. Note that the injection clock CK _INJ corresponds to the voltage V _tune of the upper half _{, the DLL} and the output clock CK _VCO correspond to the voltage V _tune of the upper half _{, and the PLL} changes. When the voltage V _{tune, the DLL is} stable, the injection clock CK _INJ is synchronized with the reference signal CK _ref . When the voltage V _{tune, the PLL is} stable, the output clock CK _VCO is synchronized with the reference signal CK _{ref and} synchronized with the phase of the injection clock CK _INJ .

The self-timing correction technique of the embodiment can increase the operating frequency of the injection phase-locked loop to the microwave and millimeter wave bands.

Figure 7 is a diagram showing the flow of the clock generation method 7 in the embodiment of the present invention. The diagram is applicable to the lock phase-locked loop 12 of FIG.

After the system 1 is turned on, the lock phase-locked loop 12 is initialized. First, the PLL circuit 30 receives the reference signal CK _ref to track the correct frequency to generate the output clock CK _VCO (S700). In the PLL circuit 30, the frequency dividing circuit 306 divides the output clock CK _VCO to provide the feedback signal CK _DIV (S702). The analog DLL circuit 32 then automatically generates an injection clock CK _INJ based on the reference signal CK _ref and the feedback signal CK _DIV , wherein the injection clock CK _{INJ is} synchronized with the reference signal CK _ref (S704). Finally, the analog DLL circuit 32 injects the injection clock CK _INJ into the PLL circuit 30, causing the voltage controlled oscillator 304 to couple the injection clock CK _INJ to the output clock CK _VCO to inject the output phase of the output clock CK _VCO with the injection. The injection phase of the clock CK _INJ is synchronized and produces an updated output clock CK _VCO (S706). In some embodiments, the analog DLL circuit 32 additionally includes a frequency multiplier that can multiply the analog DLL circuit 32 to generate an injection clock CK _INJ and couple it to the voltage controlled oscillator 304 such that the voltage controlled oscillator 304 can CK _VCO output clock pulse CK _VCO output when the same speed synchronization.

Those skilled in the art will appreciate that information and signals can be represented using a variety of different techniques. For example, the materials, instructions, information, signals, bits, symbols, and wafers described in the specification can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination of the above.

Those skilled in the art will appreciate that the various logical blocks, modules, processors, actuators, circuits, and algorithm steps described in the specification can be implemented by circuit hardware (eg, digitally implemented hardware, analog hardware, or both). Combination of the following, which can be designed and implemented by source code or other related technologies), using various forms of code or design code of instructions (also referred to herein as software or software modules), or a combination of the two. achieve. In order to clearly show the above software The various illustrated elements, blocks, modules, circuits, and steps described in the specification are generally described in terms of their function. The implementation of these features in software or hardware will be related to the specific application and design constraints of the complete system. The described functionality may be implemented in a variety of ways for each particular application, but the implementation is not deviated from the spirit and scope of the invention.

In addition, the various logic blocks, modules, and circuits described herein can be implemented using integrated circuits (ICs) or by an access terminal or access point. The integrated circuit may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), or the like. Programmable logic elements, discrete logic circuits or transistor logic gates, discrete hardware components, electrical components, optical components, mechanical components, or any combination of functions for performing the operations described herein can be performed A code or program instruction in the integrated circuit, external, or both. A general purpose processor may be a microprocessor, or the processor may be any commercially available processor, controller, microprocessor, or state machine. The processor may also be implemented by a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors, and a DSP core, or other various arrangements.

It will be understood by those skilled in the art that the specific sequence or sequence of steps of the present disclosure is merely exemplary. The specific order or sequence of steps of the program disclosed herein may be re-arranged in other orders, as may be apparent to those skilled in the art. The sequence of steps accompanying the method and requirements of the embodiments of the present invention are merely examples, and are not limited to the present invention. A specific sequence or sequence of steps of the procedure is disclosed.

The method or algorithm step can be implemented by a hardware or a processor, or a combination of the two. Software modules (including executable instructions and related materials) and other data can be stored in the data memory, such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, temporary storage A storage medium (such as a computer readable) that can be read by a device, hard drive, floppy disk, CD, or any other machine. The data storage medium can be coupled to a machine, such as a computer or processor (which can be referred to as a "processor"), which can read and write code from the storage medium. The data storage medium can be integrated into the processor. The processor and storage media can be hosted within the ASIC. The ASIC can reside in the user equipment. Alternatively, the processor and the storage medium may reside within the user equipment in the form of discrete components. In addition, suitable computer program products may include computer readable media, including code disclosed with respect to one or more disclosures. In some embodiments, a suitable computer program product can include packaging materials.

The present invention has been described above by way of a preferred embodiment, and is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

30‧‧‧PLL

300‧‧‧PD+(V/I) _PD

302‧‧‧FD+(V/I) _FD

304‧‧‧VCO

306‧‧‧Delephone

32‧‧‧ analog DLL

320‧‧‧PD

322‧‧‧VCDL

Claims (9)

An injection locking phase-locked loop circuit includes: a locked phase-locked loop circuit that receives a reference clock to generate an output clock, and divides the output clock to provide a feedback signal; and an analog delay phase lock a loop circuit coupled to the lock-lock loop circuit, automatically generating an injection clock according to the reference clock and the feedback signal, wherein the injection clock is synchronized with the reference clock to complete high-speed injection locking, thereby reducing the Outputting phase noise and jitter of the clock; wherein the locked phase-locked loop circuit couples the injection clock to the output clock to synchronize an output phase of the output clock to an injection phase of the injection clock and generate An update output clock. The injection locking phase-locked loop circuit of claim 1, wherein the analog delay phase-locked loop circuit comprises: a phase detecting circuit for detecting a phase difference between the reference clock and the feedback signal And a voltage-controlled delay line circuit that adjusts a delay value according to the phase difference to generate the injection clock. The injection locking phase-locked loop circuit of claim 2, wherein the analog delay phase-locked loop circuit further comprises a frequency multiplying circuit that multiplies the injection clock; and the locked phase-locked loop circuit The multiplied injection clock is coupled to the output clock to output the updated output clock. An integrated circuit comprising: a lock-lock loop circuit, receiving a reference clock to generate an output clock, and dividing the output clock to provide a feedback signal; and an analog delay phase-locked loop circuit coupled to the lock-lock loop The circuit automatically generates an injection clock according to the reference clock and the feedback signal, wherein the injection clock is synchronized with the reference clock to complete high-speed injection locking, thereby reducing phase noise and jitter of the output clock; The locked phase-locked loop circuit couples the injection clock to the output clock to synchronize an output phase of the output clock to an injection phase of the injection clock and generate an updated output clock. The integrated circuit of claim 4, wherein the analog delay phase-locked loop circuit comprises: a phase detecting circuit for detecting a phase difference between the reference clock and the feedback signal; A class of voltage controlled delay line circuits that adjust a delay value according to the phase difference to generate the injection clock. The integrated circuit of claim 5, wherein the analog phase-locked loop circuit further comprises a frequency multiplying circuit that multiplies the injection clock; and the locked phase-locked loop circuit multiplies the frequency The injection clock is coupled to the output clock to output the updated output clock. A clock generation method, suitable for injecting a lock-locked loop circuit, comprising: receiving a reference clock by an lock-lock loop circuit to generate an output clock; The output clock is divided by the lock phase-locked loop circuit to provide a feedback signal; an analog delay phase-locked loop circuit automatically generates an injection clock according to the reference clock and the feedback signal. The injection clock is synchronized with the reference clock; and the injection clock is coupled to the output clock by the locked phase-lock loop circuit to output an output phase of the output clock to the injection clock An injection phase is synchronized and an updated output clock is generated. The clock generation method of claim 7, wherein the step of automatically generating the injection clock by the analog delay phase-locked loop circuit comprises: detecting the reference clock by a phase detection circuit And a phase difference value between the feedback signal; and an analog voltage-controlled delay line circuit, wherein the delay value is adjusted according to the phase difference value to generate the injection clock. The clock generation method of claim 8, wherein the step of automatically generating the injection clock by the analog delay phase-locked loop circuit comprises: multiplying the injection clock by a frequency doubling circuit And the step of coupling the injection clock to the output clock by the locked phase-locked loop circuit includes: coupling the multiplied injection clock to the output clock to output the updated output clock.