TWI509757B - Mems chip and package method thereof - Google Patents

Description

MEMS wafer and packaging method thereof

The invention relates to a Micro-Electro-Mechanical System (MEMS) wafer and a packaging method thereof.

In MEMS wafer processing, internal MEMS components, such as microsonic pressure sensors, gyroscopes, accelerometers, etc., often need to be packaged in a closed space to maintain their stability. In the prior art, the encapsulation process is performed after the etching of the MEMS element is completed, and a device wafer containing a microelectromechanical element is bonded to another capping wafer by a bonding material such as aluminum or vitreous. However, since the MEMS components are packaged first, the MEMS components integrated with the CMOS process during the packaging process cannot withstand high temperatures due to aluminum or other materials, thus limiting the manner of packaging and MEMS components integrated with the CMOS process. It is also easier to damage during the packaging process.

The invention provides a MEMS wafer structure and a packaging method thereof to reduce the influence of temperature and improve the yield of the MEMS component.

A first object of the present invention is to provide a method for packaging a microelectromechanical system wafer, which solves the aforementioned problems by first completing the bonding and then etching the internal MEMS device.

A first object of the present invention is to provide a micro package packaged in the above manner Electromechanical system wafers.

To achieve the above and other objects, in one aspect, the present invention provides a MEMS wafer package method comprising the steps of: forming a cap wafer, the steps comprising: providing a first substrate; and the first substrate Forming an etch stop layer thereon; fabricating the component wafer, the method comprising: providing a second substrate; and forming a MEMS element and a material layer surrounding the MEMS element on the second substrate; bonding the cover wafer to the component wafer; After the bonding wafer is bonded to the component wafer, the first substrate is etched to form at least one channel; and the etch stop layer is etched by the via formed by the first substrate; and the material layer is etched.

After the above steps are completed, it is preferred to deposit a sealing layer on the first substrate.

In the above method, the etch stop layer and the material layer are preferably the same material or have similar etch rates for an etchant. The etch stop layer only needs to be able to shield the channels formed on the first substrate, and the pattern does not have to be very precise.

The manner in which the overlay wafer is bonded to the component wafer can be airtight or non-hermetic. The gas-tight manner is, for example, glass sintering or welding, and the latter can be, for example, a metal or an alloy as a bonding material. When using a metal or alloy, an insulating layer should be formed on the component wafer. If it is not airtight, it can use photosensitive poly The compound acts as a bonding material. Depending on the material of the bonding material, the pattern of the bonding material can be defined using lithography or lithography plus etching.

In another aspect, the present invention provides a MEMS wafer comprising: a first wafer layer comprising: a sealing layer; and a substrate under the sealing layer, the substrate having a sealed cavity a second wafer layer comprising: a substrate; and a MEMS element over the substrate; and a bonding layer bonding the first wafer layer to the second wafer layer.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The illustrations in the present invention are intended to illustrate the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

One of the features of the present invention is that a wafer containing a MEMS element (hereinafter referred to as "element wafer") is bonded to a cover wafer, and after bonding is completed, the internal MEMS device is etched. Since the MEMS component has not been etched during the packaging process (still bonding to the component wafer and cannot move), it is more resistant to high temperatures and less susceptible to damage.

According to the present invention, there are various ways of fabricating and bonding the cover wafer and the component wafer. First, a first embodiment of a method for fabricating a wafer is described. As shown in FIGS. 1 to 3, a first substrate 11 such as a germanium substrate is first provided, and an etch stop layer 12 is deposited on the substrate 11, and an etch stop layer is deposited. The material selection considerations of 12 indicate that since the etch stop layer 12 is disposed to withstand the etching of the substrate 11, when the material of the substrate 11 is germanium, the etch stop layer 12 must have a higher etching selectivity for germanium. Etch selectivity, and when the material of the substrate 11 is other materials, the etch stop layer 12 must have a higher etching selectivity ratio for the material. The pattern of the etch stop layer 12 is then defined, for example, by an inductive coupling plasma (ICP) etch. The first bonding layer 13 is then formed on the cover wafer and the pattern of the first bonding layer 13 is defined. In one embodiment, the first bonding layer 13 is made of a material that can be defined by an optical lithography, such as a photosensitive polymer such as parylene or polydimethyl siloxane. PDMS), photo-imgable resin, and the like. In this embodiment, it is only necessary to perform an exposure and development step on the photosensitive resin according to a desired pattern, and then to clean away the portion which is not intended to be retained. In another embodiment, the first bonding layer 13 uses a glass frit or solder material, and in this embodiment the pattern must be defined in other ways, such as lithography and etching. When the first bonding layer 13 is made of a solder material, its material selection will be described later.

When the first bonding layer 13 is not selected from materials which can be defined by optical lithography, it is not necessary to form the etch stop layer 12 and the first bonding layer 13 in order, either in the order of FIGS. 1 to 3 or as Figure 4~6 shows The first bonding layer 13 is formed first to form the etch stop layer 12.

The component wafer is fabricated in the manner of FIGS. 7-8, first providing a second substrate 21, such as germanium, and forming a MEMS element 24 and a material layer 22 surrounding the MEMS element on the second substrate 21. MEMS element 24 can be any shape and any number of layers, the illustrations being merely illustrative. The material of the material layer 22 may be, for example, any material used in the current CMOS process to provide insulation between the metal layers, which may be the same as or different from the etch stop layer 12, but preferably the same. In one preferred embodiment, the material of the etch stop layer 12 and the material layer 22 is the same as an oxide, such as hafnium oxide. A bond pad 26 for external connection is also formed at or after the formation of the MEMS element 24 and the material layer 22. After the above steps are completed, a second bonding layer 23 corresponding to the first bonding layer 13 is formed, and the material selection is described later.

Referring to FIGS. 9-13, after the overlay wafer and the component wafer (both can be fabricated in parallel) are completed, the first bonding layer 13 and the second bonding layer 23 are used to bond the two. The first bonding layer 13 and the second bonding layer 23 have various possible matching manners. For example, the first bonding layer 13 may be the above-mentioned photosensitive polymer such as parylene or polydimethyl siloxane. (PDMS), photo-imgable resin, or the like, and the second bonding layer 23 may be the same material or epoxy as the first bonding layer 13. This is a non-hero-sealed package. Alternatively, the first bonding layer 13 and the second bonding layer 23 may be bonded by means of glass sintering, and in this case, a hermetic package is formed.

After the cover wafer is bonded to the component wafer, in a preferred embodiment, the first substrate 11 or the second substrate 21 or both are preferably ground. The thickness is reduced by, for example, the thickness of the first substrate 11 is between 100 μm and 200 μm. The first substrate 11 is then etched by, for example, ICP etching to form at least one channel as shown in FIG. 11; the effect of the etch stop layer 12 can be seen at this time, and the pattern of the etch stop layer 12 only needs to correspond to the channel. The location is fine and does not need to be very precise. Next, the etch stop layer 12 and the material layer 22 are etched away by the via formed by the first substrate 11 as shown in FIG. At this time, it can be understood that the materials of the etch stop layer 12 and the material layer 22 are preferably the same, but the two may be different. In the latter case, an etchant needs to be replaced. If both the etch stop layer 12 and the material layer 22 are oxides, the etching may be performed, for example, by hydrogen fluoride (HF) vapor etching. When the material layer 22 is etched, the MEMS element 24 is released into a movable element. Finally, it is preferable to seal the channel on the first substrate 11 with the sealing layer 31 on the first substrate 11. The material of the sealing layer 31 may be any material capable of achieving a sealing function, including but not limited to metal, as shown in FIG. The wafer of Figure 13 can be subsequently cut to produce a wafer. (There are multiple wafers on the same wafer, only one of which is shown in Figures 1-21 of the present invention.)

14 to 18 illustrate another embodiment of the present invention. In this embodiment, the bonding wafer and the component wafer are bonded by soldering. Therefore, the material of the bonding layer 23 is a metal or an alloy, and the first bonding layer 13 is combined with the second bonding layer. The material of the layer 23 can be, for example, various metals suitable for welding or aluminum-bismuth alloys, sheet metal alloys, tin-silver alloys, gold-bismuth alloys, gold-tin alloys, lead-tin alloys, and the like. In this case, as shown in FIG. 15, after the connection pads 26 are provided on the second substrate 21, the insulating layer 25 is preferably deposited thereon to prevent the connection pads 26 from being electrically connected to the second bonding layer 23 to cause a short circuit. The material of the insulating layer 25 is preferably the same as the etch stop layer 12 and The material layer 22 is different and may include, for example, tantalum carbide (SiC) or amorphous silicon. After FIG. 15 , the cover wafer is soldered to the component wafer as shown in FIGS. 16 to 18 , and then the substrate is polished, the first substrate 11 is etched to form a channel, the etch stop layer 12 and the material layer 22 are etched, and the sealing layer is covered. Steps 31 and the like are similar to the foregoing embodiments and will not be described again.

19 to 21 illustrate another embodiment of the present invention. In this embodiment, the manufacturing steps of the overlay wafer are slightly different. After the first substrate 11 is provided, the pattern of the etch stop layer 12 is defined thereon so as to at least correspond to a channel formed when the first substrate 11 is etched in the future. Position; Next, the first substrate 11 is etched in the defined region as shown in FIG. 19, and the etch stop layer 12 is deposited in the partial region as shown in FIG. 20, and then the first bonding layer 13 is formed as shown in FIG. The cover wafer formed in this embodiment can be combined with the component wafer in any of the foregoing manners, and the bonding process is similar to the foregoing embodiments, and details are not described herein.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. For those skilled in the art, various equivalent changes can be immediately considered within the spirit of the invention. For example, the materials, the number of layers, and the like in the above embodiments are all exemplified, and there are other possibilities for equivalent changes. Equivalent changes or modifications of the concept and spirit of the invention are intended to be included within the scope of the invention.

11‧‧‧First substrate

12‧‧‧etch stop layer

13‧‧‧First bonding layer

21‧‧‧second substrate

22‧‧‧Material layer

23‧‧‧Second bonding layer

24‧‧‧MEMS components

25‧‧‧Insulation

26‧‧‧Connecting mat

31‧‧‧ Sealing layer

1 to 3 show a first embodiment of the present invention for fabricating a covered wafer.

4 to 6 show a second embodiment of the present invention for fabricating a covered wafer.

7 through 8 show a first embodiment of the fabrication of a component wafer of the present invention.

9-13 show the steps of the present invention in conjunction with overlaying a wafer and a component wafer.

14 to 18 show a second embodiment of the fabrication of the component wafer of the present invention and the steps of bonding the wafer and the component wafer.

19 to 21 show a third embodiment of the present invention for fabricating a covered wafer.

11‧‧‧First substrate

13‧‧‧First bonding layer

21‧‧‧second substrate

22‧‧‧Material layer

23‧‧‧Second bonding layer

24‧‧‧MEMS components

26‧‧‧Connecting mat

Claims (17)

A micro-electro-mechanical system (MEMS) chip packaging method, the method comprising: fabricating a cover wafer, the method comprising: providing a first substrate; and forming an etch stop layer over the first substrate; The component wafer includes: providing a second substrate; forming a MEMS element and a material layer surrounding the MEMS element on the second substrate; and providing a connection pad on the material layer; bonding the cover wafer to the component wafer; After the overlay wafer is bonded to the component wafer, the first substrate is etched to form at least one via; the etch stop layer is etched by the via formed by the first substrate; and the material layer is etched. The MEMS chip packaging method of claim 1, further comprising: depositing a sealing layer on the first substrate. The MEMS chip packaging method of claim 2, wherein the material of the sealing layer comprises a metal. The MEMS wafer packaging method of claim 1, wherein the etch stop layer and the material layer are the same material. The MEMS wafer packaging method of claim 1, wherein the material of the etch stop layer and the material layer comprises an oxide. The MEMS wafer packaging method of claim 5, wherein the etch stop layer and the material layer are etched by hydrogen fluoride (HF) vapor etching. A micro-electro-mechanical system (MEMS) chip packaging method, the method comprising: fabricating a cover wafer, the method comprising: providing a first substrate; and forming an etch stop layer over the first substrate; a component wafer, the method comprising: providing a second substrate; forming a MEMS element and a material layer surrounding the MEMS element on the second substrate; providing a connection pad on the material layer; and depositing an insulating layer on the connection pad; The wafer is bonded to the component wafer; after the bonding wafer is bonded to the component wafer, the first substrate is etched to form at least one channel; the etch stop layer is etched by the channel formed by the first substrate; and the material is etched Floor. A micro-electro-mechanical system (MEMS) chip packaging method, the method comprising: fabricating a cover wafer, the method comprising: providing a first substrate; and forming an etch stop layer over the first substrate; Forming a component wafer, the method comprising: providing a second substrate; forming a MEMS element and a material layer surrounding the MEMS element on the second substrate; providing a connection pad on the material layer; and depositing an insulating layer on the connection pad; The cover wafer is bonded to the component wafer; after the cover wafer is bonded to the component wafer, the first substrate is etched to form at least one channel; the etch stop layer is etched by the via formed by the first substrate; and etching is performed a layer of material, wherein the insulating layer comprises tantalum carbide (SiC) or amorphous silicon. The MEMS chip packaging method of claim 1, wherein the step of etching the first substrate comprises an inductive coupling plasma (ICP). The MEMS chip packaging method of claim 1, further comprising thinning the thickness of the first substrate or the second substrate or both in a grinding manner after bonding. The MEMS chip packaging method of claim 1, wherein the first substrate has a thickness of between 100 μm and 200 μm. A micro-electro-mechanical system (MEMS) chip packaging method, the method comprising: fabricating a cover wafer, the step comprising: providing a first substrate; Forming an etch stop layer over the first substrate; forming a component wafer, the method comprising: providing a second substrate; and forming a MEMS component and a material layer surrounding the MEMS component on the second substrate; covering the wafer and the component Wafer bonding, wherein the step of bonding the cover wafer to the component wafer comprises: providing at least one bonding layer between the cover wafer and the component wafer in a hermetic or non-hermetic manner to bond the two; After the bonding wafer is bonded to the component wafer, the first substrate is etched to form at least one channel; the etch stop layer is etched by the via formed by the first substrate; and the material layer is etched; wherein the layer is etched in a non-hermetic manner The at least one bonding layer material comprises a photosensitive polymer when packaged. A micro-electro-mechanical system (MEMS) chip packaging method, the method comprising: fabricating a cover wafer, the method comprising: providing a first substrate; and forming an etch stop layer over the first substrate; The component wafer includes: providing a second substrate; and forming a MEMS element and a material layer surrounding the MEMS element on the second substrate; bonding the cover wafer to the component wafer, wherein the wafer and the component crystal are covered circle The step of bonding includes: providing at least one bonding layer between the cover wafer and the component wafer in a hermetic or non-hermetic manner to bond the two; wherein at least one of the bonding layer materials comprises one of the following: Parylene, polydimethyl siloxane (PDMS), epoxy or photo-imagable resin. The MEMS wafer packaging method of claim 12, wherein the hermetic package comprises a glass frit or a solder. The microelectromechanical system chip packaging method of claim 12, wherein the material of the at least one bonding layer comprises a metal or an alloy, and the alloy comprises one of the following: aluminum. Niobium alloy, sheet metal alloy, tin-silver alloy, niobium alloy, gold-tin alloy, lead-tin alloy. The MEMS chip packaging method of claim 1, wherein the step of fabricating the overlying wafer further comprises: defining a pattern of the etch stop layer such that the position corresponds at least to a position of the first substrate forming channel. The MEMS chip packaging method of claim 1, wherein the step of fabricating the overlying wafer further comprises: defining a pattern of the etch stop layer on the first substrate such that the pattern position corresponds at least to the formation of the first substrate a position of the channel; etching the first substrate according to the pattern; and forming an etch stop layer in the pattern region.