TWI509678B - Planar semiconductor device and manufacturing method thereof - Google Patents

Description

Planar semiconductor element and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a planar semiconductor device and a method of fabricating the same.

As the capabilities of semiconductor process technology continue to increase, the function of semiconductor wafers is becoming more and more powerful, so that the amount of semiconductor chip signals is gradually increased, and the number of chips is also increased; thus, packaging technology must be continuously improved with the evolution of technology. The semiconductor package provides functions such as integrated circuit protection, heat dissipation, and circuit conduction. In addition to high-order packaging technologies, such as Ball Grid Array (BGA), Flip-Chip (FC), and many The Multi Chip Module (MCM), the most commonly used is the lead frame package method, which mainly uses Die Attachment, Wired Bond, Molding, and Marking processes. Package.

Conventional use of lead frame packaging, the use of die bonding, bonding wire, and packaging process will lead to related problems, such as packaging process is cumbersome and time-consuming, resulting in increased costs and so on.

One of the objects of the present invention is to provide a planar semiconductor device and a method of fabricating the same, which can be integrally covered by an insulating structure to provide better protection of the device; Since the planar semiconductor element has a structure having conductivity and solderability such as a terminal electrode on each surface, the finished product can be directly soldered and fixed to an external device such as a circuit board.

The embodiment of the invention provides a method for fabricating a planar semiconductor device, comprising the following steps: Step 1: providing a wafer having a plurality of semiconductor components thereon, and having a plurality of corresponding surfaces on the wafer surface Leading regions of the semiconductor components; Step 2: performing a first insulating coating step to form a first insulating layer and a second insulating layer on the upper and lower surfaces of the wafer, wherein the lead regions are exposed The first insulating layer; step 3: forming a conductive pad on each of the lead regions; step 4: performing a cutting step to cut a single semiconductor component; and step 5: performing a second insulating blanketing step Forming a third insulating layer on the side of each of the diced semiconductor components; and step 6: forming one end electrode at each end of each of the diced semiconductor components, the terminal electrode being connected to the conductive pad.

Embodiments of the present invention provide a planar semiconductor device, comprising: a semiconductor device cut by a wafer having an upper surface, a lower surface, and a plurality of sides disposed between the upper and lower surfaces, the upper surface a plurality of lead regions; a plurality of insulating structures overlying the semiconductor component, the insulating structure comprising a first insulating layer formed on the upper surface, a second insulating layer formed on the lower surface, and a molding a third insulating layer on the sides, wherein the lead regions are exposed to the first insulating layer; a conductive pad correspondingly disposed on each of the lead regions; and two respectively disposed on the semiconductor component The terminal electrode of the terminal is connected to the conductive pad.

The invention has the following beneficial effects: the planar semiconductor component of the present invention can be completely covered by the insulating structure, so that the reliability of the component can be effectively improved. Further, the planar semiconductor device produced by the present invention can provide soldering positions in a plurality of directions, so that the efficiency of the soldering operation can be improved.

For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying drawings.

The invention provides a planar semiconductor component and a manufacturing method thereof. The planar semiconductor component proposed by the invention can be electrically connected to the circuit board without directionality, and does not need to pass through a wire, etc., thereby simplifying the subsequent connection process. the complexity.

Referring to FIG. 7, the method for fabricating a planar semiconductor device according to the present invention includes the following steps. Please refer to FIG. 1 , step S101 : providing a wafer 10 , and the wafer 10 can be formed with a plurality of semiconductor components 2 ′ according to requirements of subsequent processes or applications. For example, as shown in FIG. 1 , the wafer 10 can be processed according to a semiconductor process. Three semiconductor elements 2' are formed by lithography, thin film deposition, etching, doping, etc., and the semiconductor element 2' can be completed by the following steps to complete the planar semiconductor element of the present invention. In addition, in conjunction with FIG. 1A, the upper surface 102 of the wafer 10 has a plurality of lead regions 101 corresponding to the semiconductor elements 2'. In the present embodiment, each of the semiconductor elements 2' will be on the upper surface 102 of the wafer 10. A lead region 101 is formed thereon, and the lead region 101 may be an electrical connection point, a circuit contact, or the like, and the purpose thereof is to connect the circuit of the semiconductor element 2' to the outside, and the position of the lead region 101 may be Mutual alignment, mutual misalignment or other arrangement.

It should be noted that, in order to simplify the description, the present invention regards the wafer 10 and the semiconductor element 2' as the same structure in the longitudinal direction, so the upper and lower surfaces 102, 103 of the wafer 10 are directly referred to in the following steps. It is the upper and lower surfaces 102, 103 of the semiconductor element 2'.

Next, please refer to FIG. 1 and FIG. 1A; Step S103: performing a first insulation coating step to form a first insulating layer 11A and a second insulating layer on the upper and lower surfaces 102 and 103 of the wafer 10, respectively. 11B, wherein the lead region 101 is exposed to the first insulating layer 11A. In this embodiment, the first polymer layer 11A and the second insulating layer 11B are formed by applying an organic polymer coating, cerium oxide or polycrystalline silicon on the upper and lower surfaces 102 and 103 of the wafer 10, but Not limited to the above, the thickness of the first insulating layer 11A and the second insulating layer 11B is approximately 1 to 50 μm to achieve the effect of protecting the semiconductor element 2'. Preferably, the first insulating layer 11A has a plurality of through holes 111 corresponding to the lead regions 101, and the lead regions 101 are exposed to the first insulating layer 11A by the through holes 111 to prevent the electrically connected portions from being insulated by the first insulation. Layer 11A is blocked.

Next, please refer to FIG. 2; Step S105: Forming the conductive pad 12 on each lead region 101. In this embodiment, a conductive metal such as copper, nickel/gold, aluminum, titanium/tungsten or the like is formed on the lead region 101 to facilitate subsequent electrical conduction. In other words, the conductive pad 12 can contact the lead region 101 by the through holes 111 on the first insulating layer 11A. To simplify the description, FIG. 2 only draws two conductive pads 12 for respectively representing the connection positions of the different polarities (positive or negative) of the semiconductor element 2'.

Next, please refer to FIG. 3 and FIG. 3A; and step S107: a cutting step is performed to cut out a single semiconductor element 2'. In this embodiment, a cutting tool such as a diamond knife or a laser is used to perform a cutting operation along a previously planned cutting path on the wafer 10; and after the cutting, a single semiconductor element 2' is formed. The plurality of side faces 104, as shown in FIG. 3A, each of the diced semiconductor elements 2' has four upper and lower surfaces 102, 103 (also referred to as semiconductor elements 2'). The side surfaces 104 between the lower surfaces 102, 103), such as the front side, the back side, the left side and the right side, and the upper and lower surfaces 102, 103 are covered by the first insulating layer 11A and the second insulating layer 11B, and the sides 104 is exposed, so the next step is to completely protect the exposed side 104.

Please refer to FIG. 4; Step S109: performing a second insulation coating step to form a third insulating layer 11C on the side 104 of each of the diced semiconductor elements 2'. In this step, the third insulating layer 11C is also formed on the side surface 104 by using a material such as an organic polymer coating, cerium oxide or polycrystalline germanium. In this embodiment, the conductive pad 12 of the upper surface 102 of the semiconductor component 2' can be shielded by a fixture (not shown) to prevent the conductive pad 12 from being affected by the second insulation coating step, and the fixture is The semiconductor element 2' is placed in parallel with the plating apparatus to perform a second insulation coating step, and the four exposed side surfaces 104 are overlaid with the third insulating layer 11C.

After the second insulation blanketing step, the semiconductor component 2' is removed, and the fully encapsulated semiconductor component 2' (except the bare conductive pad 12) is obtained, in other words, first. The insulating layer 11A, the second insulating layer 11B, and the third insulating layer 11C may constitute an insulating structure that provides comprehensive and complete protection of the semiconductor element 2'.

The next step is to form a terminal electrode that is guided to the conductive pad 12 to electrically connect the semiconductor device 2' to an external device such as a circuit board. The step of forming the terminal electrode may include: refer to FIG. 5; step S111: forming an electrode layer 13 to be electrically connected to the conductive pad 12. As shown, since the two conductive pads 12 respectively represent different polarities of the semiconductor element 2', in this step, two electrode layers 13 are formed to correspond to the conductive pads 12 of the positive and negative electrodes. With one of the conductive pads 12 described, silver or copper glue is adhered to the insulating structure of the end faces of the semiconductor element 2' (ie, the upper and lower surfaces 102, 103 and the side surface 104), and dried (drying) a process, a curing process, or a firing process to form the electrode layer 13 described above, in other words, the electrode layer 13 extends from the upper surface 102 to the lower surface 103 via the side surface 104, and is in a coating contact The conductive pad 12 is formed to form an external guiding path.

Next, please refer to FIG. 6; Step S113: Forming a connection layer 14 to be applied to the electrode layer 13. In this embodiment, the connection layer 14 is formed by an electroplating method, such as electroplating of nickel or tin on the electrode layer 13, and the connection layer 14 has solderability to form a solder interface to improve the electrodes at both ends. Solderability, therefore, the operator can solder the formed planar semiconductor element 2 to an electronic circuit on an external device such as a circuit board.

It should be noted that the terminal electrode composed of the electrode layer 13 and the connection layer 14 can be structurally extended from the upper surface 102 to the lower surface 103 via the partial side surface 104, and the terminal electrodes are preferably formed on the front side and the back side, The planar semiconductor element 2 of the present invention does not have to be directional in soldering or assembly, and each surface can be connected to an external device such as a circuit board, so that subsequent connection operations can be greatly simplified. . Specifically, if the upper surface 102 of the conductive pad 12 is defined as a conductive surface, and the other surfaces are non-conductive surfaces, the method of the present invention can simultaneously form the terminal electrode on the conductive surface and the non-conductive surface. Therefore, the semiconductor element 2 can be directly connected to an external device such as a circuit board on the conduction surface or the non-conductive surface.

In summary, according to the above method, the present invention can produce a planar semiconductor device 2 having a good overlying structure and a solderable structure, including a semiconductor component 2', a plurality of insulating structures overlying the semiconductor component 2', and conductive Pad 12 and terminal electrode. The semiconductor device 2' has an upper surface 102, a lower surface 103, and a plurality of side surfaces 104 disposed between the upper and lower surfaces 102, 103. The upper surface 102 has a plurality of lead regions 101. The insulating structure includes a shape formed on the upper surface. a first insulating layer 11A on 102, a second insulating layer 11B formed on the lower surface 103, and a third insulating layer 11C formed on the side surfaces 104, wherein the lead region 101 is exposed to the first insulating layer 11A; the conductive pad 12 is disposed on the lead region 101, and the terminal electrode is connected to the conductive pad 12 and forms an outward connection path.

In addition, the planar semiconductor device 2 of the present invention may have a length, width, height dimension of 0.6 mm × 0.3 mm × 0.5 mm, 1.0 mm × 0.5 mm × 0.5 mm, or 1.6 mm × 0.8 mm × 0.5 mm, etc., but not The above is limited; for example, the maximum length, width, and height of the planar semiconductor device 2 of the present invention is 1.6 mm × 0.8 mm × 0.5 mm.

In summary, the present invention has at least the following advantages:

1. The present invention provides an insulation coating process for forming a terminal electrode having a solder interface on a semiconductor device for electrical connection with other circuit substrates, and omitting a conventional lead frame packaging process (for example, using a die bond, a wire bond) , packaging and other steps), the components can be fixed on the circuit board, thereby reducing the difficulty of the process. In addition, the planar semiconductor device of the present invention can be connected in any direction, so that the operator or the automation device can perform soldering without adjusting the orientation of the component, and further improve the efficiency of the soldering operation.

2. The process utilizes an insulating structure to protect the planar semiconductor component from environmental conditions such as moisture, dust or other foreign matter to improve the reliability of the component.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the equivalents of the present invention are intended to be included within the scope of the present invention.

10. . . Wafer

101. . . Lead area

102. . . Upper surface

103. . . lower surface

104. . . side

11A. . . First insulating layer

111. . . perforation

11B. . . Second insulating layer

11C. . . Third insulating layer

12. . . Conductive pad

13. . . Electrode layer

14. . . Connection layer

2'. . . Semiconductor component

2. . . Planar semiconductor component

S101～S113. . . Process step

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exploded view showing the first and second insulating layers of the present invention formed on a wafer.

1A is a schematic view showing the molding of the first and second insulating layers of the present invention on a wafer.

Figure 2 is a schematic view showing a molded conductive pad of the present invention.

Figure 3 is a schematic diagram showing the cutting of the present invention to form a single semiconductor component.

Figure 3A is a perspective view showing the cutting of the present invention to form a single semiconductor component.

Figure 4 is a schematic view showing the formation of a third insulating layer of the present invention.

Fig. 5 is a schematic view showing the formation of an electrode layer of the present invention.

Figure 6 is a schematic view showing the formation of a connection layer and formation of a planar semiconductor device of the present invention.

Fig. 7 is a flow chart showing a method of fabricating the planar semiconductor device of the present invention.

S101～S113. . . Process step

Claims (10)

A method for fabricating a planar semiconductor device, comprising the steps of: providing a wafer having a plurality of semiconductor elements thereon, and having a plurality of lead regions corresponding to the plurality of semiconductor elements on a surface of the wafer; a first insulating coating step of forming a first insulating layer and a second insulating layer on the upper and lower surfaces of the wafer, wherein the lead regions are exposed to the first insulating layer; forming a conductive pad Each of the lead regions; performing a cutting step to cut a single semiconductor component; performing a second insulating coating step to form a third insulating layer on the side of each of the diced semiconductor components; and forming one end An electrode is connected to the conductive pad at each end of each of the diced semiconductor components. The method of fabricating a planar semiconductor device according to claim 1, wherein in the step of performing an insulation coating step, the first insulating layer has a plurality of vias corresponding to the lead regions, the leads The regions are exposed to the first insulating layer by the vias. The method for fabricating a planar semiconductor device according to claim 1, wherein after the step of performing a dicing step, each of the diced semiconductor components has four electrodes disposed on the upper surface and the lower surface of the wafer. This side between. The method of fabricating a planar semiconductor device according to claim 3, wherein the third insulating layer is applied to the four sides in the step of the second insulating coating step. The method for fabricating a planar semiconductor device according to claim 1, wherein in the step of forming an electrode at one end, the method comprises the steps of: forming an electrode layer to be connected to the conductive pad; forming a connection layer to be coated The electrode layer. A planar semiconductor device produced by the method of fabricating a planar semiconductor device according to claim 1, wherein the planar semiconductor device comprises: a single semiconductor device formed by cutting the wafer, the single semiconductor The component has an upper surface, a lower surface, and a plurality of sides disposed between the upper and lower surfaces, the upper surface having the lead regions; a plurality of insulating structures overlying the single semiconductor component, the insulating structure including a molding a first insulating layer on the upper surface of the single semiconductor device, a second insulating layer formed on the lower surface of the single semiconductor device, and a surface formed on the side surfaces of the single semiconductor device a third insulating layer, wherein the lead regions of the single semiconductor device are exposed to the first insulating layer of the single semiconductor device; and a plurality of correspondingly disposed on each of the lead regions of the single semiconductor device a conductive pad; and two terminal electrodes respectively disposed at two ends of the single semiconductor component, wherein the two terminal electrodes are respectively connected to the conductive pad . The planar semiconductor device of claim 6, wherein the first insulating layer of the single semiconductor component has a plurality of Corresponding to the lead regions of the single semiconductor component, the lead regions of the single semiconductor component being exposed by the vias to the first insulating layer of the single semiconductor component and to the single semiconductor The conductive pads of the component are in contact. The planar semiconductor device of claim 6, wherein each of the terminal electrodes comprises an electrode layer that is connected to the conductive pad to which the terminal electrode is connected and a plurality of connection layers that are overlying the electrode layer. The planar semiconductor device of claim 6, wherein each of the terminal electrodes extends from the upper surface of the single semiconductor component via the side of the portion of the single semiconductor component to the single semiconductor component lower surface. The planar semiconductor device according to claim 6, wherein the maximum length, width, and height of the single semiconductor device is 1.6 mm × 0.8 mm × 0.5 mm.