TWI508157B - Semiconductor structure and method of manufacture - Google Patents

Description

Semiconductor structure and its manufacturing method

This invention relates to a semiconductor process and, more particularly, to a semiconductor structure and method of making same.

Due to the increasing importance of the variety of portable electronic products and their peripheral products such as communication, networking, and computers, and the development of these electronic products in the direction of versatility and high performance, semiconductor manufacturing processes It is constantly evolving toward a higher process evolution, and the high-density structure is the goal pursued by the industry. As a result, semiconductor and package manufacturers are turning to the development of semiconductor packaging to three-dimensional packaging technology to further realize the high-density packaging system required to support these thinner and lighter electronic products.

The three-dimensional packaging technology, the so-called 3D integrated circuit (3D IC), integrates a plurality of layers of wafers or circuit substrates having active components into a single integrated circuit by various means. Specifically, the 3D integrated circuit technology collectively sets a plurality of wafers on a single integrated circuit in a three-dimensional or three-dimensional configuration. Therefore, high-density electrical interconnect technology is required in 3D integrated circuit technology to provide electrical contacts on the active surface and/or back side of the wafer to provide a three-dimensional stack and/or a high-density package.

The technique of an interposer with a through silicon via (TSV) is one of the key technologies currently used to implement a 3D integrated circuit, which is a via hole provided as a vertical electrical connection in a wafer or a substrate. , stack more wafers on a given area to increase stack density. Moreover, the 矽 puncturing design can provide more efficient integration, for example, can integrate different processes or reduce the transfer delay, and at the same time, because of the shorter interconnect length, thereby reducing power consumption, improving performance, and increasing transmission bandwidth. Therefore, the helium perforation technology enables the technology of wafer stack assembly construction to further move toward the trend of low power, high density and miniaturization processes.

As shown in Figs. 1A to 1E, it is a schematic cross-sectional view of a conventional method of fabricating the interposer 1.

As shown in FIG. 1A, a substrate body 10 composed of a plurality of interposer units 10' having opposite crystallizing sides 10a and back sides 13 and a plurality of conductive vias 10c communicating with the crystallizing sides 10a are provided, and The crystallizing side 10a has a redistribution layer (RDL) 11 electrically connected to the conductive via 10c, and a glass plate 12 is bonded to the crystallizing side 10a by the bonding layer 120.

As shown in Fig. 1B, the back side 13 is ground to form an intermediate side 10b with respect to the crystallizing side 10a, and the conductive via 10c is connected to the intermediate side 10b.

As shown in FIG. 1C, an insulating layer 14 exposing the conductive via 10c is formed on the intermediate side 10b, and an under bump metallurgy (UBM) 15 is formed on the exposed end of the conductive via 10c. The under bump metal layer 15 is electrically connected to the conductive via 10c.

As shown in FIG. 1D, a plurality of conductive elements 16 such as solder balls are bonded to the metal layer 15 under the bumps, and then the conductive elements 16 are covered with an insulating paste 17.

As shown in FIG. 1E, the glass plate 12 and the bonding layer 120 are removed, and then cut along the interface between the interposer units 10', and the direction from the crystallizing side 10a toward the intermediate side 10b (eg, The direction of the arrow A is cut to obtain the plural interposer 1.

As shown in FIG. 1F, it is an application of the conventional interposer 1. After the insulating glue 17 is removed, at least one semiconductor component 18 is disposed on the circuit redistribution structure 11 of the interposer 1, the interposer 1 The intermediate side 10b is connected to a package substrate 19 by the conductive elements 16.

In the method of the conventional interposer 1, the insulating adhesive 17 is adhered to the intermediate side 10b, and then the cutting process is performed, and then the insulating rubber 17 is removed by ultraviolet (UV) irradiation or laser ablation, but Since the adhesive of the insulating rubber 17 is strong and is not easily removed, the insulating rubber 17 is likely to remain on the surface of the interposer 1.

Moreover, the process of removing the insulating rubber 17 is complicated, resulting in a substantial increase in cost.

Therefore, how to solve the shortcomings that the insulating rubber is easy to remain on the surface of the interposer is a technical problem that is currently being solved by various circles.

In order to solve the problems of the above-mentioned prior art, the present invention discloses a method for fabricating a semiconductor structure, comprising: providing a substrate body composed of a plurality of interposer boards having opposite intermediate sides and a crystallizing side, And having a plurality of conductive vias connected to the intermediate side and the crystallized side; and a cutting process for cutting from the intermediate side toward the crystallizing side to separate the interposers.

In the above method, the crystallizing side is formed with a line redistribution structure electrically connecting the conductive vias.

In the above method, the cutting process is performed along the interface between the interposers.

In the above manufacturing method, the semiconductor element is mounted on the crystallizing side before the cutting process is performed. Also included forming a package material on the crystallized side to encapsulate the semiconductor component.

In the above method, the method includes forming a line redistribution structure electrically connecting the conductive vias to the intermediate side.

In the above method, the package material is formed on the intermediate side, and a conductive pillar is formed in the package material, so that the conductive pillar is electrically connected to the conductive via. For example, the conductive post is exposed on the surface of the package.

In the above method, the plurality of conductive elements are formed on the end faces of the conductive vias corresponding to the intermediate sides.

The invention further provides a semiconductor structure comprising: an interposer having opposite intermediate sides and a crystallizing side, and a plurality of conductive vias connecting the intermediate side and the crystallizing side; and a semiconductor component disposed on the crystallizing side An encapsulating material is formed on the intermediate side; and a conductive pillar is embedded in the encapsulating material and electrically connected to the conductive perforation.

In the foregoing semiconductor structure, a circuit redistribution structure is formed on the crystallizing side and electrically connected to the conductive via.

In the foregoing semiconductor structure, a circuit redistribution structure is formed on the intermediate side and electrically connected to the conductive via. For example, the conductive post is electrically connected to the conductive via by the line redistribution structure.

In the foregoing semiconductor structure, the conductive pillar is exposed on the surface of the package.

In the foregoing semiconductor structure, another package material is formed on the crystallizing side and covers the semiconductor element.

It can be seen from the above that the manufacturing method of the present invention is that the cutting direction is from the intermediate side to the crystal side during the cutting process, so that no conventional insulating glue is formed on the intermediate side, and therefore, the method of the present invention has no conventional residue. The problem of the glue on the surface of the interposer can simplify the process while reducing costs.

1,20’,30’‧‧‧Intermediary board

10,20,30‧‧‧substrate body

10’‧‧‧Intermediary board unit

10a, 20a, 30a‧‧‧ crystallized side

10b, 20b, 30b‧‧‧Intermediate side

10c, 20c, 30c‧‧‧ conductive perforations

11,21,31,31’,41’‧‧‧Line redistribution structure

12‧‧‧ glass plate

120,250‧‧‧bonding layer

13,30b’‧‧‧ Back side

14,22,32‧‧‧Insulation

15,23,33‧‧‧Metal under the bump

16,24,24’,34,34’,44‧‧‧Conductive components

17‧‧‧Insulating adhesive

18,35‧‧‧Semiconductor components

19,38‧‧‧Package substrate

2,3,4‧‧‧Semiconductor structure

25‧‧‧ Carrying parts

36,46‧‧‧Package

36'‧‧‧Encapsulation layer

460‧‧‧ openings

47‧‧‧conductive column

S‧‧‧ cutting path

1A to 1E are schematic cross-sectional views showing a method of manufacturing a conventional interposer; FIG. 1F is a schematic cross-sectional view showing the application of a conventional interposer; and FIGS. 2A to 2B are a first embodiment of a method for fabricating the semiconductor structure of the present invention; FIG. 2B to FIG. 3B is a cross-sectional view showing a second embodiment of the method for fabricating a semiconductor structure according to the present invention; wherein the 3C' is a schematic view; FIG. 4A to FIG. 4B are cross-sectional views showing a third embodiment of the method for fabricating a semiconductor structure of the present invention; wherein FIGS. 4A to 4B' are diagrams 4A to 4B. Another way.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are for convenience of description and are not intended to limit the scope of the invention, and the relative relationship may be changed or adjusted. Without substantial changes to the technical content, it is also considered to be within the scope of the invention.

2A to 2B are schematic cross-sectional views showing a first embodiment of the method of fabricating the semiconductor structure of the present invention.

As shown in FIG. 2A, a substrate body 20 composed of a plurality of interposers 20' having opposite crystallizing sides 20a and intermediate sides 20b and a plurality of conductive vias communicating the crystallizing sides 20a and the interposing sides 20b is provided. 20c, and the line side 20a has a line redistribution structure (RDL) 21 electrically connected to the conductive via 20c, and a carrier 25 is bonded to the crystallizing side 20a by the bonding layer 250. An insulating layer 22 exposing the conductive via 20c is formed on the side 20b, and a bump under the gold is formed on the end surface of the conductive via 20c. An Under Bump Metallurgy (UBM) 23 is formed on the underlying metal layer 23 of the bump to bond a plurality of conductive elements 24 such as solder balls.

In this embodiment, the carrier 25 is a glass plate.

As shown in FIG. 2B, the cutting path S (as shown in FIG. 2A) is cut along each of the interposing plates 20', and the cutting direction is cut by the intermediate side 20b toward the crystallizing side 20a (eg, In the direction of arrow B), a plurality of semiconductor structures 2 are obtained. Thereafter, after the carrier 25 and the bonding layer 250 are removed, a semiconductor element (not shown) is placed on the line redistribution structure 21 of the crystal side 20a of the semiconductor structure 2.

In this embodiment, the cutting method is a knife cutting, a laser cutting or a hidden cutting.

In another embodiment, as shown in Fig. 2B', a plurality of conductive elements 24' such as solder balls may be bonded to the line redistribution structure 21 before cutting.

In the manufacturing method of the present invention, when the cutting process is performed, the carrier 25 is supported, and the cutting direction is from the intermediate side 20b toward the crystal side 20a. Therefore, it is not necessary to form a conventional insulating glue on the intermediate side 20b. The preparation method of the present invention has no problem of the conventional residual rubber material on the surface of the semiconductor structure 2, and can simplify the process and at the same time reduce the cost.

3A to 3D are schematic cross-sectional views showing a second embodiment of the method of fabricating the semiconductor structure of the present invention. The main difference between this embodiment and the first embodiment is that the crystallization process is performed first, and then the dicing process is performed, as described in detail below.

As shown in Fig. 3A, a substrate body 30 composed of a plurality of interposing plates 30' having opposite crystallizing sides 30a and back sides 30b', and a plurality of The conductive via 30c is connected to the crystallized side 30a, and the line side 30a has a line redistribution structure (RDL) 31 electrically connected to the conductive via 30c, and is bonded to the crystallized side 30a by the bonding layer 250. A carrier 25. Next, at least one semiconductor element 35 is bonded to the line redistribution structure 31 by a plurality of conductive elements 34' such as solder balls.

Next, a package material 36 is formed on the line redistribution structure 31 of the crystallizing side 30a to cover the semiconductor element 35.

As shown in Fig. 3B, a thinning process is performed to polish the back side 30b' to form an intermediate side 30b with respect to the crystallizing side 30a, and to connect the conductive via 30c to the intermediate side 30b.

As shown in FIG. 3C, an insulating layer 32 exposing the conductive via 30c is formed on the intermediate side 30b, and a bump underlying metal layer 33 is formed on the end surface of the conductive via 30c for the underlying metal layer 33. A plurality of conductive elements 34, such as solder balls, are bonded.

In another embodiment, as shown in FIG. 3C', a fan out process can be performed on the intermediate side 30b, that is, another line redistribution structure 31' is formed on the insulating layer 32. The line redistribution structure 31' is electrically connected to the conductive elements 34, and the circuit redistribution structure 31' is formed with an encapsulation layer 36'.

As shown in FIG. 3D, following the process of FIG. 3C, the cutting is performed along the interface between the interposing plates 30', and the interposing side 30b is cut toward the crystallizing side 30a, and the carrier is removed. 25 and bonding layer 250 are used to obtain a plurality of semiconductor structures 3 on which semiconductor elements 35 have been stacked.

In the subsequent process, as shown in FIG. 3E, the intermediate side 30b of the semiconductor structure 3 is connected to a package substrate 38 by the conductive elements 34.

4A to 4B are cross-sectional views showing a third embodiment of the method of fabricating the semiconductor structure of the present invention. The main difference between this embodiment and the second embodiment is that the molding process is performed on the intermediate side, as described in detail below.

As shown in FIG. 4A, a molding process is performed to form a package 46 on the line redistribution structure 41' of the intermediate side 30b, and a plurality of openings 460 are formed on the package 46 to rewire the line. A portion of the line surface of 41' is exposed to the openings 460.

As shown in FIG. 4B, a plurality of conductive pillars 47 are formed in each of the openings 460, and the line redistribution structure 41' is electrically connected to the conductive pillars 47, and the conductive pillars 47 are bonded to the conductive pillars. Element 44.

Thereafter, the cutting is performed along the cutting path S between the interposing plates 30', and the cutting direction is cut by the intermediate side 30b toward the crystallizing side 30a to obtain the plurality of semiconductor structures 4.

In addition, as shown in FIGS. 4A' and 4B', a plurality of conductive pillars 47 may be formed on a part of the line surface of the line redistribution structure 41', and the package material 46 is formed on the line redistribution structure 41'. The conductive pillars 47 are covered, and the conductive pillars 47 are exposed on the surface of the package 46. For example, the end faces of the conductive pillars 47 are flush with the surface of the package 46.

The present invention provides a semiconductor structure 4 comprising: an interposer 30', a semiconductor component 35, package materials 36, 46, and a plurality of conductive pillars 47.

The interposer 30' has an opposite intermediate side 30b and a crystallizing side 30a, and a plurality of conductive vias 30c that communicate with the interposing side 30b and the crystallizing side 30a, and the crystallizing side 30a has an electrical connection. The line of the perforations 30c is re-arranged 31.

The semiconductor element 35 is disposed on the crystallizing side 30a and electrically connected to the line redistribution structure 31.

The package material 36 is formed on the crystallizing side 30a and covers the semiconductor element 35.

The package material 46 is formed on the intermediate side 30b.

The conductive pillars 47 are embedded in the package 46 and electrically connected to the conductive vias 30c.

In one embodiment, the intermediate side 30b has a line redistribution structure 41' electrically connected to the conductive via 30c, such that the conductive post 47 is electrically connected to the conductive via 30c by the line redistribution structure 41'.

In one embodiment, the conductive pillars 47 are exposed on the surface of the package 46.

In summary, in the manufacturing method of the present invention, when the cutting process is performed, the cutting direction is from the intermediate side to the crystal side, so that it is not necessary to form a conventional insulating glue on the intermediate side, and therefore, the method of the present invention has no habits. Knowing the problem of residual glue on the surface of the semiconductor structure, and simplifying the process, while reducing costs.

The above embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention, and those skilled in the art can practice the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Semiconductor structure

20’‧‧‧Intermediary board

20a‧‧‧The crystal side

20b‧‧‧Intermediary side

20c‧‧‧Electrical perforation

21‧‧‧Line redistribution structure

22‧‧‧Insulation

23‧‧‧ Metal layer under the bump

24‧‧‧Conducting components

25‧‧‧ Carrying parts

250‧‧‧bonding layer

B‧‧‧ cutting direction

Claims (16)

A semiconductor structure comprising: an interposer having opposite intermediate sides and a crystallizing side, and a plurality of conductive vias connecting the intermediate side and the crystallizing side; a semiconductor component disposed on the crystallizing side; And the conductive pillar is disposed on the intermediate side and embedded in the packaging material, and electrically connected to the conductive through hole. The semiconductor structure of claim 1, further comprising a line redistribution structure formed on the crystallizing side and electrically connected to the conductive via. The semiconductor structure of claim 1, further comprising a circuit redistribution structure formed on the intermediate side and electrically connected to the conductive via. The semiconductor structure of claim 3, wherein the conductive post is electrically connected to the conductive via by the line redistribution structure. The semiconductor structure of claim 1, wherein the conductive pillar is exposed on a surface of the package. The semiconductor structure according to claim 1, further comprising another package material formed on the crystallizing side and covering the semiconductor element. A method of fabricating a semiconductor structure, comprising: providing a substrate body composed of a plurality of interposers, the substrate having opposite intermediate sides and a crystallizing side, and having a plurality of connections a conductive perforation on the intermediate side and the crystallizing side, and a carrier is coupled to the crystallizing side; a cutting process is performed to cut the direction from the intermediate side toward the crystallizing side; and the carrier is removed to separate each The intermediary board. The method of fabricating a semiconductor structure according to claim 7, wherein the crystallizing side is formed with a line redistribution structure electrically connecting the conductive vias. The method of fabricating a semiconductor structure according to claim 7, wherein the carrier is a glass plate. The method of fabricating a semiconductor structure according to claim 7, wherein the cutting process is performed along a boundary between the interposers. The method for fabricating a semiconductor structure according to claim 7 is further characterized in that the semiconductor element is mounted on the crystallizing side before performing the cutting process. The method of fabricating the semiconductor structure of claim 11, further comprising forming a package material on the crystallizing side to encapsulate the semiconductor element. The method for fabricating a semiconductor structure according to claim 7 further comprises forming a line redistribution structure electrically connected to the conductive vias on the intermediate side. The method of fabricating a semiconductor structure according to claim 7 further comprises forming a package on the intermediate side, and forming a conductive pillar in the package, so that the conductive post is electrically connected to the conductive via. The method of manufacturing a semiconductor structure as described in claim 14 of the patent application, The conductive pillar is exposed on the surface of the package. The method of fabricating the semiconductor structure of claim 7, further comprising forming a plurality of conductive elements on the end faces of the conductive vias corresponding to the intermediate sides.