TWI506549B - System and method for out-of-order prefetch instructions in an in-order pipeline - Google Patents

Description

System and method for out-of-order prefetch instructions in a sequential instruction pipeline

Embodiments of the present invention are related to out-of-order prefetch instructions in a sequence pipeline of a processor architecture.

Processor performance has improved over time for memory performance. The gap between processor and memory performance means that most processors today spend a lot of time waiting for data. Modern processors typically have cache memory on several levels of the wafer and possibly outside the wafer. These cache memories help to reduce data access time by keeping frequently accessed lines in closer, faster cache memory. Data prefetching is the practice of moving data from the slower layer of the cache memory/memory hierarchy to the faster layer before the data is needed by the software. Data prefetching can be done by software. Data prefetching can also be done by hardware. Both software and hardware technologies have performance limitations.

Description Apparatus, systems, and methods are provided that provide a processor architecture with out-of-order prefetch instructions for sequential pipelines. In one embodiment, a system including hardware (eg, data prefetch queues) and software data prefetching is implemented. In this system, the characteristics of the overall microarchitecture, the characteristics of the instruction set architecture, and the characteristics of the software base are embedded in the design, selection, and synthesis of various data prefetching techniques and features.

The sequential pipeline executes the instructions sequentially, while the out-of-order pipeline allows most of the instructions to be executed out of order, including explicit data prefetch instructions. One disadvantage of the sequential pipeline is that the resources required to execute a particular instruction are not immediately available, causing the pipeline (and therefore the instruction and all subsequent instructions) to stall and wait for resources. These delays can even be caused by explicit data prefetch instructions. The disadvantage of out-of-order pipelines is that the machines required for full out-of-order execution are expensive. Embodiments of the present invention eliminate some of the delays that can be triggered by resources that are expected to be unavailable by explicit data prefetch instructions. The processor architecture described herein for sequential pipelines is much less expensive than that required for out-of-order pipelines.

The capabilities provided by embodiments of the present invention can suspend certain explicit data prefetch instructions that cannot be executed due to unavailable resources without delaying subsequent instructions. Therefore, subsequent instructions are actually executed out of order with respect to data prefetching. After the address of the data prefetch instruction is read from the source register, this data prefetch is dispatched from the host line and enters the data prefetch queue. For example, the ALU pipeline reads the address of the data prefetch instruction before sending the data prefetch command to the data prefetch queue. Subsequent instructions can continue to execute while the data is prefetched while waiting for its resources to be executed in the data prefetch queue.

In the following description, in order to provide a more thorough understanding, various specific details are set forth, such as logic implementation, size and name of signals and busbars, types and interrelationships of system components, and logical segmentation/integration selection. However, it will be appreciated that those skilled in the art can practice embodiments of the invention without these specific details. In other examples, the circuit of the control structure and the gate level is not shown in detail to avoid obscuring the present. An embodiment of the invention. Those who are familiar with the general techniques in this area have the description of this article and can implement appropriate logic without much experience.

Certain terms are used in the following description to describe the features of the embodiments of the invention. For example, "logic" means hardware and/or software configured to perform one or more functions. For example, examples of "hardware" include, but are not limited to, integrated circuits, finite state machines, or even combinatorial logic. The integrated circuit can be in the form of a processor, such as a microprocessor, a special purpose integrated circuit, a digital signal processor, a microcontroller, and the like. The interconnections between the wafers can each be point-to-point or can be configured in multiple points, or some are point-to-point and others are multi-point configurations.

1 illustrates a flow diagram of an embodiment of a computer implementation method 100 for providing out-of-order prefetch instructions for a sequential pipeline in accordance with an embodiment. Method 100 is performed by processing logic, which can include hardware (circuitry, dedicated logic, etc.), software (such as performed on a general purpose computer system or a special purpose machine or device), or a combination of both. In an embodiment, method 100 is performed by processing logic associated with the architectures discussed herein.

At block 102, processing logic determines whether to issue a data prefetch instruction (eg, lfetch) to one or more factors (eg, the availability of one or more issue slots of the second type of sequential pipeline, the priority of the data prefetch instruction) A first type of sequential pipeline (eg, an arithmetic logic unit (ALU) pipeline, an integer pipeline) or a second type of sequential pipeline (eg, a memory pipeline). For example, for software, it is possible to encode via some instruction bundles, forcing lfetch to proceed to the second type of pipeline before another instruction that requires the same pipeline. Lfetch can be the lowest priority or the highest priority. The software scheduler can make this decision. The available issue slots for the second type of sequential pipeline may be limited (eg, 2 per clock cycle). At block 104, the first type of sequential pipeline receives the data prefetch command based on one or more factors and the decision of the software scheduler. At block 106, the first type of sequence pipeline reads the address register of the data prefetch instruction and sends the data prefetch instruction to the data prefetch queue. At block 108, when at least one execution slot of the second type of sequence pipeline is available, or by first obtaining other instructions that want to use the second type of sequence pipeline, the data prefetch queue sends the data prefetch command to the second Type sequence pipeline. Another instruction can be fetched first to avoid the data overflow of the data prefetch queue and thus the data prefetch instruction (eg lfetch ). Then, when the pipeline is delayed or replayed, lfetch is sent from the data prefetch queue to the second type pipeline. At block 110, the second type of sequence pipeline also uses the issue slot of the pipeline to receive other instructions (e.g., load, store).

In one embodiment, the first type of sequential pipeline is an arithmetic logic unit (ALU) for receiving ALU instructions and data prefetch instructions, and the second type of sequential pipeline is a memory pipeline.

2 illustrates a block diagram of a processor architecture in accordance with an embodiment. The processor architecture 200 includes a sequence pipeline 220 and an optional sequence pipeline 221 for receiving data prefetch instructions and other instructions. The sequence pipelines 220, 221 may be an arithmetic logic unit (ALU) pipeline for receiving ALU instructions and data prefetch instructions (eg, lfetch-on-A). Alternatively, at least one of the pipelines 220, 221 may be an integer pipeline for receiving integer instructions and data prefetch instructions. The individual pipelines 220, 221 can act together to form a single multi-instruction wide sequential pipeline. In other words, keeping instructions across pipelines and pipelines order.

The processor architecture 200 further includes a second type of sequence pipeline 230, 231 having an issue slot that receives other instructions via the multiplexers 218, 219. A slot refers to an entry in a pipeline that can contain operations. In an embodiment, the architecture includes at least one of the pipelines 230, 231. The processor architecture 200 includes a translation lookaside buffer (TLB) 240 having a number of ports for mapping virtual addresses to physical addresses.埠 refers to the input of large structures, such as an array of acceptable operations. TLB 240 and TLB 241 can be located in lines 230 and 231, respectively. When no individual virtual address associated with the data prefetch instruction is found in the TLB 240 or 241 (eg, the TLB lost lfetch), the data prefetch queue 210 receives the data prefetch instruction. The hardware page walker 250 accesses (eg, "checks the itinerary") the page table in the memory by issuing a special load instruction along the memory pipeline. When no data prefetch instruction is found in TLB 240 or 241, the hardware page check check is initialized. The hardware paged checker receives a hardware page check run via multiplexer 252 and includes some buffering to enable it to process simultaneous multi-hard page check passes without delaying the pipeline.

The data prefetch queue 210 sends the data prefetch instruction to the second type sequence pipeline 230 when at least one execution slot of the sequence pipeline is available, or by first obtaining other instructions that want to use the second type sequence pipeline. 231 at least one of them. If no hardware paging check is processed, the data prefetch command can be issued. This design does not always wait for all hardware page check passes to be processed before issuing a data prefetch command. For example, in implementation In the example, only those data prefetched by the data prefetching due to the TLB miss will wait for all hardware paging check strokes to be processed before the data prefetch is issued. The hardware paged checker 250 can insert the respective translations into their respective TLBs for their respective data prefetch instructions or failed hardware page check passes. If the hardware page check and the translation are not in the TLB for the second time, the data prefetch command is discarded. When multiple data prefetch instructions arriving on the same page are not found in their respective TLBs, multiple hardware page check passes can be combined into a single page check run.

A second type of sequential pipeline can be executed when a multi-hardware page check run occurs.

The processor architecture of this design adds several data prefetch features (eg, sending lfetch instructions to the first type of pipeline, non-blocking lfetch as described below, etc.). The built micro-architecture enables all of these prefetching mechanisms with minimal cost and complexity, and it is easy to add additional prefetching mechanisms.

FIG. 3 illustrates a processor architecture 300 having a data prefetch queue (DPQ) 310 in accordance with an embodiment. DPQ 310 may be a first in first out (FIFO) structure that temporarily stores prefetch requests from some or all of the software and hardware prefetch sources described herein. This structure allows the pre-fetched short bursts to be accepted without back pressure. 3 shows how the prefetch system 302 including the DPQ 310, the engine 314, the MLD prefetcher 360, and the multiplexers 311, 312, 318, and 319 are connected to the existing pipelines 320, 321, 330, and 331, and How the data prefetch queue 310 is the central hub of the prefetch system 302. The prefetch of the mid-level data cache (MLD) 370 can come from the MLD prefetcher block 360. The Lfetch instruction from the lfetch-on-A pipeline feature may come from one of the first type of sequence pipelines 320, 321 (eg, the A pipeline). The prefetch associated with the non-blocking data TLB or the first order data cache (FLD) hardware prefetch feature may be from one of the second type of sequence pipelines 330, 331 (eg, the M pipeline). Next, in the period when the supervisor line instruction buffer logic (IBL) 302 does not issue an instruction into the same M pipeline, the DPQ will prefetch the M pipeline inserted into either one. Sometimes in order to avoid discarding the lfetch instruction, the DPQ takes precedence over waiting for other M-line instructions to be issued from the host line instruction buffer.

In one embodiment, the DPQ is an 8-input FIFO. Each prefetch request just occupies one entry in the DPQ, even though it will eventually be expanded into several separate prefetches. When the prefetch request reaches its FIFO header, it is moved into the expansion engine (EE) 314. The EE 314 expands the prefetch request from the DPQ into a separate prefetched group and then sequentially injects these separate prefetches into the M pipeline. The EE also allows for separate prefetches to be spanned to the opposite M line in order to use the unused line slots most efficiently. As illustrated in Figure 3, the DPQ can have two write buffers. The first port 316 can take a write from line 330 or line 320, and the second port 317 can take a write from line 331 or line 321 or the MLD prefetcher. The DPQ accepts one prefetch request per cycle per cycle. The lfetch on A 埠 should be inserted into the DPQ. If the data TLB is missed, the lfetch on M 埠 needs to be inserted into the DPQ. If there are two DPQ insertion requests on a single DP of the DPQ, only the insertion from A埠 occurs. The output of the MLD hardware prefetch block 360 includes a small FIFO queue (Q) that can be buffered and later inserted into the DPQ if its request conflicts with other prefetch requests. Within DPQ, all types of prefetches are maintained in order, but the lfetch instruction is given a higher importance than the prefetch initiated by the hardware. For example, if lfetch has been waiting in the extension engine for too long and still does not find an unused pipeline slot to use, it will trigger a pipeline bubble to force an empty slot. However, if the hardware prefetch waits too long, it may be discarded. In addition, if the DPQ begins to fill up, the waiting hardware prefetch may be deleted to create more space for the new lfetch . DPQ provides an efficient, centralized, and sharable resource to handle prefetching from a variety of sources.

FIG. 4 illustrates a block diagram of a system 1300 in accordance with an embodiment. System 1300 includes one or more processors 1310, 1315 coupled to a graphics memory controller hub (GMCH) 1320. An additional processor 1315 of a selected nature is indicated in Figure 4 by a dashed line. A portion of one or more processors 1310, 1315 includes the processor architecture (e.g., 200, 300) discussed above. In an embodiment, the architecture includes a first type of sequential pipeline 220 and an optional second pipeline 221. These pipelines (such as the ALU pipeline) can receive ALU commands and data prefetch instructions. These pipelines receive at least one data prefetch instruction from instruction buffer logic (IBL) 202. The second type of sequence lines 230, 231 (e.g., memory lines) have firing slots and execution slots. Other instructions from IB 202 are received in the issue slot. The data prefetch queue 210 receives at least one data prefetch instruction from one or both of the pipelines 220, 221. When at least one execution slot of the pipelines 230, 231 is available, the data is pre- The queue 210 issues at least one data prefetch command to at least one of the second type sequence pipelines 230, 231. The system further includes one or more execution units 232, 234 for executing instructions associated with execution slots of the second type of sequence pipelines 230, 231. Execution units may be located in sequential pipelines 230 and 231 or associated with pipelines 230, 231. The software scheduler determines whether to send at least one material prefetch instruction to the first type of sequential pipeline (eg, 220, 221) or to the second type of sequential pipeline (eg, according to the availability of one or more of the second type of sequential pipelines) 230, 231). In an embodiment, the first type of sequential pipeline is an integer pipeline for receiving integer instructions and data prefetch instructions. System 1300 further includes a memory 1340 coupled to one or more processing units. One or more execution units of the second type of sequential pipeline send data associated with the executed instructions to the memory.

4 illustrates that the GMCH 1320 is coupled to a memory 1340, such as a dynamic random access memory (DRAM). In at least one embodiment, the DRAM is associated with a non-volatile cache memory.

The GMCH 1320 can be part of a wafer set or wafer set. The GMCH 1320 can communicate with the processors 1310, 1315 and control the interaction between the processors 1310, 1315 and the memory 1340. The GMCH 1320 also serves as an acceleration bus interface between the processors 1310, 1315 and other components of the system 1300. With respect to at least one embodiment, the GMCH 1320 communicates with the processors 1310, 1315 via a multi-point bus (such as a front side bus (FSB) 1395).

In addition, the GMCH 1320 is also coupled to a display 1345 (such as a flat panel display). The GMCH 1320 can include an integrated graphics accelerator. GMCH The 1320 is further coupled to an input/output (I/O) controller hub (ICH) 1350 that is used to couple various peripheral devices to the system 1300. The example shown in the embodiment of FIG. 4 is an external drawing device 1360 along with another peripheral device 1370, which may be a separate drawing device coupled to the ICH 1350.

There may also be additional or different processors in system 1300. For example, the additional processor 1315 can include the same additional processor as the processor 1310, the additional processor being heterogeneous or asymmetric to the processor 1310, an accelerator (such as a graphics accelerator or digital signal processing (DSP) unit), on-site Program gate array, or any other processor. In terms of measuring various features, various differences between physical resources 1310, 1315 include architecture, microarchitecture, heat, power consumption characteristics, and the like. These differences effectively show that the processing elements 1310, 1315 are themselves asymmetric and heterogeneous. With regard to at least one embodiment, different processing elements 1310, 1315 can be present within the same wafer package. During execution of the software (e.g., software scheduler) by the processing elements 1310, 1315, it is also wholly or at least partially resident within the processing elements 1310, 1315. Processing elements 1310, 1315 also form a machine-accessible storage medium and processor architecture 200.

Referring now to Figure 5, a block diagram of a second system 1400 in accordance with an embodiment of the present invention is shown. As shown in FIG. 5, multiprocessor system 1400 is a point-to-point interconnect system and includes a first processor 1470 coupled to a second processor 1480 via a point-to-point interconnect 1450. As shown in FIG. 5, each processor 1470, 1480 includes a processor architecture (e.g., 200, 300) as described herein. When a software (such as a software scheduler) is executed by the processor, it is also completely Or at least partially resident in the processor. The processor also constitutes a machine-accessible storage medium. Alternatively, the one or more processors 1470, 1480 can be components other than the processor, such as an accelerator or a field programmable gate array. Although only two processors 1470, 1480 are shown, it is to be understood that the scope of embodiments of the present invention is not limited thereto. In other embodiments, there may be one or more additional processing elements in a processor.

Processor 1470 can further include an integrated memory controller hub (IMC) 1472 and point-to-point (P-P) interfaces 1476 and 1478. Likewise, second processor 1480 can include IMC 1482 and point-to-point (P-P) interfaces 1486 and 1488. Processors 1470, 1480 exchange data via point-to-point (PtP) interface 1450 using point-to-point (PtP) interface circuits 1478, 1488. As shown in FIG. 5, IMCs 1472, 1482 couple the processors to respective memories, namely memory 1442 and memory 1444, which may be part of the main memory that is locally attached to each processor.

Processors 1470, 1480 exchange data with wafer set 1490 via point-to-point interface circuits 1476, 1494, 1486, 1498 via individual P-P interfaces 1452, 1454. Wafer set 1490 also exchanges data with high performance graphics circuitry 1438 via high performance graphics interface 1439.

A shared cache memory (not shown) that may be included in either processor is external to both processors, but is coupled to the processor via a PP interconnect such that if the processor enters a low power mode, either or both The processor's local cache information can be stored in the shared cache memory.

Wafer set 1490 is coupled to first bus bar 1416 via interface 1496. In an embodiment, the first bus bar 1416 can be a peripheral component interconnect (PCI) bus, or such as a PCI Express Bus or other third generation I/O interconnect bus, although the scope of embodiments of the present invention is not limited in this respect.

As shown in FIG. 5 , various input/output devices 1414 can be coupled to the first bus bar 1416 , and the bus bar bridge 1418 coupled to the first bus bar 1416 is coupled to the second bus bar 1420 . In an embodiment, the second bus bar 1420 can be a low pin count (LPC) bus bar. In an embodiment, various devices that can be coupled to the second busbar 1420 include, for example, a keyboard/mouse 1422, a communication device 1426, and a data storage unit 1428, such as a disk drive or other mass storage device including a code 1430. . Additionally, the audio I/O 1424 can be coupled to the second bus bar 1420. Please note that other architectures are also available. For example, the system can be implemented as a multi-point transmission bus or other such architecture instead of the point-to-point architecture of FIG.

Referring now to Figure 6, a block diagram of a third system 1500 in accordance with an embodiment of the present invention is shown. The same elements in Figures 5 and 6 bear the same reference numerals, and in order to avoid obscuring the other aspects of Figure 6, certain aspects of Figure 6 have been removed from Figure 6.

The processing elements 1470, 1480 illustrated in FIG. 6 may each include a processor architecture (eg, 200, 300), integrated memory and I/O control logic ("CL") 1472 and 1482, respectively. For at least one embodiment, CL 1472, 1482 may include memory controller hub logic (IMC), such as those previously described in relation to Figures 4 and 5. Additionally, CL 1472, 1482 can include I/O control logic. 6 illustrates not only that memory 1442, 1444 is coupled to CL 1472, 1482, but also that I/O device 1514 is also coupled to control logic 1472, 1482. A conventional I/O device 1515 is coupled to the chip set 1490.

Figure 7 illustrates a functional block diagram of a system 700 implemented in accordance with an embodiment. The illustrated embodiment of processing system 700 includes one or more processors (or central processing units) 705 having processor architecture 790 (eg, processor architecture 200, processor architecture 300), system memory 710, non-volatile ( "NV" memory 715, data storage unit ("DSU") 720, communication link 725, and chipset 730. The illustrated processing system 700 can represent any computing system, including desktop computers, notebook computers, workstations, handheld computers, servers, blade servers, and the like.

The interconnection of the components of processing system 700 is as follows. The processor 705 is communicatively coupled to the system memory 710, the NV memory 715, the data storage unit 720, and the communication link 725 via the chipset 730 to transmit/receive commands or data. In one embodiment, the NV memory 715 is a flash memory device. In other embodiments, NV memory 715 includes any of read only memory (ROM), programmable ROM, erasable programmable ROM, electrically erasable programmable ROM, and the like. In one embodiment, system memory 710 includes random access memory (RAM) such as dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDR SDRAM), static RAM (SRAM), and the like. The DSU 720 represents any storage device for software materials, applications, and/or operating systems, but is most typically a non-volatile storage device. The DSU 720 can optionally include one or more integrated drive electronic (IDE) hard disk drives, an enhanced IDE (EIDE) hard disk drive, and a multi-disk array (redundant array of independent Disks; RAID), small computer system interface (small Computer system interface; SCSI) hard disk drive, and the like. Although the illustrated DSU 720 is internal to the processing system 700, the DSU 720 can be externally coupled to the processing system 700. Communication link 725 couples processing system 700 to the network such that processing system 700 can communicate with one or more other computers over the network. Communication link 725 may include a data machine, an Ethernet card, a one billion bit Ethernet card, a universal serial bus (USB) port, a wireless network interface card, a fiber optic interface, and the like.

The DSU 720 can include machine-accessible media 707 on which one or more sets of instructions (e.g., software) are stored, embodying any one or more of the methods or functions described herein. The software (software scheduler), while being executed by the processor 705, also resides entirely or at least partially within the processor 705, which also constitutes a machine-accessible storage medium.

Although the machine-accessible medium 707 shown in the illustrative embodiments is a single medium, the term "machine-accessible media" shall include a single medium or multiple media (eg, centralized) for storing one or more sets of instructions. Or decentralized database, and/or associated cache and server). "Machine-accessible media" shall also include any medium that can store, encode, or carry a set of instructions for machine execution and cause the machine to perform any one or more of the embodiments of the present invention. Thus, the term "machine-accessible media" shall include, but is not limited to, solid state memory, optical, and magnetic media.

Thus, machine-accessible media, including the form of information provided (ie, stored and/or transmitted), can be used by a machine (eg, a computer, a network device, a personal digital assistant, a manufacturing implement, any one or more processor groups) Any mechanism for accessing devices, etc.). For example, machine accessible media includes recordable/not Recordable media (eg, read only memory (ROM); random access memory (RAM); disk storage media; optical storage media; flash memory devices, etc.), and electrical, optical, acoustic, or other propagating signals The form (such as carrier wave, infrared signal, digital signal, etc.);

As illustrated in Figure 7, each sub-assembly of processor system 700 includes input/output (I/O) circuitry 750 for communicating with one another. I/O circuit 750 can include an impedance matching circuit that can be adjusted to achieve a desired input impedance to reduce signal reflections and interference between sub-components. In an embodiment, PLL architecture 700 (e.g., PLL architecture 100) may be included in a variety of different digital systems. For example, PLL architecture 790 can be included in processor 705 and/or communicatively coupled to the processor to provide a resilient clock source. A clock source can be provided to the state element of processor 705.

It should be understood that various other components of processing system 700 have been excluded from Figure 7 and its discussion for clarity. For example, processing system 700 can further include a graphics card, additional DSUs, other persistent data storage devices, and the like. Wafer set 730 may also include a system bus for interconnecting sub-assemblies and a variety of other data busses, such as a memory controller hub and an input/output (I/O) controller hub, and The peripheral devices are connected to the data busbars of the wafer set 730 (eg, peripheral component interconnect busbars). Accordingly, processing system 700 is also operable with less than one or more of the elements illustrated in the figures. For example, processing system 700 need not include DSU 720.

The processor design described in this article includes a strong new microarchitecture design. In a particular embodiment, this design includes eight multi-thread cores located on a single chip and can issue up to 12 instructions per cycle to the execution pipeline. 12 pipelines can include 2 M pipelines (memory), 2 A pipelines (ALU), 2 I pipelines (integer), 2 F pipelines (floating point), 3 B pipelines (branch), and 1 N line (NOP). Line number M is reduced from the previous Itanium ^® processor 4-2. As previously Itanium ^® processor design, the stop command is issued with the order. Memory operations detect any errors before they are stopped, but they can be stopped before the memory operation is completed. Instructions that load the target scratchpad are used to delay their execution until the loading is complete. The memory command using the stored memory result can be stopped before the storage is completed. The cache layer ensures that such memory operations will be completed in the normal order.

The data cache hierarchy can be composed of the following cache levels: 16 KB first level data cache (FLD-core private)

256 KB intermediate data cache (MLD-core private)

32 MB last level instruction and data cache (LLC - all 8 cores shared)

LLC contains all other caches. All 8 cores can share LLC. MLD and FLD are for private use by a single core. The threads on a particular core share all levels of cache. All data caches can have a 64-bit cache line. To simulate the performance of a previous group of 128-bit cache line Itanium ^® processors, typical, triggering the extraction of the MLD miss two 64- byte lines, which together into a set of 128-bit aligned Block. This last feature is called MLD paired line prefetch processor architecture (e.g. Itanium ^® Architecture), which is defined or may not include an error address debug software may be used to prefetch data into a different cache levels lfetch various commands. This lfetch instruction does not require an architectural order for other memory operations.

Because Itanium ^® architecture optimized for software support includes the software and focus data prefetching, so software running on the processor design described in this document, other than in the case of the architecture of software are more likely to contain information on pre take. This software data prefetch has been very successful in improving performance. In one embodiment, the exemplary software executed on the processor design would be a large enterprise application. These applications tend to have large cache and memory usage and require high memory bandwidth. Data prefetching, such as all forms of speculation, can result in performance loss when the guess is incorrect. Based on this, it is important to minimize the number of useless data prefetches (not prefetching data for cache misses). Data prefetch consumes different levels of entry and exit from the memory hierarchy and limited bandwidth between them. Data prefetch moves other lines away from the cache memory. Unwanted data prefetch consumes these resources without any benefit and undermines the possible better use of such resources. In the multi-threaded multi-core processor described above, shared resources such as communication links and cache memory are heavily utilized by non-measured access. Large enterprise applications tend to emphasize these shared resources. In such systems, it is critical to limit the amount of useless prefetches to avoid wasting resources that have been used by unintended access. Interestingly, software data prefetching techniques have a tendency to produce less useless prefetching than many hardware data prefetching techniques. However, due to the dynamic nature of its input, hardware data prefetching techniques have the ability to generate useful data prefetches that are sometimes unrecognizable by software. Software and hardware data prefetching have a variety of other complementary strengths and weaknesses. The processor design makes the software prefetch more efficient, improves the conservation, complements the high precision hardware data prefetching without damaging the software data prefetching, obtaining the average wide gain without significant loss and slight loss. Robust performance gains minimize the design resources required.

Some features of this process design enhance the efficiency of software data prefetching. These features are called lfetch -on-A and non-blocking lfetch . Hardware data prefetching features include MLD hardware prefetching and FLD hardware prefetching. The microarchitecture feature of the processor design is a Data Prefetching Queue (DPQ), which is a shared resource that involves performing data prefetching associated with all of the features described herein. Software codes executed on a processor (e.g., processor Itanium ^®), may be implemented for each type of instruction cycle execution units available and the number of knowledge to schedule. On the previous Itanium ^® processor, lfetch instructions are executed on the M line, together with all the other memory operations (such as the loading and storage). In one embodiment, as described herein, the software can use up to two M-line firing slots per cycle. Thus, the need to use the M-line to issue slots is an important cost associated with lfetch . Interestingly, although the firing slots on the M-line may be insufficient, a large portion of the M-line execution slots in the cycle are not used due to delays and replays in the pipeline of the design. This idle bandwidth cannot be used by the software because the delay or replay of an instruction defined in the sequential pipeline will delay or replay all subsequent instructions. In addition to the two M pipelines, the processor architecture also has two A pipelines and two I pipelines. The importance of the A pipeline is much lower than that of the M pipeline and is much longer than that of the M pipeline. This is because the ALU command executed by the A pipeline can also be executed by the I pipeline or the M pipeline. As mentioned previously, lfetch allows execution in any order relative to other memory operations. Therefore, lfetch 's non-faulting feature only requires a register to access its instructions sequentially. The portion of the memory access lfetch can be deferred.

This design allows lfetch to be sent to the A or M pipeline for efforts to reduce the cost of issuing the lfetch command. When lfetch is sent down to the A pipeline, it simply reads its address register and places it into the DPQ. Then, when the M pipeline is delayed or replayed, lfetch can be sent from the DPQ to the M pipeline. The lfetch instruction sent to the A pipeline has a longer latency (eg, a minimum of +7 cycles), but it only needs to use the execution slot of the M pipeline instead of the issue slot of the M pipeline instruction. The software scheduler controls which line lfetch goes down to, so this feature gives the software the ability to issue a bandwidth lfetch for the M pipeline.

A processor (e.g., processor Itanium ^®) having a trip check paging hardware device, which can be found in the memory of the virtual hash page table heteroaryl (virtual hash page table; VHPT) in translation, and inserted into the TLB. In the previous Itanium ^® processor, when lfetch data TLB misses the trip to check paging and initializes the hardware, the duration of the delay line to check travel period paging hardware. The problem with this approach is that useless lfetch will delay the pipeline for a long time. Due to the inherent speculation of the lfetch instruction, it would uselessly attempt to refer to a page that has never been referenced by an unintended instruction. An example of this is when the lfetch instruction is used in the loop to prefetch data that may be needed in a later iteration of the loop. In this case, some useless lfetch instructions have been issued when the loop exists. Such instructions can easily lead to useless hardware paging checks and associated long-term pipeline delays. It is worth noting that the lfetch instruction that always discards the missed material TLB is not a good choice because sometimes prefetching is required. An example of this is a loop that accesses data from a large address space. This type of loop needs to trigger quite a lot of hardware paging checks. If the lfetch instructions are discarded, they may lose a lot of useful prefetches when they miss the data TLB.

To raise this issue and make software data prefetching more efficient, this design uses most of the lfetch directives as non- detection types, and such lfetch can be about the fact that all other instructions are executed out of order. First, the design extends the ability of the hardware page checker to allow it to handle multiple hardware page check passes simultaneously. Second, the design uses DPQ to queue the lfetch instructions for the missing data TLB. Therefore, in this design, the lfetch of the miss data TLB can trigger a hardware page check check and then be placed into the DPQ, which is then sent after the hardware page check check is inserted into the TLB. When multiple lfetch instruction misses the material TLB on the same page, multiple possible hardware page check passes are merged into a single walk, and all lfetch instructions are placed into the DPQ. If the DPQ is filled with the lfetch command, it will delay the supervisor line to avoid dropping lfetch . This technique is similar to the technique of making the cache unblocked. Like a non-blocking cache, a non-blocking TLB access becomes a blocking access when the queue entry is exhausted.

The MDL hardware prefetcher is a sequential prefetcher that moves lines from higher order caches or memories into MLD. It tracks the spatial location of the mid-level data cache miss and may request additional lines near the trigger miss. As illustrated in FIG. 3, the prefetcher tracks up to 8 missed address streams based on 4K pages based on monitoring MLD to ring 380 transmissions, interface to LLC cache accesses. For each address stream, it records the most recent miss address and the current prefetch direction and depth. For each miss within the five cache lines that were previously missed, the prefetcher first issues a sequence in the forward or backward direction corresponding to the corresponding number recorded in the prefetch depth column of the corresponding historical login. take. Next, it increases the prefetch depth of the address stream up to 4 cache lines. Essentially, this prefetch algorithm dynamically adjusts the effective line size of the mid-level data cache, depending on the spatial location of the cache miss being observed. To reduce the potential negative effects of prefetching caused by hardware, the MLD prefetcher only responds to the requested load miss as a trigger. Software-induced prefetching ( lfetch ), storage misses, and hardware-initiated prefetches are ignored. In addition, MLD prefetch requires filling up the mid-level data cache in non-recently used states. Therefore, useless prefetching in the same group has a higher probability of being evicted before other lines, and useful prefetching will be marked as the most recently used on the first request to access the line.

It is to be understood that the phrase "a" or "an" or "an" Therefore, it is emphasized that the two or more "embodiments", "an embodiment", or "alternative embodiment" referred to in the various parts of the specification are not necessarily all referring to the same embodiment. Furthermore, it is also appropriate to combine these specific features, structures, or characteristics in one or more embodiments.

The detailed description of the various embodiments of the present invention is set forth in the accompanying drawings. In each figure, from beginning to end In the figures, the same numbers describe substantially similar components. The embodiments described are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments are utilized or derived from the embodiments, such that structural and logical substitutions and changes can be made without departing from the scope of the disclosure. Therefore, the following detailed description is not to be construed as limiting the scope of the claims

200‧‧‧ processor architecture

202‧‧‧Instruction Buffer Logic

220‧‧‧Sequential pipeline

221‧‧‧Sequential pipeline

230‧‧‧Second type sequential pipeline

231‧‧‧Second type sequential pipeline

218‧‧‧Multiplexer

219‧‧‧Multiplexer

240‧‧‧Translated backup buffer

241‧‧‧Translated backup buffer

210‧‧‧ Data prefetch queue

250‧‧‧Hardware paging checker

252‧‧‧Multiplexer

300‧‧‧ Processor Architecture

302‧‧‧Instruction Buffer Logic

310‧‧‧ Data prefetch queue

311‧‧‧Multiplexer

312‧‧‧Multiplexer

314‧‧‧Extension engine

316‧‧‧ first

317‧‧‧Second

318‧‧‧Multiplexer

319‧‧‧Multiplexer

320‧‧‧ pipeline

321‧‧‧ pipeline

330‧‧‧ pipeline

331‧‧‧ pipeline

360‧‧‧Intermediate data cache hardware prefetcher

370‧‧‧Intermediate data cache

1300‧‧‧ system

1310‧‧‧ processor

1315‧‧‧ Processor

1320‧‧‧Graphics and Memory Controller Hub

1340‧‧‧ memory

1345‧‧‧ display

1350‧‧‧Input/Output Controller Hub

1360‧‧‧External drawing device

1370‧‧‧peripheral device

1395‧‧‧ front-end busbar

1400‧‧‧Multiprocessor system

1470‧‧‧First processor

1480‧‧‧second processor

1450‧‧‧ Point-to-point interconnection

1472‧‧‧Integrated Memory Controller Hub

1482‧‧‧Integrated Memory Controller Hub

1476‧‧‧ point-to-point interface

1478‧‧‧ point-to-point interface

1486‧‧‧ peer-to-peer interface

1488‧‧‧ point-to-point interface

1450‧‧‧ peer-to-peer interface

1442‧‧‧ memory

1444‧‧‧ memory

1494‧‧‧ peer-to-peer interface

1498‧‧‧ peer-to-peer interface

1452‧‧‧ peer-to-peer interface

1454‧‧‧ point-to-point interface

1490‧‧‧ chipsets

1438‧‧‧High performance drawing circuit

1439‧‧‧High-performance graphical interface

1496‧‧ interface

1416‧‧‧First bus

1414‧‧‧Input/output devices

1418‧‧‧ bus bar bridge

1420‧‧‧Second bus

1422‧‧‧Keyboard/mouse

1426‧‧‧Communication device

1428‧‧‧Data storage unit

1430‧‧‧ yards

1424‧‧‧Audio input/output

1514‧‧‧Input/output devices

1515‧‧‧Traditional input/output devices

700‧‧‧Processing system

790‧‧‧ Processor Architecture

705‧‧‧ processor

710‧‧‧ system memory

715‧‧‧ Non-volatile memory

720‧‧‧ data storage unit

725‧‧‧Communication links

730‧‧‧ chipsets

707‧‧‧Machine accessible media

750‧‧‧Input/Output Circuit

790‧‧‧PLL architecture

380‧‧‧ Ring

The various embodiments of the present invention are illustrated by the non-limiting example of the accompanying drawings in which: FIG. 1 illustrates an embodiment of a computer implemented method for providing out-of-order prefetch instructions for sequential pipelines in accordance with an embodiment of the present invention. FIG. 2 illustrates a processor architecture in accordance with an embodiment of the present invention; FIG. 3 illustrates a processor architecture in accordance with another embodiment of the present invention; FIG. 4 is a block diagram of a system in accordance with an embodiment of the present invention; A block diagram of a second system in accordance with an embodiment of the present invention; FIG. 6 is a block diagram of a third system in accordance with an embodiment of the present invention; and FIG. 7 illustrates a functional block diagram illustrating a system implemented in accordance with an embodiment of the present invention.

Claims (20)

A processor comprising: at least one sequential pipeline for receiving data prefetch instructions and other instructions; a translation lookaside buffer (TLB) having a number of ports, mapping virtual addresses to physical addresses; data prefetching queues, When an individual virtual address associated with each data prefetch instruction is not found in the TLB, it is used to receive a data prefetch instruction; and a hardware page walker is not found in the TLB. When the data prefetch instruction is used, it is used to access the page table in the memory. The processor of claim 1, wherein the at least one sequential pipeline is an arithmetic logic unit (ALU) pipeline for receiving an ALU instruction and a data prefetch instruction. The processor of claim 1, further comprising: at least one of the second type of sequence pipelines having an issue slots for receiving a plurality of other instructions. The processor of claim 3, wherein, when at least one execution slot of the at least one of the second type sequence pipelines is available, the data prefetch queue sends a data prefetch command to the second The at least one of the type sequence pipelines. The processor of claim 1, wherein when the plurality of instructions simultaneously request the same translation from the hardware paging checker, The hardware page check check is merged into a single page check check. The processor of claim 1, wherein the at least one sequential pipeline is an integer pipeline for receiving an integer instruction and a data prefetch instruction. The processor of claim 3, wherein the at least one of the second type of sequence pipelines is executed when a multi-hardware page check check occurs. A system comprising: one or more processing units, comprising: a first type of sequential pipeline for receiving at least one data prefetching instruction; at least one of the second type of sequential pipelines having a transmitting slot for receiving a plurality of instructions And a data prefetching queue, the data prefetching queue is configured to receive the at least one data prefetching instruction when the translational back buffer does not have an entry associated with the virtual address of the data prefetching instruction, and When at least one execution slot of the at least one of the second type of sequential pipelines is available, the at least one data prefetch command is issued to the at least one of the second type of sequential pipelines. The system of claim 8 further comprising: an additional first type of sequential pipeline, wherein the first type of sequential pipeline is an arithmetic logic unit (ALU) pipeline for receiving ALU instructions and data prefetch instructions. Such as the system of claim 8 of the patent scope, wherein the second category The at least one of the type sequence pipelines includes a memory pipeline. The system of claim 10, further comprising: one or more execution units for executing instructions associated with the execution slot of the memory pipeline. The system of claim 11, further comprising: a software scheduler for utilizing at least one of the one or more firing slots including the second type of sequential pipeline and the at least one data prefetching instruction One or more factors of priority to determine whether to send the at least one data prefetch instruction to the first type of sequential pipeline or to the second type of sequential pipeline. The system of claim 11, wherein the first type of sequential pipeline is an integer pipeline for receiving integer instructions and data prefetch instructions. The system of claim 11, further comprising: a memory coupled to the one or more processing units, wherein the one or more execution units of the memory pipeline transmit an instruction related to the executed instruction Information is given to the memory. A computer-implemented method, comprising: determining whether to send a data prefetching instruction to a first sequential pipeline or to a second sequential pipeline according to availability of one or more transmission slots of a second sequential pipeline; according to one or more factors Receiving, by the first sequence pipeline, the data prefetching instruction; sending the data prefetching instruction to the data prefetching queue; The data prefetch instruction is issued to the second sequential pipeline when at least one execution slot of the second sequential pipeline is available. The computer-implemented method of claim 15, wherein the first type of sequential pipeline is an arithmetic logic unit (ALU) pipeline for receiving an ALU instruction and a data prefetching instruction, wherein the second sequential pipeline memory Body line. The computer-implemented method of claim 15, further comprising: receiving, by the transmitting slot of the second sequential pipeline, a plurality of other instructions, wherein the one or more factors comprise one or more of the second type of sequential pipelines The unavailability of at least one of the launch slots and the priority of the data prefetch command. A machine-accessible medium comprising data, when accessed by a machine, causing the machine to perform operations comprising: deciding whether to issue a data prefetch command based on availability of one or more firing slots of the second type of sequential pipeline a first type of sequential pipeline or sent to the second type of sequential pipeline; receiving the data prefetching instruction in the first sequential pipeline according to one or more factors; sending the data prefetching instruction to the data prefetching queue; When at least one execution slot of the second sequential pipeline is available, the data prefetch command is issued to the second sequential pipeline. The machine-accessible medium of claim 18, wherein the first type of sequential pipeline is an arithmetic logic unit (ALU) pipeline, The ALU instruction and the data prefetch instruction are received, wherein the second sequential pipeline is a memory pipeline. The machine-accessible medium of claim 18, further comprising: receiving, by the transmitting slot of the second sequential pipeline, a plurality of other instructions, wherein the one or more factors comprise one or more of the second type of sequential pipeline The unavailability of at least one of the plurality of firing slots and the priority of the data prefetching instruction.