TWI481034B - Compound semiconductor device and method of manufacturing the same - Google Patents

Description

Compound semiconductor device and method of manufacturing same field

The embodiments described herein relate to a compound semiconductor device and a method of fabricating the same.

background

Nitride semiconductors are characterized by their high saturation electron velocity and wide band gap. Therefore, nitride semiconductors have been extensively studied for the purpose of utilizing these characteristics to apply them to high breakdown voltage, high output compound semiconductor devices. For example, GaN of a nitride semiconductor has a 3.4 eV band gap larger than the band gap of Si (1.1 eV) and GaAs (1.4 eV). Therefore, GaN has a large breakdown electric field strength. Therefore, GaN is highly promising as a material for forming a compound semiconductor device for a power supply device which can operate at a high voltage and which can generate a large output.

There have been many reports on semiconductor devices using the nitride semiconductor, and field-effect transistors are typical, and particularly high electron mobility transistors (HEMT). In a GaN-based HEMT and an AlGaN/GaN-based HEMT, the use of GaN as an electron channel layer and the use of AlGaN as an electron supply layer attracts much attention. In the AlGaN/GaN-based HEMT, lattice distortion occurs in the AlGaN layer due to a difference in lattice constant between AlGaN and GaN. This distortion results in piezoelectric polarization and spontaneous polarization, and thus produces a high density, two-dimensional electron gas (2DEG). Therefore, it is expected that the AlGaN/GaN-based HEMT can be used as a high-efficiency switching device, and High crash voltage power devices for electric vehicles, etc.

However, due to the high density of the two-dimensional electron gas, it is difficult to obtain a normally closed transistor. Therefore, research on various technologies has been directed towards solving this problem. Conventional proposals include a technique for dissipating the two-dimensional electron gas by forming an InAlN layer between the gate electrode and the electron supply layer.

However, if the InAlN layer is formed and extends in a region between the gate electrode and the source electrode in a plan view, and in a region between the gate electrode and the gate electrode, the InAlN The layer also causes the 2DEG to disappear in these areas (access areas) and thus increases the on-resistance. Conventional studies have directed the removal of InAlN layers in the access regions by dry etching. However, dry etching of the InAlN layer in the access regions causes current collapse, and thus it is difficult to obtain a sufficient level of gate current.

[Patent Document 1] Japanese Laid-Open Patent Publication No. 2009-76845

[Patent Document 2] Japanese Laid-Open Patent Publication No. 2007-19309

summary

SUMMARY OF THE INVENTION An object of the present invention is to provide a compound semiconductor device which can realize a normal shutdown operation while suppressing current collapse, and a method of fabricating the same.

According to one aspect of the embodiments, a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed on the substrate; and a gate electrode, a source electrode, and a drain electrode, It is formed on or above the compound semiconductor stack structure. The compound semiconductor stacked structure includes: an electron channel layer; and a nitride semiconductor layer including an electron supply layer formed on the electron channel layer. At the gate The indium (In) fraction of the surface of the nitride semiconductor layer in the region between the pole and the source electrode and in the region between the gate electrode and the gate electrode is proportional to the region below the gate electrode The surface of the nitride semiconductor layer has a low indium (In) fraction.

According to another aspect of the embodiments, a method of fabricating a compound semiconductor device includes: forming a compound semiconductor stacked structure on a substrate; and forming a gate electrode on or over the compound semiconductor stacked structure A source electrode and a drain electrode. The step of forming the compound semiconductor stacked structure further includes: forming an electron channel layer; and forming a nitride semiconductor layer including an electron supply layer on the electron channel layer. In the region between the gate electrode and the source electrode and in the region between the gate electrode and the gate electrode, the surface indium (In) fraction of the nitride semiconductor layer is proportional to the gate The surface of the nitride semiconductor layer in one region below the electrode has a low indium (In) fraction.

Simple illustration

1A is a cross-sectional view showing the structure of a compound semiconductor device according to a first embodiment; FIG. 1B is a graph showing the distribution of indium (In) fraction in an In-containing layer; 2A and 2B; The figure is a diagram showing an example of the function of the In-containing layer; the 3A to 3L are cross-sectional views sequentially showing a method of manufacturing the compound semiconductor device according to the first embodiment; and FIG. 4 is a diagram showing the second embodiment according to a second embodiment. A cross-sectional view showing the structure of a compound semiconductor device; Figure 5 is a cross-sectional view showing the structure of a compound semiconductor device according to a third embodiment; and Figs. 6A to 6E are cross-sectional views showing a method of manufacturing a compound semiconductor device of a fourth embodiment in sequence; 7 is a cross-sectional view showing the structure of a compound semiconductor device according to a fifth embodiment; and FIGS. 8A to 8L are cross-sectional views sequentially showing a method of manufacturing a compound semiconductor device according to the fifth embodiment; 1 is a cross-sectional view showing the structure of a compound semiconductor device according to a sixth embodiment; FIG. 10 is a cross-sectional view showing the structure of a compound semiconductor device according to a seventh embodiment; FIGS. 11A to 11E are The sequence shows a cross-sectional view of a method of manufacturing a compound semiconductor device according to an eighth embodiment; FIG. 12 is a view showing an independent package according to a ninth embodiment; and FIG. 13 is a view showing a tenth implementation according to a tenth embodiment A wiring diagram of a power factor correction (PFC) circuit; FIG. 14 is a wiring diagram showing a power supply device according to an eleventh embodiment; and FIG. 15 is a diagram showing a twelfth High-frequency amplifier wiring diagram of one embodiment; FIG. 16 is a graph showing the results of a first experiment of.

Figure 17 is a graph showing the results of a second experiment.

18A and 18B are cross-sectional views showing a compound semiconductor device of a reference example; and Figs. 19A and 19B are graphs showing the results of a third experiment and a fourth experiment.

Description of the embodiment

Most of the embodiments will be described in detail below with reference to the accompanying drawings.

(First Embodiment)

The first embodiment will be explained below. Fig. 1A is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to the first embodiment.

In the first embodiment, as shown in Fig. 1A, a compound semiconductor stacked structure 7 is formed on a substrate 1 such as a Si substrate. The compound semiconductor stacked structure 7 includes an initial layer 2a, a buffer layer 2b, an electron channel layer 3, a spacer layer 4, an electron supply layer 5, and an In-containing layer 6. For example, the initial layer 2a may be an AlN layer of about 160 nm thick. For example, the buffer layer 2b may be a stacked layer of a plurality of Al _x Ga _1-x N (0.2<x<0.8) layers, and the stacked layer has a side gradually decreasing from the side of the initial layer 2a toward the side of the electron channel layer 3. Al rate. For example, the buffer layer 2b may have a thickness of about 500 nm. For example, the electron channel layer 3 may be an i-GaN layer which is not intentionally doped with an impurity of about 1 μm thick. For example, the spacer layer 4 may be an i-Al _0.2 Ga _0.8 N layer which is not intentionally doped with an impurity of about 5 nm thick. The electron supply layer 5 may be, for example, an n-type Al _0.2 Ga _0.8 N layer of about 20 nm thick. For example, the electron supply layer 5 may be doped with about 5 × 10 ¹⁸ /cm ³ of Si as an n-type impurity. For example, the In-containing layer 6 may be an InAlN layer of about 10 nm thick. The spacer layer 4, the electron supply layer 5, and the In-containing layer 6 are examples of the nitride semiconductor layer.

One element isolation region 20 defining one element region is formed in the compound semiconductor stacked structure 7. In the element region, a source electrode 11s and a drain electrode 11d are formed on the In-containing layer 6. An insulating film 12 is formed to cover the source electrode 11s and the drain electrode 11d on the In-containing layer 6. An opening 13g is formed in the insulating film 12 at a position between the source electrode 11s and the gate electrode 11d in a plan view, and a gate electrode 11g is formed in the opening 13g. An insulating film 14 is formed to cover the gate electrode 11g on the insulating film 12. Although the material for the insulating films 12 and 14 is not particularly limited, for example, a Si nitride film can be used. These insulating films 12 and 14 are examples of the terminating film.

The In-containing layer 6 includes an In exclusion region 6a. The In exclusion region 6a is in the surface portion of the In-containing layer 6 except for a region overlapping the gate electrode 11g in plan view. The In fraction in the region containing the In layer 6 other than the In exclusion region 6a is substantially fixed as will be described later, and the In fraction (In composition) in the In exclusion region 6a is on the surface. (to the shallow portion of the In exclusion region 6a) is reduced as shown in Fig. 1B.

Here, the composition of the In-containing layer 6 and the In exclusion region 6a will be explained. In this embodiment, if the In layer 6 is not contained, 2DEG will appear on the surface portion of the electron channel layer 3 due to the difference in lattice constant between the GaN of the electron channel layer 3 and the AlGaN of the electron supply layer 5. In the share. On the other hand, if the In-containing layer 6 is present on the electron supply layer 5, the 2DEG disappears depending on the components. This embodiment employs an area that can be placed under the gate electrode 11g. Most of the components in which 2DEG disappears (for example, In fraction: 0.35 to 0.40).

Therefore, the 2DEG hardly exists under the gate electrode 11g, and this can cause a normal off operation in this embodiment. On the other hand, since the In fraction of the In exclusion region 6a is not high enough for most of the 2DEG to disappear, the 2DEG having a sufficient concentration value exists in a region below the In exclusion region 6a in the plan view, or In an access area. Therefore, the on-resistance can be suppressed to a low value. Further, for example, the In exclusion region 6a may be formed by annealing as described later in detail, and dry etching is not required. It is possible to avoid the current collapse caused by damage in the dry etching process.

Further, since the composition of the In exclusion region 6a is closer to AlN than the composition of the remaining region containing the In layer 6, the In exclusion region 6a has a large band gap as shown in Fig. 2A. Therefore, as shown in FIG. 2B, a pair of higher Schottky barriers of the gate electrode 11g are formed as compared with the case where the In exclusion region 6a is not present, and thus electron (leakage current) lateral injection can be suppressed. Surface part. Although electron injection into the surface portion changes the charging of the wells and can cause operation instability and is represented by current collapse, this embodiment can suppress this inconsistency.

As described above, excellent characteristics can be obtained by this embodiment.

Hereinafter, a method of manufacturing a GaN-based HEMT (compound semiconductor device) according to the first embodiment will be described. 3A to 3L are cross-sectional views sequentially showing a method of manufacturing a GaN-based HEMT (Compound Semiconductor Device) according to the first embodiment.

First, as shown in Fig. 3A, the compound semiconductor stacked structure 7 is formed on the substrate 1. In the process of forming the compound semiconductor stacked structure 7, the initial layer 2a, the buffer layer 2b, and the like may be formed by a crystal growth process such as metal organic vapor phase epitaxy (MOVPE) and molecular beam epitaxy (MBE). The electron channel layer 3, the spacer layer 4, the electron supply layer 5, and the In-containing layer 6. In the process of forming the AlN layer, the AlGaN layer, and the GaN layer by MOVPE, a trimethylaluminum (TMA) gas as an Al source, a trimethylgallium (TMG) gas as a Ga source, and A mixed gas of ammonia (NH ₃ ) gas as an N source. In this procedure, the on/off and the flow rate of the supply of the trimethylaluminum gas and the trimethylgallium gas are appropriately set depending on the components of the compound semiconductor layer to be grown. The flow rate of ammonia gas used for all of the compound semiconductor layers is set to be about 100 ccm to 10 Lm. For example, the growth pressure can be adjusted to about 50 Torr to 300 Torr, and the growth temperature can be adjusted to about 1000 ° C to 1200 ° C. For example, in the process of growing the n-type compound semiconductor layers, Si may be doped into the compound semiconductor layers by adding a mixed gas containing Si in a predetermined flow rate by adding SiH ₄ gas containing Si. The dose of Si is adjusted to be about 1 × 10 ¹⁸ /cm ³ to 1 × 10 ²⁰ /cm ³ and is, for example, about 5 × 10 ¹⁸ /cm ³ . In the process of forming the InAlN layer, trimethylaluminum (TMA) gas as an Al source, trimethylindium (TMI) gas as an In source, and ammonia (NH ₃ ) gas as an N source can be used. A mixed gas. In this procedure, for example, the growth pressure can be adjusted to about 50 Torr to 200 Torr, and the growth temperature can be adjusted to about 650 ° C to 800 ° C.

Next, as shown in FIG. 3B, an element isolation region 20 defining an element region is formed in the compound semiconductor stacked structure 7. In the process of forming the element isolation region 20, for example, a photoresist pattern is formed on the compound semiconductor stacked structure 7 to selectively expose the element isolation region 20 to be formed. The region is implanted with ions such as Ar ions through a photoresist pattern used as a mask. Alternatively, the compound semiconductor stacked structure 7 may be etched by dry etching using a chlorine-containing gas through a photoresist pattern used as an etch mask.

Then, as shown in Fig. 3C, a tantalum nitride film 21 is formed on the entire surface. The tantalum nitride film 21 is formed by, for example, a plasma enhanced chemical vapor deposition (CVD) process and is about 100 nm thick. Alternatively, after the formation of the In-containing layer 6, the tantalum nitride film 21 may be formed before the element isolation region 20 is formed. In this case, for example, SiH ₄ gas can be used as a source gas, and the grown tantalum nitride film 21 is about 10 nm thick.

Next, as shown in FIG. 3D, a photoresist is applied and then patterned to thereby form a resist pattern 22 to cover a region where the gate electrode is to be formed, and the remaining region is exposed.

Next, as shown in FIG. 3E, the tantalum nitride film 21 is etched by using the resist pattern 22 as an etch mask and wet etching using a HF-based solution. Therefore, the surface of the In-containing layer 6 is exposed in the access region of the GaN-based HEMT. The resist pattern 22 is then removed.

Annealing is then performed in a non-oxidizing environment to thereby exclude indium (In) from the surface portion of the In-containing layer 6. Therefore, as shown in Fig. 3F, the In exclusion region 6a having a low In division is formed in the surface portion of the In-containing layer 6 (see Fig. 1B). The gas which can be used to constitute the non-oxidizing environment is not particularly limited and includes N ₂ gas, H ₂ gas, or a mixed gas of N ₂ gas and H ₂ gas. Although the temperature of the annealing is not particularly limited, it is preferably adjusted to about 700 ° C to 800 ° C, and to, for example, about 750 ° C. When the In exclusion region 6a is formed, a high concentration 2DEG appears in the surface portion of the electron channel layer 3 below the In exclusion region 6a.

Next, as shown in FIG. 3G, the source electrode 11s and the drain electrode 11d are formed on the In-containing layer 6. The source electrode 11s and the drain electrode 11d can be formed by, for example, a lift-off procedure. More specifically, a photoresist pattern is formed to expose a region where the source electrode 11s and the gate electrode 11d are to be formed, and is simultaneously used by an evaporation process, for example, the photoresist pattern is used as a growth mask. A metal film is formed on the entire surface, and then the photoresist pattern is removed together with a portion of the metal film deposited on the photoresist pattern. In the process of forming the metal film, for example, a Ti film of about 100 nm thick may be formed, and then an Al film of about 300 nm thick may be formed. Next, the metal films are annealed (for example, by rapid thermal annealing (RTA)) at 400 ° C to 1000 ° C (for example, at 600 ° C) in an N ₂ gas atmosphere to form ohmic characteristics.

Then, as shown in FIG. 3H, the tantalum nitride film 21 is removed by wet etching. Next, as shown in Fig. 3I, the insulating film 12 is formed on the entire surface. The insulating film 12 is preferably formed, for example, by atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (CVD), or sputtering.

Next, as shown in FIG. 3J, the opening 13g is formed in the insulating film 12 at a position between the source electrode 11s and the gate electrode 11d in plan view. In this procedure, for example, the In-containing layer 6 in which no In exclusion region 6a is formed may overlap the opening 13g in a plan view.

Next, as shown in FIG. 3K, the gate electrode 11g is formed in the opening 13g. The gate electrode 11g can be formed by, for example, a lift-off procedure. More specifically, a photoresist pattern is formed to expose the gate electrode 11g to be formed. a region which is simultaneously used by an evaporation process, for example, the photoresist pattern is formed as a growth mask to form a metal film on the entire surface, and then removed together with a portion of the metal film deposited on the photoresist pattern The photoresist pattern. In the process of forming the metal film, for example, a Ni film of about 50 nm thick may be formed, and then an Au film of about 300 nm thick may be formed. Next, as shown in FIG. 3L, the insulating film 14 is formed over the insulating film 12 to cover the gate electrode 11g.

Therefore, a GaN-based HEMT according to the first embodiment can be manufactured.

(Second embodiment)

Hereinafter, a second embodiment will be explained. Fig. 4 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to a second embodiment.

Unlike the first embodiment in which the gate electrode 11g is in Schottky contact with the compound semiconductor stacked structure 7, the second embodiment employs the insulating film 12 between the gate electrode 11g and the compound semiconductor stacked structure 7, The insulating film 12 is used as a gate insulating film. In short, the opening 13g is not formed in the insulating film 12, and a MIS type structure is employed.

Further, in the second embodiment thus constituted, in the case where the In exclusion region 6a is present, similarly to the first embodiment, the effect of suppressing the current collapse is successfully achieved while achieving the normal off operation.

The material for the insulating film 12 is not particularly limited, and preferred examples thereof include oxides, nitrides or oxynitrides of Si, Al, Hf, Zr, Ti, Ta and W. Particularly desirable is alumina. The insulating film 12 may have a thickness of 2 nm to 200 nm and is, for example, about 10 nm.

(Third embodiment)

A third embodiment will be described below. Fig. 5 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to a third embodiment.

Unlike the first embodiment in which the source electrode 11s and the drain electrode 11d are formed in the In-containing layer 6, in the third embodiment, the recesses 10s and 10d are formed on the In-containing layer 6, and the source The pole electrode 11s and the drain electrode 11d are formed in the recesses 10s and 10d, respectively.

Further, in the third embodiment thus constituted, in the case where the In exclusion region 6a is present, similarly to the first embodiment, the effect of suppressing the current collapse is successfully achieved while achieving the normal off operation.

The compound semiconductor device according to the third embodiment can be manufactured by the following steps. After the In exclusion region 6a is formed (Fig. 3F), and before the source electrode 11s and the gate electrode 11d are formed (Fig. 3G), the recesses 10s and 10d are formed. Next, the source electrode 11s and the drain electrode 11d are formed in the recesses 10s and 10d, respectively. In the process of forming the recesses 10s and 10d, for example, a photoresist pattern is formed on the compound semiconductor stacked structure 7 to selectively expose a region where the recesses 10s and 10d are to be formed, and by using a chlorine-containing Gas dry etching etches the In-containing layer 6 through a photoresist pattern used as an etch mask. Alternatively, a structure similar to that of the third embodiment can be obtained by a method of one of the fourth embodiments described below.

(Fourth embodiment)

Hereinafter, a fourth embodiment will be explained. 6A to 6E are diagrams showing a GaN-based HEMT (compound semiconductor) according to the fourth embodiment in order A cross-sectional view of one of the methods of the device.

In this embodiment, first, a procedure similar to the first embodiment (Fig. 3E) until wet etching (patterning) of the tantalum nitride film 21 and removal of the resist pattern 22 is performed. Next, as shown in FIG. 6A, the recesses 10s and 10d are formed in the In-containing layer 6. Then, as shown in FIG. 6B, the source electrode 11s and the drain electrode 11d are formed in the recesses 10s and 10d, respectively.

Next, for example, annealing (for example, RTA) is performed at 400 ° C to 1000 ° C (for example, 600 ° C) in a nitrogen atmosphere to thereby generate ohmic characteristics, and indium (In) is made from the surface of the In-containing layer 6 Partially excluded. Therefore, as shown in Fig. 6C, an In exclusion region 6a having a lower indium fraction is formed in the surface portion of the In-containing layer 6. In short, in this embodiment, the annealing for generating the ohmic characteristics is also effective for forming the In exclusion region 6a.

Next, as shown in FIG. 6D, the tantalum nitride film 21 is removed by wet etching. Then, a procedure including the formation of the insulating film 12 to the formation of the insulating film 14 is performed similarly to the first embodiment, as shown in Fig. 6E.

According to the fourth embodiment, the number of annealings can be less than the number of annealings in the first embodiment.

(Fifth Embodiment)

The fifth embodiment will be described below. Fig. 7 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to a fifth embodiment.

In the fifth embodiment, as shown in Fig. 7, a compound semiconductor stacked structure 37 is formed on a substrate 31 such as a Si substrate. The compound semiconductor stacked structure 37 includes an initial layer 32a, a buffer layer 32b, an electron channel layer 33 and an In-containing layer 36. For example, the initial layer 32a can be an AlN layer approximately 160 nm thick. For example, the buffer layer 32b may be a stacked layer of a plurality of Al _x Ga _1-x N (0.2<x<0.8) layers, and the stacked layer has a side gradually decreasing from the side of the initial layer 32a toward the side of the electron channel layer 33. Al rate. For example, the buffer layer 32b may have a thickness of about 500 nm. For example, the electron channel layer 33 may be an i-GaN layer or an I-AlGaN layer which is not intentionally doped with an impurity of about 1 μm thick. For example, the In-containing layer 6 may be an InAlN layer of about 10 nm thick. The In-containing layer 6 is an example of the nitride semiconductor layer.

An element isolation region 20 defining one element region is formed in the compound semiconductor stacked structure 37. In the element region, the source electrode 11s and the drain electrode 11d are formed on the In-containing layer 36. The insulating film 12 is formed to cover the source electrode 11s and the drain electrode 11d on the In-containing layer 36. An opening 13g is formed in the insulating film 12 at a position between the source electrode 11s and the gate electrode 11d in a plan view, and the gate electrode 11g is formed in the opening 13g. The insulating film 14 is formed to cover the gate electrode 11g on the insulating film 12. Although the material for the insulating films 12 and 14 is not particularly limited, for example, a Si nitride film can be used. These insulating films 12 and 14 are examples of the terminating film.

The In-containing layer 36 includes an In exclusion region 36a. The In exclusion region 36a is in the surface portion of the In-containing layer 36 except for a region overlapping the gate electrode 11g in plan view. The In fraction in the region containing the In layer 36 other than the In exclusion region 36a is substantially fixed as will be described later, and is similar to the In exclusion region 6a in the first embodiment, and is excluded in the In The In fraction (In composition) in the region 36a is toward the surface (to the In exclusion region 36a) The shallower part is reduced.

Here, the composition of the In-containing layer 36 and the In exclusion region 36a will be explained. In this embodiment, the composition of the In-containing layer 36 can be determined so as to be between the GaN of the electron channel layer 33 and the lattice constant of the InAlN (for example, In fraction: 0.30) of the In-containing layer 36. The relationship suppressing 2DEG is generated in a region where the In exclusion region 36a does not exist in a plan view, or in a surface portion of the electron channel layer 33 in a region below the gate electrode 11g.

Therefore, the 2DEG hardly exists under the gate electrode 11g, and this can cause a normal off operation in this embodiment. On the other hand, since the In fraction of the In exclusion region 36a is not high enough to suppress the 2DEG generation, the 2DEG having a sufficient concentration value exists in a region below the In exclusion region 36a in the plan view, or in an access. In the district. In other words, in this embodiment, the In exclusion region 36a serves as the electron supply layer. Therefore, the on-resistance can be suppressed to a low value. Further, for example, the In exclusion region 36a may be formed by annealing as described in detail later, and dry etching is not required. It is possible to avoid the current collapse caused by damage in the dry etching process. Further, by suppressing electron injection similarly to the first embodiment, operational instability due to electron injection can be suppressed.

Further, the number of nitride semiconductor layers in the fifth embodiment is smaller than that in the first embodiment. In other words, the number of interfaces between different materials is small. The larger the number of interfaces, the larger the number of well steps that make the operation unstable. According to the fifth embodiment, a more stable operation can be obtained as compared with the first embodiment. Another advantage of this fifth embodiment is that the number of times a large change in growth conditions under micro-control can be reduced at each interface between different materials.

As described above, excellent characteristics can be obtained by this embodiment.

Hereinafter, a method of manufacturing a GaN-based high electron mobility transistor (compound semiconductor device) according to the fifth embodiment will be described. 8A to 8L are cross-sectional views sequentially showing a method of a GaN-based high electron mobility transistor (compound semiconductor device) according to the fifth embodiment.

First, as shown in Fig. 8A, the compound semiconductor stacked structure 37 is formed on the substrate 31. In the process of forming the compound semiconductor stacked structure 37, the initial layer 32a, the buffer layer 32b, the electron channel layer 33, and the In-containing layer 36 may be formed by crystal growth of, for example, MOVPE or MBE. These growth conditions may be similar to those of the initial layer 2a, the buffer layer 2b, the electron channel layer 3, and the In-containing layer 6 used in the first embodiment except for the components for forming the mixed gas containing the In layer 36.

Next, as shown in FIGS. 8B to 8D, an element region is defined in the compound semiconductor stacked structure 37, the tantalum nitride film 21 is formed on the entire surface, and the resist pattern 22 is formed so as to cover the gate to be formed. One of the electrodes is exposed and the remaining area is exposed. Then, as shown in Fig. 8E, similar to the first embodiment, the tantalum nitride film 21 is etched by wet etching using a HF-based solution through the resist pattern 22 used as an etch mask. . Therefore, the surface of the In-containing layer 36 is exposed in a portion thereof corresponding to the access region of the GaN-based HEMT. The resist pattern 22 is then removed.

Next, similar to the first embodiment, annealing is performed in a non-oxidizing environment to thereby exclude indium (In) from the surface portion of the In-containing layer 36. Therefore, as shown in Fig. 8F, an In exclusion region 36a having a lower In fraction is formed in the surface portion of the In-containing layer 36. When the In exclusion area 36a is formed, a high concentration The degree 2DEG appears in the surface portion of the electron channel layer 33 below the In exclusion region 36a.

Next, as shown in FIGS. 8G to 8I, similarly to the first embodiment, the source electrode 11s and the drain electrode 11d are formed, annealed to generate ohmic characteristics, and the nitridation is removed by wet etching. The ruthenium film 21 is formed, and the insulating film 12 is formed.

Next, as shown in Figs. 8J to 8L, similarly to the first embodiment, the opening 13g is formed, the gate electrode 11g is formed, and then the insulating film 14 is formed.

Therefore, the compound semiconductor device according to the fifth embodiment can be manufactured.

(Sixth embodiment)

The sixth embodiment will be described below. Fig. 9 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to a sixth embodiment.

Unlike the fifth embodiment in which the gate electrode 11g is in Schottky contact with the compound semiconductor stacked structure 37, similarly to the second embodiment, the sixth embodiment is in the gate electrode 11g and the compound semiconductor stacked structure 37. The insulating film 12 is used to allow the insulating film 12 to function as a gate insulating film. In short, the opening 13g is not formed in the insulating film 12, and a MIS type structure is employed.

Further, in the sixth embodiment thus constituted, in the case where the In exclusion region 36a is present, similarly to the second embodiment, the effect of suppressing the current collapse is successfully achieved while achieving the normal off operation.

The material used for the insulating film 12 is not particularly limited, and a preferred embodiment thereof is included. An oxide, a nitride or an oxynitride of Si, Al, Hf, Zr, Ti, Ta, and W. Particularly desirable is alumina. The insulating film 12 may have a thickness of 2 nm to 200 nm and is, for example, about 10 nm.

(Seventh embodiment)

A seventh embodiment will be described below. Fig. 10 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to a seventh embodiment.

Unlike the fifth embodiment in which the source electrode 11s and the drain electrode 11d are formed in the In-containing layer 36, similarly to the third embodiment, the recesses 10s and 10d are formed in the flat portion in the seventh embodiment. On the In layer 36, the source electrode 11s and the drain electrode 11d are formed in the recesses 10s and 10d in the third embodiment, respectively.

Further, in the seventh embodiment thus constituted, in the case where the In exclusion region 36a is present, similarly to the sixth embodiment, the effect of suppressing the current collapse is successfully achieved while the normal off operation is realized.

Similar to the third embodiment, the compound semiconductor device according to the seventh embodiment can be manufactured by the following steps. After the formation of the In exclusion region 36a (Fig. 8F), and before the formation of the source electrode 11s and the gate electrode 11d (Fig. 8G), the recesses 10s and 10d are formed. The source electrode 11s and the drain electrode 11d are formed in the recesses 10s and 10d, respectively. Alternatively, a structure similar to that of the seventh embodiment can be obtained by a method of one of the eighth embodiments described below.

(Eighth embodiment)

Hereinafter, an eighth embodiment will be explained. Figures 11A through 11E are based on The cross-sectional view showing a method of one of GaN-based HEMTs (compound semiconductor devices) according to the eighth embodiment is shown.

In this embodiment, first, a procedure similar to the fifth embodiment (Fig. 8E) until wet etching (patterning) of the tantalum nitride film 21 and removal of the resist pattern 22 is performed. Next, as shown in FIG. 11A, the recesses 10s and 10d are formed in the In-containing layer 36. Then, as shown in FIG. 11B, the source electrode 11s and the drain electrode 11d are formed in the recesses 10s and 10d, respectively.

Next, for example, annealing (for example, RTA) is performed at 400 ° C to 1000 ° C (for example, 600 ° C) in an N ₂ gas atmosphere to thereby generate ohmic characteristics, and indium (In) is made from the In-containing layer 36. The surface is partially excluded. Therefore, as shown in Fig. 11C, an In exclusion region 36a having a lower indium fraction is formed in the surface portion of the In-containing layer 36. In short, in this embodiment, similar to the fourth embodiment, the annealing for generating the ohmic characteristics is also effective for forming the In exclusion region 36a.

Next, as shown in FIG. 11D, the tantalum nitride film 21 is removed by wet etching. Then, a procedure including the formation of the insulating film 12 to the formation of the insulating film 14 is performed similarly to the fifth embodiment, as shown in Fig. 11E.

According to the eighth embodiment, the number of annealings can be less than the number of annealings in the fifth embodiment.

(Ninth embodiment)

A ninth embodiment relates to an individual package of a compound semiconductor device including a GaN-based HEMT. Fig. 12 is a view showing a stand-alone package according to the ninth embodiment.

In the ninth embodiment, as shown in FIG. 12, according to the first to eighth real One of the back side of the HEMT wafer 210 of one of the compound semiconductor devices of any of the embodiments is fixed to a pad 233 (die pad) using a die attaching agent 234 such as solder. For example, one end of one line 235d of an Al wire is bonded to a drain pad 226d connected to the drain electrode 11d, and the other end of the line 235d is bonded to a drain lead 232d integrally coupled with the pad 233. For example, one end of one line 235s of an Al line is bonded to a source pad 226s connected to the source electrode 11s, and the other end of the line 235s is joined to a source lead 232s separated from the pad 233. For example, one end of a line 235g of an Al wire is bonded to a gate pad 226g connected to the gate electrode 11g, and the other end of the wire 235g is joined to a gate lead 232g separated from the pad 233. The pad 233, the HEMT wafer 210, and the like are packaged by a molding resin 231 such that a portion of the gate lead 232g, a portion of the drain lead 232d, and a portion of the source lead 232s Outwardly protruding.

The individual package can be manufactured, for example, by the following steps. First, the HEMT wafer 210 is bonded to a lead frame pad 233 using a die attach 234 such as solder. Then, the gate pads 226g are connected to the gate leads 232g of the lead frame by wire bonding, and the gate pads 226d are connected to the gate leads 232d of the lead frame by using the wires 235g, 235d, and 235s, respectively. The source pad 226s is connected to the source lead 232s of the lead frame. Subsequent molding of the molded resin 231 is carried out by a transfer molding process. The lead frame is then cut.

(Tenth embodiment)

Hereinafter, a tenth embodiment will be explained. The tenth embodiment relates to a PFC (Power Factor Correction) circuit, and the PFC circuit is provided with one A compound semiconductor device of one of GaN-based HEMTs. Figure 13 is a wiring diagram showing a PFC circuit according to a tenth embodiment.

The PFC circuit 250 includes a switching element (transistor) 251, a diode 252, a choke coil 253, capacitors 254 and 255, a diode bridge 256, and an AC power source (AC) 257. The drain electrode of the switching element 251, the anode terminal of the diode 252, and one terminal of the choke coil 253 are connected to each other. A source electrode of the switching element 251, a terminal of the capacitor 254, and a terminal of the capacitor 255 are connected to each other. The other terminal of the capacitor 254 and the other terminal of the choke coil 253 are connected to each other. The other terminal of the capacitor 255 and the cathode terminal of the diode 252 are connected to each other. A gate driver is coupled to the gate electrode of the switching element 251. The AC 257 is connected between the two terminals of the capacitor 254 through the diode bridge 256. A DC power source (DC) is connected between the two terminals of the capacitor 255. In this embodiment, the compound semiconductor device according to any of the first to eighth embodiments is used as the switching element 251.

In the process of manufacturing the PFC circuit 250, for example, the switching element 251 is connected to the diode 252, the choke coil 253, and the like by, for example, solder.

(Eleventh Embodiment)

Hereinafter, an eleventh embodiment will be explained. The eleventh embodiment relates to a power supply device, and the power supply device is provided with a compound semiconductor device including a GaN-based HEMT. Fig. 14 is a wiring diagram showing a power supply device according to the eleventh embodiment.

The power supply device includes a high voltage primary side circuit 261, a low voltage secondary side circuit 262, and a primary side circuit 261 and the second Transformer 263 between side circuits 262.

The primary side circuit 261 includes a PFC circuit 250 according to the tenth embodiment, and an inverting circuit connected between the two terminals of the capacitor 255 of the PFC circuit 250. The inverting circuit can be, for example, a full bridge. Inverter circuit 260. The full bridge inverter circuit 260 includes a plurality of (four in this example) switching elements 264a, 264b, 264c, and 264d.

The secondary side circuit 262 includes a plurality of (three in this example) switching elements 265a, 265b, and 265c.

In this embodiment, the compound semiconductor device according to any one of the first to eighth embodiments is used for the switching element 251 of the PFC circuit 250, and the switching element 264a of the full-bridge inverter circuit 260, 264b, 264c and 264d are used. The PFC circuit 250 and the full bridge inverter circuit 260 are components of the primary side circuit 261. On the other hand, a general MIS-FET (Field Effect Transistor) based on erbium is used for the switching elements 265a, 265b, and 265c of the secondary side circuit 262.

(Twelfth Embodiment)

Hereinafter, a twelfth embodiment will be explained. The twelfth embodiment relates to a high frequency amplifier, and the high frequency amplifier is provided with a compound semiconductor device including a GaN-based HEMT. Fig. 15 is a wiring diagram showing a high frequency amplifier according to a twelfth embodiment.

The high frequency amplifier includes a digital predistortion circuit 271, mixers 272a and 272b, and a power amplifier 273.

The digital predistortion circuit 271 compensates for non-linear distortion of the input signal. The mixer 272a mixes the input signal of the non-linear distortion that has been compensated with AC signal. The power amplifier 273 includes the compound semiconductor device according to any of the first to eighth embodiments, and amplifies an input signal mixed with an AC signal. In the illustrated example of this embodiment, the signal on the output side can be mixed with an AC signal by the mixer 272b at the time of switching and sent back to the digital predistortion circuit 271.

The composition of the compound semiconductor layer used for the compound semiconductor stacked structure is not particularly limited, and GaN, AlN, InN, or the like can be used. Further, a mixed crystal of GaN, AlN, InN or the like can also be used. The nitride semiconductor layer containing the In-containing layer is not particularly limited to InAlN, and may be In _x Al _y Ga _1-xy N (0<x) 1,0 y<1,x+y 1) Wait.

The configuration of the gate electrode, the source electrode, and the drain electrode is not limited to those described in the above embodiments. For example, they can be composed of a single layer. The method of forming these electrodes is not limited to this stripping procedure. Annealing may be omitted after forming the source electrode and the drain electrode, as long as the ohmic characteristic is obtained. The gate electrode can be annealed.

The configuration of the gate electrode, the source electrode, and the drain electrode is not limited to those described in the above embodiments. For example, they can be composed of a single layer. The method of forming these electrodes is not limited to this stripping procedure. Annealing may be omitted after forming the source electrode and the drain electrode, as long as the ohmic characteristic is obtained. The gate electrode can be annealed.

The substrate may be a tantalum carbide (SiC) substrate, a sapphire substrate, a tantalum substrate, a GaN substrate, a GaAs substrate, or the like. The substrate can be any of electrically conductive, semi-insulating and insulating substrates. In consideration of cost, a Si substrate (for example, a Si substrate having a (111) plane), a SiC substrate or a blue color is used. A gemstone substrate is preferred. Further, the thicknesses and materials used to form the individual layers are not limited to those described in the embodiments.

Hereinafter, experiments conducted by the present inventors and the like will be described.

(first experiment)

In a first experiment, an In _0.4 Al _0.6 N was formed, followed by annealing at various temperatures, and the In fraction was measured after annealing. The annealing was carried out for 10 minutes in an N ₂ atmosphere. The results are shown in Figure 16.

The In fraction is strongly determined by the annealing temperature, and the most effective In exclusion occurs at 700 ° C to 800 ° C, as shown in FIG.

(second experiment)

In a second experiment, the compound semiconductor devices were fabricated similarly to the fifth embodiment, but varying the annealing temperature and obtaining a relationship between the annealing temperature and the maximum drain current. The results are shown in Figure 17.

As the annealing temperature increases, the access resistance decreases and the maximum drain current increases, as shown in FIG. This is because the higher the annealing temperature, the more significant the In exclusion and the lower the In fraction, and the lower the In fraction, the stronger the spontaneous polarization and piezoelectric polarization and the more pronounced phenomenon of the 2DEG.

(third experiment)

In a third experiment, the relationship between the gate voltage and the drain current was obtained for the fifth embodiment and a first reference example shown in Fig. 18A. The results are shown in Figure 19A. Note that the first reference example includes an In-containing layer 136 not including the In exclusion region 36a, instead of the In-containing layer 36 of the fifth embodiment.

In the case where the In-containing layer 36 is present, the fifth embodiment has a low access resistance and a high maximum gate current as shown in Fig. 19A. In addition, when accessing the resistor When reduced, the controllability (crosslinking gm) of the gate electrode increases. It will thus be appreciated that the fifth embodiment successfully produces the effect of improving gate control and increasing maximum drain current.

(fourth experiment)

In a fourth experiment, for the fifth embodiment and a second reference example shown in FIG. 18B, the gate voltage V is obtained after being pressurized by applying a high bias voltage to the drain electrode 11d. The relationship between _DS and the drain current. In other words, this experiment is about studying the extent of current collapse. The results are shown in Figure 19B. Note that the second reference example includes an In-containing layer 106 which does not include the In exclusion region 6a and which has been subjected to dry etching to produce 2DEG, in place of the In-containing layer 6 of the first embodiment.

Compared with the second reference example, the current collapse of the fifth embodiment is greatly reduced as shown in Fig. 19B. This can be attributed mainly to three factors.

First, in the second reference example, since the dry etching is performed to remove the In-containing layer 106, a lot of damage is left in the access region. Therefore, there are many well steps that cause a current collapse, and thus the drain current is greatly reduced under a large bias load applied to the drain electrode. On the contrary, since the In-containing layer 36 is not removed by dry etching, the fifth embodiment does not become an etching failure which causes a well order. This is the reason for suppressing the collapse of this current.

Second, the second reference example has an interface between InAlN and AlGaN. In the growth process of these nitride semiconductor layers, since the growth conditions largely change at the interface, many well steps may be generated. In contrast, the fifth embodiment has no interface between InAlN and AlGaN, so that the number of well steps which cause a current collapse is small, and thus the current collapse is successfully suppressed.

Third, the In fraction in the surface portion including the In layer 6 including the In exclusion region 6a is lower than the In fraction in the In-containing layer 106. The fifth embodiment thus has a large band gap of the semiconductor layer in contact with the gate electrode 11g, and the Schottky barrier of the gate electrode 11g is increased. Therefore, leakage current comparison does not flow from the gate electrode 11g to the surface, and thus it is possible to suppress the portion of the electron injecting surface which may be a cause of current collapse.

According to the above compound semiconductor device or the like, in the case where a nitride semiconductor layer having an appropriately adjusted In fraction and formed over the electron channel layer exists, normal off operation can be achieved while suppressing current collapse.

1‧‧‧Substrate

2a‧‧‧ initial layer

2b‧‧‧buffer layer

3‧‧‧Electronic channel layer

4‧‧‧Separation layer

5‧‧‧Electronic supply layer

6‧‧‧Including layer

6a‧‧‧In exclusion area

7‧‧‧ compound semiconductor stack structure

10s, 10d‧‧‧ recess

11d‧‧‧汲electrode

11g‧‧‧gate electrode

11s‧‧‧ source electrode

12‧‧‧Insulation film

13g‧‧‧ openings

14‧‧‧Insulation film

20‧‧‧Component isolation area

21‧‧‧ nitride film

22‧‧‧resist pattern

31‧‧‧Substrate

32a‧‧‧ initial layer

32b‧‧‧buffer layer

33‧‧‧Electronic channel layer

36‧‧‧Including layer

36a‧‧‧In exclusion area

37‧‧‧ compound semiconductor stack structure

106‧‧‧Including layer

136‧‧‧Including layer

210‧‧‧HEMT chip

226d‧‧‧汲pad

226g‧‧‧gate pad

226s‧‧‧Source pad

231‧‧‧Molded resin

232d‧‧‧bend lead

232g‧‧‧gate lead

232s‧‧‧Source lead

233‧‧‧ solder pads (die pads)

234‧‧‧Grain Attachment

235d, 235g, 235s‧‧ lines

250‧‧‧PFC circuit

251‧‧‧Switching elements (transistors)

252‧‧‧ diode

253‧‧‧ Choke coil

254, 255 ‧ ‧ capacitor

256‧‧‧ diode bridge

257‧‧‧AC power supply (AC)

260‧‧‧Full-bridge inverter circuit

261‧‧‧primary circuit

262‧‧‧secondary circuit

263‧‧‧Transformer

264a, 264b, 264c, 264d‧‧‧ switch components

265a, 265b, 265c‧‧‧ switching elements

271‧‧‧Digital predistortion circuit

272a, 272b‧‧‧ Mixer

273‧‧‧Power Amplifier

1A is a cross-sectional view showing the structure of a compound semiconductor device according to a first embodiment; FIG. 1B is a graph showing the distribution of indium (In) fraction in an In-containing layer; 2A and 2B; The figure is a diagram showing an example of the function of the In-containing layer; the 3A to 3L are cross-sectional views sequentially showing a method of manufacturing the compound semiconductor device according to the first embodiment; and FIG. 4 is a diagram showing the second embodiment according to a second embodiment. A cross-sectional view showing the structure of a compound semiconductor device according to an example; FIG. 5 is a cross-sectional view showing the structure of a compound semiconductor device according to a third embodiment; and FIGS. 6A to 6E are sequential views showing the manufacture of a fourth embodiment. A cross-sectional view of one of the methods of the compound semiconductor device; FIG. 7 is a view showing a compound semiconductor package according to a fifth embodiment A cross-sectional view of a structure of the structure; 8A to 8L are sequential cross-sectional views showing a method of manufacturing a compound semiconductor device according to the fifth embodiment; and FIG. 9 is a view showing a compound semiconductor device according to a sixth embodiment. FIG. 10 is a cross-sectional view showing the structure of a compound semiconductor device according to a seventh embodiment; and FIGS. 11A to 11E are sequential views showing the manufacture of a compound semiconductor device according to an eighth embodiment. A cross-sectional view of a method; FIG. 12 is a view showing a single package according to a ninth embodiment; and FIG. 13 is a wiring diagram showing a power factor correction (PFC) circuit according to a tenth embodiment; Figure 14 is a wiring diagram showing a power supply device according to an eleventh embodiment; Figure 15 is a wiring diagram showing a high-frequency amplifier according to a twelfth embodiment; and Figure 16 is a first A chart of the results of the experiment.

Figure 17 is a graph showing the results of a second experiment.

18A and 18B are cross-sectional views showing a compound semiconductor device of a reference example; and Figs. 19A and 19B are graphs showing the results of a third experiment and a fourth experiment.

1‧‧‧Substrate

2a‧‧‧ initial layer

2b‧‧‧buffer layer

3‧‧‧Electronic channel layer

4‧‧‧Separation layer

5‧‧‧Electronic supply layer

6‧‧‧Including layer

6a‧‧‧In exclusion area

7‧‧‧ compound semiconductor stack structure

11d‧‧‧汲electrode

11g‧‧‧gate electrode

11s‧‧‧ source electrode

12‧‧‧Insulation film

13g‧‧‧ openings

14‧‧‧Insulation film

20‧‧‧Component isolation area

Claims (17)

A compound semiconductor device comprising: a substrate; a compound semiconductor stacked structure formed on the substrate; and a gate electrode, a source electrode and a drain electrode formed on the compound semiconductor stacked structure Or above, wherein the compound semiconductor stacked structure comprises: an electron channel layer; and a nitride semiconductor layer comprising an electron supply layer formed on the electron channel layer, and between the gate electrode and the source electrode One region and each region of a region between the gate electrode and the drain electrode, the indium (In) fraction of the surface of the nitride semiconductor layer is higher than the nitrogen in the region below the gate electrode The indium (In) fraction on the surface of the semiconductor layer is low. The compound semiconductor device of claim 1, wherein the nitride semiconductor layer comprises an In-containing layer formed on the electron supply layer. The compound semiconductor device of claim 1, wherein the electron supply layer is an In-containing layer. The compound semiconductor device of claim 2, wherein the In-containing layer comprises an In exclusion region, and the indium (In) fraction is reduced to a shallower portion of the In exclusion region, the shallow portion being The region is located between the gate electrode and the source electrode and in each region of the region between the gate electrode and the gate electrode. The compound semiconductor device according to any one of claims 1 to 3, wherein the nitride semiconductor layer is composed of In _x Al _y Ga _1-xy N (0<x) 1,0 y<1,x+y 1) indicates. The compound semiconductor device according to any one of claims 1 to 3, further comprising a gate insulating film formed between the gate electrode and the compound semiconductor stacked structure. The compound semiconductor device according to any one of claims 1 to 3, further comprising a termination film, wherein the termination film covers a region between the gate electrode and the source electrode, and the gate electrode and the gate electrode The compound semiconductor stacked structure in each region of the region between the drain electrodes. A power supply device comprising a compound semiconductor device, the compound semiconductor device comprising: a substrate; a compound semiconductor stacked structure formed on the substrate; and a gate electrode, a source electrode and a drain An electrode formed on or above the compound semiconductor stacked structure, wherein the compound semiconductor stacked structure includes: an electron channel layer; and a nitride semiconductor layer including an electron supply layer formed on the electron channel layer, and In the region between the gate electrode and the source electrode and in the region between the gate electrode and the gate electrode, the indium (In) fraction of the surface of one of the nitride semiconductor layers is The surface of the nitride semiconductor layer in the region under the gate electrode has a low indium (In) fraction. An amplifier comprising a compound semiconductor device and the compound half The conductor device comprises: a substrate; a compound semiconductor stacked structure formed on the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure, The compound semiconductor stack structure includes: an electron channel layer; and a nitride semiconductor layer including an electron supply layer formed on the electron channel layer, and a region between the gate electrode and the source electrode In each region of the region between the gate electrode and the drain electrode, an indium (In) fraction of a surface of the nitride semiconductor layer is a nitride semiconductor layer in a region below the gate electrode The surface of the surface has a low indium (In) fraction. A method of fabricating a compound semiconductor device comprising: forming a compound semiconductor stacked structure on a substrate; and forming a gate electrode, a source electrode and a drain electrode on or over the compound semiconductor stacked structure; The step of forming the compound semiconductor stacked structure further includes: forming an electron channel layer; and forming a nitride semiconductor layer including an electron supply layer on the electron channel layer, and the region between the gate electrode and the source electrode And in each region of the region between the gate electrode and the drain electrode, an indium (In) fraction of a surface of the nitride semiconductor layer is lower than the gate electrode The surface of the nitride semiconductor layer in the region has a low indium (In) fraction. The method of manufacturing a compound semiconductor device according to claim 10, wherein the step of forming the nitride semiconductor layer further comprises: forming an In-containing layer on the electron supply layer; and being located at the gate electrode and the source Indium (In) is excluded from the region between the electrode and the In-containing layer in each region of the region between the gate electrode and the gate electrode. The method of manufacturing a compound semiconductor device according to claim 10, wherein the electron supply layer comprises an In layer, and the step of forming the nitride semiconductor layer further comprises: being located at the gate electrode and the source electrode Indium (In) is excluded from the inter-region and the In-containing layer in each region of the region between the gate electrode and the gate electrode. A method of fabricating a compound semiconductor device according to claim 11 or 12, wherein the step of forming the indium (In) is included in a non-oxidizing environment using a mask covering one of the regions where the gate electrode is to be formed Annealing is performed. A method of manufacturing a compound semiconductor device according to claim 13 wherein the non-oxidizing environment is an N ₂ gas atmosphere, an H ₂ gas atmosphere, or a mixed gas atmosphere of N ₂ gas and H ₂ gas. A method of fabricating a compound semiconductor device according to claim 13 wherein the ohmic characteristics of the source electrode and the drain electrode are formed during the annealing. Making a compound as claimed in any one of claims 10 to 12 The method of the semiconductor device further includes forming a gate insulating film on or over the compound semiconductor stacked structure before forming the gate electrode. The method of manufacturing a compound semiconductor device according to any one of claims 10 to 12, further comprising forming a termination film, and the termination film covers a region between the gate electrode and the source electrode and The compound semiconductor stacked structure in each region of the region between the gate electrode and the drain electrode.