TWI478094B - Guard band clipping systems and methods - Google Patents

Description

Protective tape shearing system and method

The present invention relates to a data processing system, and more particularly to a computer graphics system and method.

Computer graphics is a science and art that uses computers to produce graphics, images, or other pictorial or graphic information. The generation of graphics or images is often referred to as rendering. Generally, in computer three-dimensional drawing, the geometry representing the surface (or volume) of an object in a scene is translated into primitives (image primitives), stored in a frame register, and then displayed on a display device.

When rendering a graphic or image, when processed through multiple parallel systems, the object undergoes multiple processes through multiple stages of the pipeline, often referred to as space. Referring to Figure 1, the rendering process 10 is generally shown as from the model space 102 to the world space 104, to the view space 106, to the clip space 108, to the display space. (screen space) 110. In some implementations, this process may include world space 104 and jump directly from model space 102 to observation space 106. Briefly, the model space 102 represents the original adjustment system, so that certain objects that will be included in the current scene have not yet been converted. Model space 102 provides a platform for the user to use the model transformation to process objects on the display. Through the user interface of the computer display, the user can try to find directions or sort the objects in various aspects, shapes and/or sizes. In more detail, through the user interface, users can go through various The model transformation provided for the object or model directs the host processor to perform the modification, with the result that the model space 102 becomes the world space 104.

More transformations (e.g., observation transitions) are provided from the world space 104 to the vertices of the transformed object to facilitate launching and shearing, thereby developing into the observation space 106. In the observation space 106 (also referred to as the shooting space), various functions are generated - such as adding, modifying brightness and/or shadows, tiny rejections, creating an observation book, etc., which form a judgment: what objects can be photographed by the camera and what Objects cannot be captured by the camera. For example, an observation of a plane truncation with close and long shear planes is typically created. Objects of rendered 3D scenes, if the close and far cut planes do not match the edges of the plane cuts, the processing is ignored, thereby reducing the cut operation.

In the shear space 108, the coordinates of the plane cuts created in the observation space 106 are formatted (eg, by perspective division) to simplify the complexity of the cut, and then the cut is performed.

Once the cut is performed, the base primitives in the observations are mapped to display space 110 and rendered onto the display device. Please note that in some cases, various processes as described above may occur in different and/or other spaces.

See cut space 108 now, applying various techniques to reduce the number of primitives that need to be cut (such as triangles). One of the commonly used techniques is the protective tape cutting technique. In the guard band shear, the close and long shear planes created in the observation space 106 remain unchanged, but the plane cuts are stretched beyond the desired viewport. In other words, a total of two plane truncations are created: one is the guard band plane truncation and the other is the smaller viewport plane truncation. The environment for rendering and cutting can be implemented as follows. If the triangle is outside the viewport, it is completely discarded. If the triangle is inside the viewport, it does not need to be cut and rendered directly. If the triangle intersects the viewport and the guard plane plane section or if the triangle crosses the close and long distance cut planes, the cut is performed.

Although guard band clipping provides a conservative approach to rendering (for example, more triangles pass directly than triangles that need to be cut), this conservativeity is still balanced with the reduction in shearing operations. That is to say, in most cases, the time interval during which the guard band shear is reduced depends on the cutting performed by the main processor (for example, the central processing unit, or the CPU) by receiving a triangle located outside the display screen, allowing the main The processor performs a simpler and faster selection and shear test interval. However, when the triangle is about to be cut, the processing is laborious and time consuming. In traditional systems, the typical approach is to perform a cut by performing one of several different algorithms on the host processor, such as Cohen-Sutherland, Catherine. The Sutherland-Hodgman algorithm, the Weiler-Atherton algorithm, the Patrick Gilles Maillot, and so on. These algorithms usually need to be completely classified (for example, observing the plane cut-off cut code), the intersection judgment with the observation cut plane, and the interpolation of each parameter of the vertex (such as alpha parameter, Fogo parameter, etc.). Both require very strong calculation steps, and the mapping with the hardware is not very good.

The present invention provides systems and methods for protecting the belt from shearing. Briefly, In an architecture, an embodiment of one of the methods of the present invention includes: transmitting the converted vertex data to a downstream of the drawing pipeline; and the guard band cutting module determines whether the basic primitive corresponding to the converted vertex data needs to be cut. And performing protection guard band shearing and center of gravity interpolation based on the above determination to protect the coordinates of the new vertex with the clipping calculation logic unit.

An embodiment of one of the guard band shearing systems of the present invention includes: a vertex processor that converts the converted vertex data to integer display spatial data, calculates the cut code, and transmits the converted vertex data to the downstream of the drawing pipeline And a protection strip shearing module coupled to the vertex processor, a guard band computing logic unit coupled to the guard band shearing module, the guard band shearing module for determining and converting the transformed vertex data Whether the corresponding basic primitive needs to be cut, according to the judgment, the basic primitive is transmitted to the guard band calculation logic unit to perform guard band clipping.

An embodiment of one of the guard band shearing systems of the present invention comprises: a state machine receiving state data and converted vertices; a vertex index buffer coupled to the state machine; and a vertex buffer buffered by the vertex index a vertex buffer storing the transformed vertex; a vertex processor coupled to the vertex index buffer, the vertex processor generating a cut code of the vertex, and corresponding to the result of the cut base element The vertices of the attributes perform perspective rendering correction; a tiny rejection module performs micro-rejection according to the value of the clipping code; a protection band cutting module determines whether the basic primitive needs to be protected according to the value of the clipping code a shearing; and a guard band shear calculation logic unit that cuts the base primitive in response to a determination that a cut is required; the guard band shear calculation logic unit is further configured to perform interpolation to define a new cut The coordinates of the vertices.

The protective tape shearing system and method (referred to as the GB shearing system) disclosed herein provides a fast, convenient, hardware-based protective tape shear. In one embodiment, the cutting is performed by one or more fixed point computational logic units (ALUs) without the need for the main processor to operate, which speeds up the clipping process compared to conventional techniques. In such an embodiment, the cut is performed in the display space, and the tiny rejection is performed in the cut space or display space. Because of the implementation of dedicated hardware, embodiments of the GB shear system of the present invention that do not use a main processor provide efficient, high speed calculations, reducing complexity.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

2 is an embodiment of a graphics processing system 100 that includes an embodiment of a guard band (GB) shearing system 200. In some cases, the graphics processing system 100 can be configured as a computer system. The graphics processing system 100 can include a display device 202, by a display interface unit (DIU) 204 and local memory 206 (eg, can include display buffers, texture buffers, command buffers, etc.). Here, local memory 206 may also include a frame buffer or a storage unit. The local memory 206 is coupled to a graphics processing unit (GPU) 214 via a storage interface unit (MIU) 210. In the present embodiment, the storage interface unit 210, the graphics processing unit 214, and the display interface unit 204 are coupled to a bus interface unit (BIU) 218. In one embodiment, the bus interface unit 218 can be compatible with PCIE and can be used The Plot Address Remap Table (GART), although other memory mapping mechanisms are used. The graphics processing unit GPU 214 includes a GB shearing system 200, as described below. Although shown as only one component of the graphics processing unit GPU 214, in some embodiments, the GB cutout system 200 can include other components of one or more of the graphics processing systems 100 as shown, or other components.

The bus interface unit 218 is coupled to a chip set 222 (such as a north bridge chip set) or a converter. The chipset 222 includes interface circuitry for enhancing signals from a central processing unit (CPU) 226 (also referred to herein as a main processor) and for inputting and receiving signals to and from the system memory 224, as well as input and output devices (I/O) ( The signals not shown in the figure are separated. Although a PCIE bus bar protocol is described herein, in some embodiments, other connections and/or communication methods (such as PCI, dedicated high speed bus, etc.) may be employed between the main processor 226 and the graphics processing unit 214. System memory 224 also includes driver software 250 for communicating communication instructions or commands to the scratchpad and instruction stream handlers in graphics processing unit 214 via host processor 226.

In some embodiments, other graphics processing units are also included, such as coupled to the elements shown in FIG. 2 via a PCIE busbar protocol via chipset 222. In one embodiment, the graphics processing system 100 may include all of the elements shown in FIG. 2, and may also include several and/or different elements. Additionally, in some embodiments, other components, such as a south bridge chipset coupled to the wafer set 222, may also be utilized.

In certain particular embodiments, the GB shearing system 200 is implemented in hardware, including any one or combination of the following, as in the art. Known to the surgeon: a logic discrete circuit with logic gates to implement the logic function of the data signal, a special application integrated circuit (ASIC) with a corresponding logic gate combination, a programmable gate array (PGA), a field programmable gate Array (FPGA), state machine, and more.

3 is a schematic diagram of an embodiment of the drawing processing unit 214 and the guard band shearing system 200 in FIG. In some embodiments, more or less elements than those shown in FIG. 3 may also be included. For example, each module or unit as described below may have its own internal register or register, which is not shown in the figure, and may be used independently in the module or shared with other modules. In one embodiment, the graphics processing unit 214 can be configured as a pipeline architecture including a Command Stream Processor (CSP) 302, an Execution Unit Pool (EU) 304, a Triangular Structure Unit (TSU) 306, and a GB Shear System 200, attributes. Structural Unit (ASU) 308, Range and Tile Generation Unit (STG) 310, Texture First In First Out Unit (TFIFO) 312, Deep First In First Out Unit (ZFIFO) 314, Attribute Structure Unit (ASU) First In First Out (FIFO) The unit (AFIFO) 316 is integrated.

The command stream processor 302 provides status data (from the driver software 250), and the execution unit pool 304 (such as the vertex shape function) provides exchanged vertex data (which may also come from the driver software 250) to the triangulation unit 306. In some embodiments, vertex data can be provided by a fixed function vertex shader processor. Based on the received data, the triangulation unit 306 integrates and sets basic primitives (such as lines, triangles, such as polygons, triangles, combined basic primitives of the sector, etc.) for blank clipping, and reprocesses the attribute structure unit 308. data. For example, the triangular structure unit 306 performs Known tasks: viewport conversion, tiny rejection, range box generation and culling. In addition, the triangular structure unit 306 performs guard band shearing by using the GB shearing system 200.

The triangulation unit 306 provides these materials from the processor described above to the attribute structure unit 308, which sets the attribute triangle values for each of the base elements to be rendered (eg, through primitive-level interpolation) (eg, Color, depth, transparency, blur, etc.). Such attribute triangle values are sent to the depth first in first out unit 314 and the attribute structure unit first in first out unit unit 316. For example, if attribute structure unit 308 includes Z (depth), attribute trigonometric processing unit (eg, ALU, etc.), along with depth first in first out unit 314, performs such calculations, as is known to those skilled in the art, in depth first in, first out. These triangular values are written in unit 314 for subsequent use in the Z-test unit. The attribute structure unit 308 cooperates with the attribute structure unit first in first out unit 316 to perform primitive color and texture attribute triangulation processing known to those skilled in the art for further interpolation at the primitive level. The attribute structure unit 308 also passes the triangular structure unit edge function to the range and tile generation 310, and the range and tile generation 310 provides a tile generation function that causes the data object to be segmented into tiles (eg, 8x8, 16x16, etc.) and passed to Texture first in first out unit 312.

Figure 4 is a schematic illustration of some of the elements of an embodiment of the protective (GB) tape shearing system 200 shown in Figure 3. As described above, in one embodiment, the GB shearing system 200 is part of the triangular structure unit 306, including an input state machine (ISM) 402, a scratchpad module 404, a vertex search buffer (VIB) 406, Vertex buffer (VB) 408, vertex processor 410, basic primitive sink Edit/Micro Reject (PATR) module 412 (also known as micro-rejection module), protection band cut module (GBC) 414, guard band vertex buffer (GBVB) 416, guard band calculation logic unit (GB ALU) 418, a triangle processor (TRIPROC) 420, and a guard band attribute output state machine (OSM GBA) module 422. The guard band attribute output state machine (OSM GBA) module 422 outputs the result of protecting the vertex attribute to the attribute structure unit 308 for further setup. The attribute structure unit 308 is shown in FIG. 4 and may also include other elements. The attribute structure unit (ASU) calculation logic unit (ALU) 424 transfers the data to the range and tile generation unit 310, and the attribute structure unit first in first out unit unit 316. And a deep FIFO unit 314, as described in FIG. Some embodiments of the GB shear system 200 may include fewer or more or different components.

In general, guard band clipping is performed after the vertex coordinates (and associated attributes) are corrected and mapped to integer display coordinates in vertex processor 410, such that linear interpolation matches the display space requirements. In one embodiment, the perspective rendering corrections are all synchronized with the XYZ coordinate determination, it being understood that some of the vertices may later be clipped in the guard band calculation logic unit 418 along with the calculated value of the new vertex result. Thus, as will be discussed further below, vertex processor 410 serves at least two hardware modules, which are referred to as vertex retrieval buffer 406 and guard band cutout module 414. In one embodiment, the guard band shear module 414 has a higher priority than the standard phase disposed between the vertex processor 410 and the vertex search buffer 406, thus the shear from the guard band shear module 414 The request related to the cut operation can interrupt the current search buffer from the vertex The vertex processing of the 406 is processed.

Input state machine 402 is used to synchronize execution of unit pool data (eg, state, commands, converted vertex data) and command stream processor data (eg, status, commands). The input state machine 402 communicates the command and status data to the scratchpad module 404, and passes the converted vertex data to the vertex lookup buffer 406. Vertex retrieval buffer 406 writes vertex data to vertex buffer 408. The vertex retrieval buffer 406 determines its reference number based on the position (e.g., band) of each vertex in the base primitive. When the base primitive is rejected or completed (if it is completed, it is passed to the attribute structure unit 308), the vertex retrieval buffer 406 updates (self-updates or updates according to the request of the downstream module) all the specific basics in the same or substantially the same time. The reference number of all vertices of the primitive. Vertex buffer 408 receives vertex data transmitted from input state machine 402 when any of the input to the vertex buffer is released (eg, when all of the base primitives are rejected or are passed to attribute structure unit 308).

Vertex processor 410 receives the cut space vertex data from vertex buffer 408 (using an index through vertex retrieval buffer 406), performs perspective art correction and viewport conversion, and converts the data to an integer display space. The vertex processor 410 also generates a cut code for the vertex, which is used by the downstream modules to determine whether to include a minor rejection or a guard band cut. In one embodiment, vertex processor 410 includes a pipeline (eg, a multi-stage pipeline architecture. Thus, during standard processing, vertex processor 410 processes all of the vertices required for all upcoming vertex retrieval buffers 406 and will Transfer to the base primitive assembly/micro-rejection module 412 and the guard band cutout module 414.

The standard processing performed by vertex processor 410 and vertex retrieval buffer 406 continues until guard band shear module 414 transmits a signal to vertex processor 410 indicating receipt of a clipping event. In general, in response to the generation of new vertices based on the shearing operation, the guard band clipping module 414 requests the vertex processor 410 to interrupt the processing from the vertex retrieval buffer 406, and the XYZ vertex calculation and the attribute perspective rendering correction are processed by the vertex. The unit 410 is redone. As implied above, the vertex processor 410 accomplishes the above various tasks by temporarily storing all current data in an integer buffer, and the instant service protection band cut module request. After the protection band cutout module request is processed, the processing of the vertex retrieval buffer 406 continues. In particular, for the base primitive to be protected for shear band clipping, vertex processor 410 retrieves the cut space data from vertex retrieval buffer 406 and then generates new vertices for the cropped base primitive. For example, when a guard band shear event is generated in a subsequent pipeline phase (eg, the signal from the guard band shear module 414 indicates that a shear event is generated), the vertex processor 410 takes the data (data required for current stage processing) from the vertex. The search buffer 406 is copied, temporarily stored in a temporary buffer, and in one embodiment, stored in the vertex processor 410. After the service protection band cut module request, the vertex processor 410 accesses the temporary storage data and continues processing the data of the vertex retrieval buffer 406.

After the vertex processor 410 has processed, the base primitive assembler/minor rejection module 412 performs a slight rejection of all vertices located outside of the viewport (represented by the cut code of the vertex processor 410). One or more micro-rejection techniques (in display or shear space) may be used, including those known in the art: negative W, shear window, Z close distance, Z long distance, cull distance Off test and shear face test.

The base primitive data is passed to a guard band shear module 414 which determines whether a tape cut is required based on the cut code generated by the vertex processor 410, and the cut code is also suggested to the guard band shear module 414 for protection. The band and viewport parts are referenced, and the position of the base vertices is located. If clipping is required, the vertex data is transferred to the guard band vertex buffer 416 and the cut calculation is performed in the guard band calculation logic unit 418. The clipped triangles are passed to a triangle processor 420 where calculations such as deterministic calculations, range boxes, edge functions, attribute functions, and the like known to those skilled in the art are performed. The output of the triangle processor 420 is provided to a guard band attribute output state machine module 422, as described above. The output of the guard band attribute output state machine module 422 (vertex attribute) is output to the attribute structure unit calculation logic unit 424 and then output to the range and tile generation unit 310 and various FIFOs, as detailed above. The attribute structure unit calculation logic unit 424 receives the clipped (or called protected) vertex attributes (Z, color, texture, etc.) from the guard band attribute output state machine module 422, and calculates a trigonometric value for the primitive The processing stage performs further imputation. Thus, the attribute structure unit calculation logic unit 424 transfers the triangular geometry setting material from the triangle processor 420 to the range and tile generation unit 310. The attribute triangle value and any status information are written to the depth first in first out unit 314 and the attribute structure unit first in first out unit unit 316.

Figure 5 depicts a flow diagram of one embodiment of a method of the protective tape shearing system of Figure 4, indicated at 200a. The relevant portions of the method 200a are described in detail in Figures 6 and 7, respectively. The GB shearing method 200a performs a guard band shear test 502. Referring now further to FIG. 6, step 602, vertex retrieval buffer 406 accesses display space data from vertex buffer 408 and provides it to vertex processor 410 in step 604. In one of these embodiments, such access will begin after becoming a spatial state downstream of the guard band shear module 414. The following formula represents the mechanism by which vertex processor 410 uses the virtual code to generate the cut code:

In short, the above virtual code sets a clipping flag or a cut code for each vertex, and the guard band cutting module 414 indicates whether or not the guard band is to be cut. The driver software 250 sets different wnear and wfar values and sets the depth range in the clipping space to be larger than the z range (znear, zfar) of the display space. GB_range corresponds to the GB range index value (for example, 13, 23). Shear space data (e.g., x0, y0, etc.) is accessed from vertex buffer 408 by vertex retrieval buffer 406. Note that vertex processor 410 performs floating point operations, with each digit having a numerical portion and an exponent portion.

As part of the guard band shear test step 502, the vertex search buffer 406 also transmits the display spatial data to the base primitive assembler/micro-rejection module 412, see step 606. Accordingly, step 608 determines if a minor rejection is performed. The basic primitive assembly/micro-rejection module 412 is determined by a cut code of a vertex of a predetermined basic primitive (e.g., a triangle). The cut code describes the position of the vertex relative to the guard band, resulting from the method of the embodiment described above. In addition, the cut code is also useful for subsequent reserved triangles (such as not encountered by the clipping process) to control the interpolation of new vertices. The following pseudo code describes an embodiment in which the basic primitive assembler/minor rejection module 412 performs processing: }

As can be seen from the second portion of the virtual code described above, if a microrejection is to be performed, in one embodiment, the execution of the microrejection (step 610) will be based on the setting of the vertex flag, and the vertex flag is based on the guard band in the two dimensional space. The range is generated from a comparison of the display space data used by the Z or W from the vertex search buffer 406. For example, if all three vertices of a triangle are outside the Z range (Z<0), then this triangle is rejected. That is, if all three vertices are negative Z, even if the above described pseudo code (corresponding to the operation of vertex processor 410) is true and the triangle is within the guard band, the triangle will still be rejected. It should be noted that the triangle is invisible because all three vertices are negative Z. In one of the embodiments, the implementation of the micro-reject includes: performing a Z-distance test. In the Z close-range test, the following program is executed for the triangle segments corresponding to the various vertex combinations: the vertex v0v1, v1v2, v2v0 is set, and the clipping flag is generated on the Z range:

For the first portion of the virtual code described above corresponding to the base primitive assembler/minor rejection module 412, the triangle that is not slightly rejected will perform guard band clipping (step 504). See Figure 7, which further describes the guard band shearing method 504. In general, to protect the tape cut, do the following: (a) If all three vertices w 0, then reject this triangle (for example, if the triangle W is negative W, then the triangle is invisible, reject the triangle. Same as Z); (b) perform xy-cut (depending on the edge of the guard band, by - w x w,-w y w definition, (according to xy-clip code), for each XY clipping plane (x=w, x=-w, y=w, y=-w)); and (c) perform W-cut (wnear) w Wfar, for each W clipping plane (w=wnear, w=wfar).

Still further, the guard band cutout module 414 receives vertex data (to be clipped) from the vertex buffer 408 (through the vertex retrieval buffer 406) (step 702), and performs Z close range in the guard band calculation logic unit 418. Cut (step 704).

In Z close range shearing, each vertex combination (v ₀ v ₁ , v ₁ v ₂ , v ₂ v ₀ ) is sequentially clipped by the Z close distance plane. In order to define the coordinates of the new post-cut vertex, the center of gravity interpolation is performed. Taking v ₁ v ₂ as an example, the following virtual code describes an exemplary flow (note that with reference to the output buffer described below, in one embodiment, the reference guard band vertex buffer 416, "r" represents edge-derived The ratio of new vertices produced by the two vertices, "r" is also used by the center of gravity interpolation for other attributes (such as RGB), including XYZW):

In one embodiment, guard band calculation logic unit 418 performs XY shearing and W shearing while performing Z close shearing (steps 706, 708). While performing the above Z close range shearing, the individual cut vertices are stored in the guard band vertex buffer 416. If at least one of these vertices is in the viewport, this vertex is in the guard band and is represented by the following expression: -w<x<w, -w<y<w. As such, for XY clipping, a cut code is generated for each vertex (such as produced by vertex processor 410) and a new vertex is generated (based on the cut program). In one of these embodiments, each vertex uses the following four bits to describe the clipping code (such as left, right, bottom, top): Bit ₀ = (x < - w) Bit ₁ = (x > w) Bit ₂ =(y<-w) Bit ₃ =(y>w)3

The XY shearing routine continues to be described below. In one of the embodiments, the guard band calculation logic unit 418 performs the left, right, bottom, and top cuts. During each shear phase, one or more buffers (such as including a guard band vertex buffer 416) are used to temporarily store vertex data. For example, use one buffer to store the input and another to store the output. For example, guard band calculation logic unit 418 performs the following virtual code:

The guard band vertex buffer 416 can store a series of vertices (such as 8). The vertices of this series are located at the head by v0, and the points are connected to form a fan shape, which is accompanied by the protection flag flag output to the triangle processor 420. . For example, an interpolation command can be used to define the attribute value of the post-cut vertex using the guard band flag. Note that although the pseudo code is parallel processing in the above description, W clipping and XY clipping can be performed in order. Subsequently, a triangulation is performed (for example, by GB ALU 418). After the triangulation, the attribute structure unit calculation logic unit 424 of the attribute structure unit 308 performs attribute interpolation. To calculate the attribute value of the new triangle, attribute structure unit calculation logic unit 424 requests a ratio from guard band vertex buffer 416 and an attribute to vertex buffer 408.

The flowcharts of Figures 5-7 illustrate embodiments of the architecture, functionality, and/or operation of the guard band shear system 200 and the corresponding method 200a. At this point, Each square represents various functions of one or more modules. It should be understood that other alternative devices, components, functions, and flows may be beyond the scope of FIGS. 5-7. For example, the flow represented by the two blocks in Figure 5 can also be executed in two blocks in succession, or sometimes in reverse order, depending on the desired function, which will be below. For further explanation.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102‧‧‧Model space

104‧‧‧World Space

106‧‧‧ Observation space

108‧‧‧Cutting space

110‧‧‧ display space

200‧‧‧GB shearing system

202‧‧‧Display equipment

204‧‧‧Display interface unit

206‧‧‧Local memory

210‧‧‧Storage interface unit

214‧‧‧Drawing processing unit

222‧‧‧ Chipset

218‧‧‧ bus interface unit

224‧‧‧ system memory

226‧‧‧ central processor

250‧‧‧Drive software

302‧‧‧Command Stream Processor

304‧‧‧Executive unit pool

306‧‧‧Triangular structural unit

308‧‧‧Attribute Structure Unit

310‧‧‧ Range and tile generation unit

402‧‧‧Input state machine

312‧‧‧Textured FIFO unit

404‧‧‧Storage Module

314‧‧‧Deep FIFO unit

408‧‧‧ vertex buffer

406‧‧‧Vertex Search Buffer

410‧‧‧ vertex processor

414‧‧‧Protection belt shear module

420‧‧‧ Triangle Processor

416‧‧‧Protection with vertex buffer

316‧‧‧Attribute Structure Unit FIFO Unit

412‧‧‧Basic Element Compilation/Micro Rejection Module

418‧‧‧Protection Band Computing Logic Unit

422‧‧‧Protection band attribute output state machine module

424‧‧‧Attribute Structure Unit Calculation Logic Unit

502, 504, 602~610, 702~708‧‧‧ steps

1 is a conceptual block diagram depicting various equivalent systems or spaces for rendering images in a graphics processing system; FIG. 2 is an embodiment of a guard band shearing system and method in a graphics processing system of the present invention; 2 is a block diagram of an embodiment of a drawing processing unit and a protective tape cutting system in FIG. 2; FIG. 4 is a block diagram of an embodiment of a protective tape cutting system shown in FIG. 3; and FIG. 5 to FIG. A flow chart of an embodiment of a method of protecting a belt shearing system is shown.

100‧‧‧Drawing Processing System

200‧‧‧GB shearing system

202‧‧‧Display equipment

204‧‧‧Display interface unit

206‧‧‧Local memory

210‧‧‧Storage interface unit

214‧‧‧Drawing processing unit

218‧‧‧ bus interface unit

222‧‧‧ Chipset

224‧‧‧ system memory

226‧‧‧ central processor

250‧‧‧Drive software

Claims (16)

A protection band clipping system in a graphics processor, comprising: a vertex processor, converting the converted vertex data to an integer display space data, calculating a clipping code, and transmitting the converted vertex data to a downstream of the drawing pipeline; And a protection band cutting module coupled to the vertex processor; a protection band computing logic unit coupled to the protection band cutting module, the protection band cutting module is used to determine the converted Whether the corresponding primitive element of the vertex data needs protection band shearing, and when it is determined that the protection band is required to be cut, the basic element is transmitted to the protection band calculation logic unit to perform protection band shearing, in response to the protection band calculation The guard band cut performed by the logic unit, the guard band shear module is further configured to request an interrupt of a standard process through the vertex processor, and the interrupt should be interrupted, and the vertex processor recalculates the vertex coordinates and the recalculated The cut code of the vertex coordinates, performing a perspective correction on the attribute corresponding to the recalculated vertex coordinates, and mapping the recalculated vertex coordinates to integers Show space. The protection band clipping system in the graphics processor of claim 1, further comprising a vertex index buffer coupled to a vertex buffer and the vertex buffer, wherein the vertex buffer is used to store the conversion Post vertex data and clipping space data. A guard band clipping system in a graphics processor according to claim 1, wherein the vertex processor performs standard processing of the converted vertex data by accessing a vertex buffer via a vertex index buffer. . The protection band cutting system in the drawing processor according to claim 1, further comprising a micro rejection module, determining whether to perform a micro rejection of the basic primitive according to the cut code from the vertex processor. And it should be judged that the tiny rejection module is used to perform the micro rejection. The protective tape cutting system of the drawing processor of claim 1, wherein the protective tape cutting module is further configured to determine whether a basic primitive needs to be executed according to a cut code from the vertex processor. Protective tape is cut. The protective tape cutting system in the drawing processor according to claim 1, further comprising an attribute setting unit that receives the guard band vertex attribute from the guard band cutting system, and for each of the basics to be rendered The primitives are set to the attribute triangle values. A guard band shearing system in a graphics processor as described in claim 1, wherein the guard band shear calculation logic unit is configured to perform center of gravity interpolation to define coordinates of newly cut vertices. A protection band shearing method comprises: transmitting a converted vertex data to a downstream of a drawing pipeline; and determining, in a guard band shearing module, whether a basic primitive corresponding to the converted vertex data needs a protection band shear; When the guard band is required to be cut, the guard band shear is performed and interpolation is performed to define a new cut vertex in the guard band shear calculation logic unit; and a guard band shear performed by the logic unit in response to the guard band calculation Cutting operation, the protection band cutting module requests a vertex processor standard operation Breaking, wherein the vertex processor responds to the interrupt by recalculating vertex coordinates and recalculating the cut code for the recalculated vertex coordinates; performing perspective art correction for the attribute corresponding to the recalculated vertex coordinates ; and map the recalculated vertex coordinates to the integer display space. The protective tape cutting method of claim 8, wherein the interpolation is a center of gravity interpolation. The protection band clipping method of claim 8, further comprising: storing the converted vertex data and cutting the spatial data in a vertex buffer indexed by a vertex index buffer. The protection band clipping method of claim 10, further comprising: processing the converted vertex data by accessing the vertex buffer via the vertex index buffer. The protection band cutting method according to claim 8, further comprising: a micro rejection module determining whether the basic primitive needs to perform a micro rejection according to a cut code from a vertex processor. The protective tape cutting method according to claim 12, further comprising: the micro rejection module performing a response of the determination. The protection tape cutting method according to claim 8 of the patent application scope, further comprising: determining whether the basic primitive is required according to a cut code from a vertex processor To perform a guard band cut. The protection tape cutting method according to the item of claim 8, further comprising: an attribute setting unit receiving the protection layer processed vertex attribute from the protection band shearing system, and each of which is to be rendered The base element sets the attribute triangle value separately. A guard band clipping system in a graphics processor pipeline, comprising: a state machine, receiving state data and converted vertices; a vertex index buffer coupled to the state machine; and a vertex buffer buffered by the vertex index a vertex buffer storing the transformed vertex; a vertex processor coupled to the vertex index buffer, the vertex processor generating a cut code of the vertex, and corresponding to the result of the cut base element The vertices of the attributes perform perspective rendering correction; a tiny rejection module performs micro-rejection according to the value of the clipping code; a protection band cutting module determines whether the basic primitive needs to be protected according to the value of the clipping code And a guard band shear calculation logic unit that cuts the base primitive in response to a determination that a cut is required; the guard band shear calculation logic unit is further configured to perform interpolation to define a new cut a coordinate of the vertex, in response to the guard band shear performed by the guard band computing logic unit, the guard band shear module is further configured to request a standard processing through the vertex processor , Responds to the interrupt, the processor recalculates the vertex coordinates of the vertices and the vertex coordinates recalculated shear code, attributes to the vertex coordinates of the corresponding recalculation Perform a perspective correction and map the recalculated vertex coordinates to the integer display space.