TWI475378B - Storage system to couple to a host, controller to interface with nand memory in storage system, and method of managing a stack of nand memory devices - Google Patents

Description

a storage system coupled to a host, a controller coupled to a NAND memory in the storage system, and a method of managing a stack of NAND memory devices

Today's communication devices continue to become more complex and diverse to provide increased functionality. These devices support multimedia that requires higher capacity memory, specifically provided by a multi-chip package design. Communication links, bus bars, chip-to-wafer interconnects, and storage media can operate in the event of signal/storage failures at high levels. It is expected that such communication devices incorporate error detection and correction mechanisms. The ECC (Bug Error Correction Code) has been moved into the memory storage structure but requires additional improvements.

In the following detailed description, numerous specific details are set forth However, those skilled in the art will appreciate that the invention may be practiced without the specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail so that the invention is not concealed.

The embodiment illustrated in Figure 1 shows a communication device 10 that may include non-volatile memory having a virtualized ECC NAND controller that serves multiple NAND flash devices in accordance with the present invention. The invention is not limited to wireless communication embodiments and other non-wireless applications may also use the invention. As shown in such a wireless embodiment, communication device 10 includes one or more antenna structures 14 to allow radios to communicate with other over-the-air communication devices. As such, the communication device 10 can operate as a cellular device or a device operating in a wireless network such as: Wireless Fidelity (Wi-Fi), WiMax, Mobile WiMax, and Wideband Coded Multiple Proximity ( WCDMA), and Global System for Mobile Communications (GSM) networks, but the invention is not limited to operating only in such networks. The radio subsystems, which are placed in the same platform of the communication device 10, provide the ability to communicate with other devices in a network in a different RF/location space in different frequency bands.

This embodiment illustrates that antenna structure 14 is coupled to transceiver 12 to accommodate modulation/demodulation variations. In general, the analog front end transceiver 12 may be a separate radio frequency (RF) discrete or integrated analog circuit, or the transceiver 12 may embed a host central processing unit (CPU) 20 having one or more processor cores 16 and 18. . These cores allow processing of workloads across these cores and handle baseband and application functions. Data and instructions can be transferred between the CPU and the memory bank by a memory interface 28.

System memory 22 can include both volatile memory and non-volatile memory, such as NAND memory structure 24. Please note that these volatile and non-volatile memories can be packaged separately or combined in a stacking process. In particular, multiple NAND memory structures can be placed in a multi-chip package (MCP) to reduce the footprint on a board. Thus, various embodiments of system memory 22 show that memory devices can be configured in different ways by mixing memory devices and configurations to take advantage of the limited space within the communication product, and various package options can be used to find low A good combination of power and high reliability.

In the prior art, performing an ECC (Error Correction Code) algorithm inside a NAND memory is limited to providing an error detection and correction mechanism that is only suitable for a single memory device. Updating a fixed host platform to support a new NAND technology will cost you a lot of ECC requirements, page size, addressing capabilities, and new command set specifications. There are further limitations, and the ECC algorithm is a specific technique. For example, changes between single layer unit technology (SLC) and multi-level cell technology (MLC) will invalidate the ECC algorithm in use. In addition, an alternative memory with a different product reduction level will have to be modified for existing ECC algorithms. And existing memory devices incorporating ECC internally are costly based on the combined die area of the flash and ECC algorithm logic.

To overcome these shortcomings and in accordance with the present invention, the architecture illustrated in Figure 2 allows a single virtualized ECC NAND controller 26 to serve multiple NAND memory structures, i.e., a "raw" memory stack 24. The term "raw" implies a NAND memory device that does not implement an ECC algorithm internally. Regardless of the number of internal raw NAND memories, the host CPU 20 drives the virtualized ECC NAND controller 26 and the raw NAND memory structure as a single memory system. In addition, because this solution can select one NAND at a time, power consumption is reduced compared to prior art stacked architectures. The virtualized ECC NAND controller 26 includes a protocol interface 30 for exchanging signals with the host CPU 20, an ECC engine 32 for performing an ECC algorithm, and a NAND interface 34 for managing the memory stack 24.

The virtualized ECC NAND controller 26 acts as a bridge from the host NAND interface to the original NAND memory stack and provides the host with the correct ECC algorithm for the raw NAND provided in the system memory. The host side operates with its standard NAND interface, address space, command set, page size, ECC, etc., and the virtualized ECC NAND controller 26 adapts the host side to the particular raw NAND that is incorporated into the memory stack.

By removing ECC functionality from individual NAND memory devices in the NAND stack and incorporating the functionality into the ECC NAND controller 26, a variety of features can be implemented. In the case where the ECC NAND controller 26 is external to the NAND memory device, the host side implements a virtualized address space that allows the host to drive the system as a single NAND wafer, even if there are multiple NAND memory devices in the storage system. . Thus, host CPU 20 is free to manage more of the wafers at the interface. In other words, when the host CPU 20 manages one of the chips at the interface, the virtualized ECC NAND controller 26 can manage the plurality of NAND memory devices in the stacked memory.

Prior art products combine ECC along with data management algorithms (eg, Flash Translation Layer (FTL), wear leveling, damaged block management, etc.) in a common integrated circuit. In contrast, the architecture presented in the figure separates the ECC from the data management algorithm. The virtualized ECC NAND controller 26 implements only the ECC algorithm and does not implement any other data management algorithms. This allows the host CPU 20 to maintain full control of the virtualized memory in terms of data pages, metadata areas, and allows the virtualized ECC NAND controller 26 to provide a better ECC engine.

In using the virtualized ECC NAND controller 26 as a bridge from the host NAND interface to the original NAND memory stack, the host platform can manage a page size that is different from the page size of the original NAND. In addition, the virtualized ECC NAND controller 26 isolates the host platform from the memory stack to allow the host CPU 20 to use certain commands that are not supported by the original NAND. In one embodiment, host CPU 20 may have a larger set of commands than the command set of the virtual memory device in the virtualized ECC NAND, while in another embodiment, compared to the command set internal to the virtualized ECC NAND. The command set of the host can be a reduced command set. In either embodiment, the logic within the ECC NAND controller 26 adapts the set of commands of the host CPU 20 to the set of commands of the physical memory device. The host platform can use a basic NAND command set and the virtualized NAND controller 26 can use a new set of commands that are extended.

3 shows that host CPU 20 is allowed to interface to protocol interface 30 via an unaltered electrical connection in the protocol specification to allow the host to communicate to a single memory system with a large error free address space. In other words, this architecture allows the host CPU 20 to provide data exchange with the memory stack 24 as a standard NAND interface to maintain a virtual command set and address space.

At the same time and without adding internal logic to the host platform, ECC NAND 26 provides ECC functionality to increase the overall reliability of the data exchange by correcting bit errors in the original NAND. The addressing is virtualized because the host CPU 20 drives the connected memory device as a single NAND die, and the virtualized ECC NAND controller 26 redirects the data to one of the selected NANDs of the stack. Thus, a single virtualized ECC NAND controller 26 manages the NAND flash memory stack and performs an ECC algorithm.

Additionally, the architecture of the virtualized ECC NAND controller 26 between the host CPU 20 and the memory stack 24 enables the use of a single NAND device to accommodate the ability to manage a set of NAND memories using different wafer enable (CE) pins. Host. In one embodiment, the host interface selectively drives different flash memories by using CE signals, although the virtualized ECC NAND is comprised of a single NAND die of higher density. The internal logic of the virtualized ECC NAND controller 26 translates the request from the host CPU 20 (which concludes one of the CEs) into a portion of the NAND array that is addressed to the selected NAND memory device itself. The request is encoded in the address loop of the support. It should be noted that host CPU 20 may have a number of address cycles that are less than the number of cycles required for a raw NAND memory device. Similarly, the host platform can manage a page size that is different from the page size of a raw NAND memory device and even use certain commands that are not supported by the memory device, such as a multi-plane job or a cache job.

For example, if the original NAND memory device does not support multi-plane jobs, the virtualized ECC NAND controller 26 can emulate these commands by two channels. If the original NAND memory device does not support a cache job, the virtualized ECC NAND controller 26 can emulate the commands by means of an internal ping pong buffer or the like. In addition, if the host platform requires a page size different from the page size of the original NAND memory device, the virtualized ECC NAND controller 26 provides a virtualization of a page size and page number different from the real physical block. Physical block.

The protocol interface 30 is the portion of the virtualized ECC NAND controller 26 that communicates with the host CPU 20 using standard NAND communication protocols. The protocol interface 30 interprets any received commands and further directs to store any data transmitted by the host. In addition, the protocol interface 30 manages the NAND ready/busy signal to account for the latency of the ECC algorithm. The protocol interface 30 includes an internal buffer 36 for storing data transmitted by the host CPU 20 during a staging operation. Following a confirmation command, the protocol interface 30 sets the busy signal low to avoid any type of data job being sent to the virtualized ECC NAND controller 26.

The size of the buffer 36 is appropriately selected to reduce the delay caused by the ECC calculation. In the case where the buffer size is appropriate, the host CPU 20 can start transmitting a new page during a write operation without waiting for the previous flash stylized job to end. This timing advantage will benefit during a subsequent read operation, and thus, while the ECC engine 32 calculates the redundancy on the current page, the next page can be retrieved from the original NAND.

The ECC engine 32 is a portion of the virtualized ECC NAND controller 26 that is servoed to implement an ECC algorithm that computes redundancy on the data sent by the host CPU 20. The ECC algorithm is used to detect and correct errors that occur during the storage or writing of the original information to the stacked memory 24 or from the stacked memory 24. The ECC algorithm can implement multiple layers, cyclicity, error correction, and variable length digital code to correct multiple random error patterns. As such, the ECC engine 32 can implement a BCH code or a Lie-Solomon algorithm.

During a write operation, the ECC algorithm calculates redundancy on the data sent by the host. Once the redundancy is calculated, it is added to the host data and transferred to the NAND flash page buffer. During a read operation, the ECC engine 32 recalculates the redundancy on the data from the original NAND for comparison with the old redundancy values previously stored in the flash memory. If the two redundancy are equal, then the data is correct and allows it to be transferred from the protocol interface buffer to the host CPU 20. However, if the two redundancy are not equal, the ECC engine 32 corrects the error of the data bit, and then the data can be transferred to the host CPU 20. If the number of errors is higher than the ECC correction capability, the host CPU 20 is signaled to a read failure.

The NAND interface 34 is a virtualized ECC NAND controller 26 servo to communicate with the original NAND by re-planning both the commands and addresses previously received from the host CPU 20. Thus, in a write operation, data is transferred from the protocol interface buffer to the selected flash memory. With this function, the NAND interface 34 decodes the address to redirect the received data to the selected NAND and sends the new payload of data plus ECC redundancy to the selected original NAND in the stacked memory 24. During this operation, the busy signal remains low and transitions to a high signal level at the end of the original NAND stylization job.

During a read operation, the NAND interface 34 transfers the data from the selected raw NAND to the buffer 36 in the protocol interface 30. At the same time, the ECC engine 32 processes the data to calculate the associated parity check to compare with the redundancy read from the flash memory and, if necessary, perform bit correction.

When the protocol interface 30 has a wafer enable pin and the NAND interface 34 has more than one wafer enable pin, the address is decoded to redirect the data to the selected original NAND memory device of the memory stack. On the other hand, when the protocol interface 30 has more wafer enable pins than the NAND interface 34, the address is decoded to redirect the data to the correct portion of the original NAND, depending on which wafer enable is low.

By using the virtualized ECC NAND controller 26 to perform ECC algorithms outside of the NAND flash memory stack, a flexible memory system solution can be secured in terms of current technology and number of memory devices. In fact, the virtualized ECC NAND controller 26 can continue to operate regardless of the non-volatile memory system SLC and/or MLC included in the memory stack 24. In addition, the virtualized ECC NAND controller 26 is capable of managing multiple flash NAND devices and even accommodating memory devices having different reduction levels. It should also be noted that one of the ECC correction capabilities within the virtualized ECC NAND controller 26 does not affect the flash NAND design. In addition, since one NAND memory device can be selected at a time by the solution illustrated by the architecture shown in FIG. 3, power consumption is reduced as compared to a conventional stacked architecture.

Since the new memory technology increases the number of bits stored in a single unit, it also increases the chances of reading, writing, and maintaining errors. This necessitates the use of a more complete ECC algorithm whose code has an increased correction capability. To address these technical challenges, it should be understood that the embodiments presented herein provide an architecture in which a single controller manages a NAND flash memory stack along with an ECC algorithm. This architecture allows the host CPU to drive a single memory system with a large error-free address space using a standard NAND protocol. By placing the ECC correction capability in the external controller, changes to the ECC algorithm can be facilitated without having to change the flash mask. The external controller also allows for different techniques to be used for the controller and NAND memory, and allows the memory devices to have different levels of downsizing.

While the invention has been shown and described with reference Therefore, it is to be understood that the appended claims are intended to cover all such modifications and

10. . . Communication device

12. . . RF transceiver

14. . . antenna

16. . . Processor core

18. . . Processor core

20. . . Host CPU

twenty two. . . System memory

twenty four. . . Memory stack

26. . . Virtualized ECC NAND controller

28. . . Memory interface

30. . . Agreement interface

32. . . ECC engine

34. . . NAND interface

36. . . buffer

The subject matter of the present invention has been particularly pointed out and clearly claimed in the conclusion of the specification. The organization and method of operation of the present invention, as well as the objects, features and advantages thereof, may be best understood from the following detailed description.

1 illustrates a wireless architecture incorporating a virtualized ECC NAND controller to perform an ECC algorithm and manage data transfer between a host processor and a NAND memory stack in accordance with the present invention;

2 illustrates a host processor-to-memory interface, wherein a virtualized ECC NAND controller provides functional blocks that perform both ECC algorithms and data transfers to the NAND memory stack;

Figure 3 shows further details of the virtualized ECC NAND controller.

It should be understood that the elements illustrated in the drawings are not necessarily to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, the reference numbers are repeated to refer to the corresponding or.

10. . . Communication device

12. . . RF transceiver

14. . . antenna

16. . . Processor core

18. . . Processor core

20. . . Host CPU

twenty two. . . System memory

twenty four. . . Memory stack

26. . . Virtualized ECC NAND controller

28. . . Memory interface

Claims (20)

A storage system coupled to a host, the storage system comprising: a plurality of NAND memory devices, the plurality of NAND memory devices not internally implementing an error correction code (ECC) algorithm; and a plurality of NAND memory devices An external controller that outputs a virtualized address space to the host to allow the host to drive the storage system as a single NAND memory device, even if the storage system includes a plurality of NAND memory devices, the control The device further provides a single virtualized ECC algorithm for each of the plurality of NAND memory devices. The storage system of claim 1, wherein the controller implements an ECC algorithm and does not implement a data management algorithm for average smearing and corrupted block management. The storage system of claim 2, wherein the controller includes a protocol interface circuit having a buffer to reduce delays caused by calculations of the ECC algorithm. The storage system of claim 3, wherein the protocol interface circuit manages a NAND ready/busy signal transmitted to the host processor to account for a delay of the ECC algorithm. The storage system of claim 1, wherein the controller manages one of the plurality of NAND memory devices different from a page size of the page size of the host. The storage system of claim 1, wherein the controller overwrites a command issued by the host that is not supported by the plurality of NAND memory devices. The storage system of claim 1, wherein the controller is configured to The data received by the host processor is redirected to one or more of the selected plurality of NAND memory devices. A controller for interfacing with a plurality of NAND memory devices in a storage system, the controller comprising: a protocol interface circuit for exchanging signals with a host processor; an error correction code (ECC) engine And an NAND interface for managing the plurality of NAND memories, the NAND interface configured to simulate that the plurality of NAND memory devices are not issued by the host processor In support of the command, the NAND interface is further configured to provide power to one of the plurality of NAND memory devices at a time for saving overall power consumption of the storage system. The controller of claim 8, wherein the controller is from a host NAND interface to a bridge of the plurality of NAND memory devices, wherein the host processor selects an ECC algorithm for use in the storage system The plurality of NAND memory devices. The controller of claim 8, wherein the controller manages a page size from the host processor that is different from a page size of the plurality of NAND memory devices. The controller of claim 8, wherein the controller provides a single NAND interface to the host processor-virtualized address space to allow the host to drive the storage system as a single NAND memory device, even if the storage system The plurality of NAND memory devices are included. The controller of claim 8, wherein the controller includes a protocol interface circuit having a buffer for transferring data to the host processor, the buffer having a buffering capability for reading a second data page for subsequent Parallel processing ECC algorithm execution in the read job. The controller of claim 12, wherein the protocol interface circuit manages a NAND ready/busy signal transmitted to the host processor to account for a delay of the ECC algorithm. A method of managing a NAND memory device stack that does not internally implement an error correction code (ECC) algorithm, the method comprising: exchanging signals with a host processor using one of a controller device protocol interface to allow the host The processor is in communication with a large error-free address space; a single virtualized ECC algorithm is implemented by an ECC engine block embedded in the controller device; and by a NAND interface block embedded in the controller device The command and address received from the host processor are re-planned to manage the data transfer to the NAND memory device stack. The method of claim 14, further comprising interpreting commands received from the host processor by the protocol interface block to direct storage of data from the host processor. The method of claim 14, further comprising loading a buffer in the protocol interface block, the buffer having a buffering capability to read a second data page to process the ECC algorithm in parallel in a subsequent read job carried out. A wireless communication system including a plurality of NAND memory devices, the The line communication system includes: a transceiver; a processor having first and second processor cores coupled to the transceiver; and an error correction code (ECC) controller having: an embedded a NAND interface block for receiving commands and addresses and exchanging signals with the processor; an ECC engine for implementing an ECC algorithm; and a NAND interface circuit for re-planning from the host processor Both the received command and the address are directed to data transfer with the NAND memory devices, and the NAND memory devices do not implement the ECC algorithm internally. The wireless communication system of claim 17, wherein the ECC controller further comprises a protocol interface circuit having a buffer to reduce delays caused by calculations of the ECC algorithm. The wireless communication system of claim 17, wherein the ECC controller allows the processor to redirect the data received from the processor to a selected NAND memory device when the ECC controller redirects data received from the processor The device is driven as a single NAND memory device. A wireless communication system according to claim 17, wherein the ECC controller allows the processor to manage a page size different from a page size of the NAND memory devices.