TWI465916B - Asymmetric transport system and method of heterogeneous dual-core - Google Patents

Description

Heterogeneous dual core asymmetric transmission system and method

The present invention relates to a dual core transmission system and method, and more particularly to a heterogeneous dual core asymmetric transmission system and method.

In the prior art, communication between common dual core processors uses a symmetric transmission mechanism. For example, Texas Instruments' DaVinci processor architecture, between the core of the Advanced RISC Machine (ARM) and the Digital Signal Processor (DSP) Using the shared memory method to do the bidirectional transfer of data, first divide the shared memory into two memory blocks ARM-to-DSP and DSP-to-ARM, when the ARM core transmits data to the memory block ARM After -to-DSP, it is necessary to notify the DSP core through the interrupt to read the data of the memory block ARM-to-DSP; conversely, after the DSP core transmits the data to the memory block DSP-to-ARM, it needs to pass through The interrupt informs the ARM core to read the data of the memory block DSP-to-ARM.

In the traditional data transmission method, the ARM core writes data to the memory, the DSP core reads the memory data, the DSP core writes the data to the memory, or the ARM core reads the memory data, and must use the interrupt to communicate. . Traditional technology shares memory for two-way communication, and hardware interrupts are required regardless of the traffic volume of the transmitted data, thus wasting memory usage space and hardware interruption.

The invention provides a heterogeneous dual core asymmetric transmission system. This asymmetric transmission system does not require two-way communication to use shared memory for data transmission, in order to save memory resources and hardware interruptions.

The invention further provides a heterogeneous dual-core asymmetric transmission method. The asymmetric transmission method uses shared memory for data transmission when two-way communication is not needed, thereby saving memory resources and hardware interruption use.

In order to solve the above problems, the present invention proposes a heterogeneous dual core asymmetric transmission system. This asymmetric transmission system includes shared memory, a general purpose processor, a coprocessor, and a mailbox. The general purpose processor is coupled to the shared memory. The general purpose processor writes the first data to the shared memory. The coprocessor is coupled to the shared memory. The type of coprocessor is different from the general purpose processor. The coprocessor reads the first data from the shared memory and performs arithmetic processing on the first data to obtain the second data. The co-processor transmits the second data, and the data traffic of the transmitted second data is smaller than the data traffic of the first data. The mailbox is coupled between the general-purpose processor and the co-processor, wherein the second data transmitted by the co-processor is first written to the mailbox, and then transmitted to the general-purpose processor by the mailbox.

From another point of view, the present invention proposes a heterogeneous dual core asymmetric transmission method. This asymmetric transmission method is applicable to the aforementioned asymmetric transmission system. The asymmetric transmission method includes the following steps: the general-purpose processor writes the first data to the shared memory; the co-processor reads the first data from the shared memory; and the cooperative processor performs the arithmetic processing on the first data to obtain The second data; the co-processor writes the second data to the mailbox, wherein the data flow of the second data is smaller than the data flow of the first data; and the second data of the mailbox is transmitted to the general-purpose processor.

In an embodiment of the present invention, the data flow direction of the first data is a single direction, and only the general processor writes the first data to the shared memory, and the coprocessor reads the first data from the shared memory. The data of the same amount of the first data cannot be returned from the shared memory to the general-purpose processor in the reverse direction, and the data of the same amount of the first data cannot be written from the coprocessor to the shared memory, wherein the same amount is referred to. The data is the amount of data equivalent or similar to the first data.

In an embodiment of the present invention, the data flow direction of the second data is a single direction, and only the co-processor writes the second data to the mailbox, and the general processor reads the second data from the mailbox, and cannot be from the mailbox. The data of the same amount of the second data is returned to the coprocessor in the reverse direction and the data of the same amount of the second data cannot be written from the general purpose processor to the mailbox, wherein the same amount of information is equivalent or similar to the second data. The amount of data.

In an embodiment of the invention, the shared memory includes a flag register, and the flag content of the flag register is used to record write permission, read permission, and write memory start. The position and the end position of the read memory.

In an embodiment of the invention, the general-purpose processor and the co-processor use the shared memory in a manner of polling the flag register, wherein the general-purpose processor writes according to the flag content of the flag register. In the action, the coprocessor performs a read operation according to the flag content of the flag register.

In an embodiment of the invention, the first data is a picture, and the operation of the coprocessor is to perform position detection on a local pattern in the picture, and the second data is an exact position of the partial pattern in the picture.

In an embodiment of the invention, the first data is a continuous picture, and the operation of the coprocessor is to analyze and compare two adjacent pictures in the continuous picture, and the second data is an adjacent picture in the continuous picture. Difference point.

In an embodiment of the invention, the first data is a voice data, the operation of the coprocessor is a voice compression calculation for the voice data, and the second data is the compressed voice data.

In an embodiment of the invention, the first data is a file, the operation of the coprocessor is data compression for the file, and the second data is a compressed file.

In an embodiment of the invention, the coprocessor sends a request to the mailbox to write the second data to the mailbox, and then the mailbox issues an interrupt command to the general purpose processor to cause the general purpose processor to read the second data.

Based on the above, the heterogeneous dual core asymmetric transmission system and method of the present invention uses two different types of processors. The general purpose processor transfers a large amount of data to the coprocessor through shared memory. The coprocessor performs arithmetic processing on a large amount of data to obtain a part of the data or compressed data in the large amount of data, and then transmits the data to the general purpose processor via the mailbox. The system and method of the present invention can reduce the use of memory resources and hardware interruptions because the data traffic transmitted by the two processors is asymmetric, and the shared memory is used for data transmission when two-way communication is not required.

The above described features and advantages of the invention will be apparent from the following description.

In the following embodiments, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

Please refer to FIG. 1. FIG. 1 is a block diagram of a heterogeneous dual-core asymmetric transfer system according to an embodiment of the present invention. The asymmetric transmission system 100 includes a shared memory 110, a general purpose processor GPP, a coprocessor CP, and a mailbox 120. The heterogeneous dual core is two different types of processors, that is, the type of the coprocessor CP is different from the type of the general processor GPP. The general-purpose processor GPP can have a processing function for executing a general application program, and is mainly a control guide, such as processing a user interface, interrupt processing, and the like. The coprocessor CP is mainly used for mathematical operations, and is responsible for the work of real-time, regular operation characteristics to cope with high computational requirements, such as fast Fourier transform, matrix multiplication, and so on. The coprocessor CP can be a digital signal processor (DSP), a Field Programmable Gate Array (FPGA) processor, or a complex programmable logic device (referred to as a complex programmable logic device). For CPLD).

In the above, the shared memory 110 is coupled between the general-purpose processor GPP and the cooperative processor CP. The mailbox 120 is also coupled between the general purpose processor GPP and the coprocessor CP. The general-purpose processor GPP can receive the first data DATA1 from an external data capture device (not shown) or receive the first data from a graphical user interface (GUI). The general purpose processor GPP writes the received first data DATA1 to the shared memory 110. The coprocessor CP then reads the first data DATA1 from the shared memory 110, performs mathematical operations on the first data DATA1 to obtain the second data DATA2, and then writes the second data DATA2 to the mailbox 120. Finally, the mailbox 120 transmits the second data DATA2 to the general purpose processor GPP.

It is worth noting that the transmission mechanism of this system is: (1) the data flow direction of the first data DATA1 is transmitted in a single direction (as indicated by a thick arrow), and the first data DATA1 is written by the general-purpose processor GPP only in a single direction. The shared memory 110 cannot retransmit the data of the same amount of the first data DATA1 from the shared memory 110 to the general-purpose processor GPP in the reverse direction, wherein the same amount of data referred to herein is equivalent or similar to the data amount of the first data DATA. (2) The coprocessor CP reads the first data DATA1 only from the shared memory 110, and cannot write the data of the same amount of the first data DATA1 from the coprocessor CP to the shared memory 110; (3) transmission The data flow direction of the second data DATA2 is in another direction (as indicated by a thin arrow), and the second data DATA2 is written to the mailbox 120 by the coprocessor CP in only one direction, and cannot be the same amount from the mailbox 120 in the reverse direction. The data of the second data DATA2 is then transmitted back to the coprocessor CP, wherein the same amount of data referred to herein is equal to or similar to the data size of the second data DATA2; and (4) the general purpose processor GPP reads only the second from the mailbox 120. Data DATA2 You can not write the same amount to the mailbox 120 in the second information data from a general purpose processor GPP.

Please note that there are two data flow directions (shown by thick and thin arrows) in the asymmetric transmission system 100, and the first data flow direction is from the general-purpose processor GPP via the shared memory 110 to the cooperative processor CP. The second data flow direction is from the coprocessor CP via the mailbox 120 to the general purpose processor GPP, wherein the first data DATA1 transmitted through the first data flow direction and the second data DATA2 transmitted through the second data flow direction The data flow of the second data DATA2 is much smaller than the data flow of the first data DATA1. Therefore, in the case of asymmetric transmission and high computing requirements, the asymmetric transmission system 100 is an effective technical solution for solving the problem, and can provide a more efficient transmission mechanism, and does not require two-way communication to use the shared memory 110. Data transfer, which saves memory resources and the use of hardware interrupts.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a shared memory 110 according to an embodiment of the present invention. Initially, a flag register can be planned in the shared memory 110 (Flag Registers FR, as shown, the flag register FR has a 16-byte flag content, which can be used to define: write permission Read permission, write start position of memory and end position of read memory.

For example, the first byte may be defined to determine the general processor GPP write authority or the read permission of the coprocessor CP. When the first byte value is 0, the general purpose processor GPP can write to the shared memory 110, and The coprocessor CP cannot read the data of the shared memory 110. When the first byte value is 1, the coprocessor CP can read the data of the shared memory 110, and the general processor GPP cannot write to the shared memory 110. . The second to fourth bytes may be defined as storing the start position of the general-purpose processor GPP write shared memory 110, and the fifth to seventh bytes may be defined as storing the termination position of the general-purpose processor GPP write shared memory 110. The 8th to 10th bytes may be defined as the starting position of the storage coprocessor CP to read the memory, and the 11th to 13th bytes may be defined as the storage coprocessor CP reading the end position of the shared memory 110, and other bytes are Retention can add other features.

It is worth mentioning that the flag content definition of the flag register FR is only an alternative embodiment, and those skilled in the art can also change the size and content of the flag byte according to their needs.

In view of the above, the general purpose processor GPP and the coprocessor CP can use the shared memory 110 by polling the flag value of the flag register FR. For example, the general-purpose processor GPP can perform a write operation according to the flag content of the flag register FR, and the cooperative processor CP can perform a read operation according to the flag content of the flag register FR. For example, initially, the general-purpose processor GPP reads the first byte of the flag register FR. If the first byte value is 0, the general-purpose processor GPP can write to the shared memory 110 to start the large amount to be transmitted. The data (such as the first data DATA1) is written into the shared memory 110, and after the writing is completed, the first byte value of the flag register FR is changed to 1, to allow the coprocessor CP to perform the reading operation. That is, when the general-purpose processor GPP writes the first data DATA1 to the shared memory 110, the coprocessor CP only needs to perform a polling operation, and checks the first byte at intervals to confirm whether the action can be read.

When the coprocessor CP polls and confirms that the first byte value of the flag register FR is 1, the data of the shared memory 110 is read until the read operation is completed, and then the flag is temporarily stored. The first byte value of the FR is changed to 0 to allow the general purpose processor GPP to write to the shared memory 110 data.

It is worth mentioning that, since the work of the coprocessor CP only performs mathematical operations, the usual idle time is to wait for the first data DATA1 transmitted by the general processor GPP, and to transfer the processed second data DATA2 to the general processing. GPP. This method of polling does not use the interrupt command, and the mathematical operation of the coprocessor CP can be prevented from being interrupted and the original operation can be stopped.

In addition, the second data DATA2 after the operation is transmitted to the general-purpose processor GPP before the mechanism of the mailbox 120 is required. The mechanism of this mailbox 120 is that the coprocessor CP needs to issue a request to the mailbox 120 to write the second data DATA2 to the mailbox 120. Next, after the second data DATA2 is written, the mailbox 120 issues an interrupt command to the general-purpose processor GPP to cause the general-purpose processor GPP to read the second data DATA2.

Please refer to FIG. 3. FIG. 3 is another embodiment of the asymmetric dual-core asymmetric transmission system of FIG. In this embodiment, the general purpose processor GPP receives the first data DATA1 from an external camera 132 (which may also be a camera). The first data DATA1 here is an image picture (or image data). The mathematical calculation process of the coprocessor CP is used to detect a local pattern in the image picture, for example, detecting the position of the "cross pattern" in the picture. The coprocessor CP returns the position coordinate value (x, y) of the detected "cross pattern" to the general processor GPP, where the position coordinate value (x, y) is the second data DATA2. From this embodiment, the first data DATA1 is the data amount of one picture, the cooperative processor CP performs the detection algorithm, the second data DATA2 is the position coordinate value (x, y), and the second data DATA2 passes the mechanism of the mailbox 120. And back to the general processor GPP. The mailbox 120 issues an interrupt command to the general-purpose processor GPP, and the interrupt service program of the general-purpose processor GPP receives the interrupt command. Then, the application of the general-purpose processor GPP receives the position coordinate value (x, y) of the "cross pattern".

Although several possible types have been described for the asymmetric transmission system in the above embodiments, those of ordinary skill in the art will appreciate that the application of the present invention is not limited to the above-described possible types. In other words, as long as the architecture of the asymmetric dual-core asymmetric transmission system as shown in FIG. 1 or FIG. 3 is adopted, it is in line with the spirit of the present invention. In the following, several embodiments will be described to enable those skilled in the art to further understand the spirit of the invention and to practice the invention.

Please refer to Figure 3 again. In an embodiment, if the transmitted first data DATA1 is a continuous picture, and the second data DATA2 to be returned is a difference point of adjacent pictures in the continuous picture, the coordinated processor CP may perform The detection algorithm is designed to analyze and compare adjacent two images in a continuous picture.

In another embodiment, if the asymmetric transmission system 100 performs voice compression calculation for voice data, the system can be designed such that the general-purpose processor GPP receives the voice data transmitted by the camera 132 (or a voice capture device such as a microphone). As the first data DATA1, the general-purpose processor GPP transmits the first data DATA1, the mathematical operation of the cooperative processor CP is to perform voice compression calculation for the voice data, and the returned second data DATA2 is the compressed voice data.

In another embodiment, when the transmitted first data DATA1 is a file and the second data DATA2 to be returned is a compressed file, the mathematical operation of the coprocessor CP can be designed to perform data compression for the file.

Please note that the camera 132 of FIG. 3 is merely an alternative embodiment, and may be other image capturing devices such as a camera, and of course a voice capturing device, a microphone, or a hard disk. Those skilled in the art can also change the type of data capture device according to their needs. Therefore, the application of the present invention is not limited to the above several possible types.

Please refer to FIG. 4. FIG. 4 is a flowchart of a method for asymmetric transmission of a heterogeneous dual core according to an embodiment of the present invention. This asymmetric transmission method 400 is applicable to the aforementioned asymmetric transmission system. The asymmetric transmission method 400 includes the following steps: in step S410, the general purpose processor writes the first data to the shared memory; then, in step S420, the coprocessor reads the first data from the shared memory; In step S430, the coprocessor performs mathematical operation processing on the first data to obtain the second data; in step S440, the coprocessor generates the second data to the mailbox, wherein the data flow of transmitting the second data is much smaller than Transmitting the data flow of the first data; finally, in step S450, the mailbox transmits the second data to the general purpose processor.

In summary, the asymmetric transmission system and method of the embodiments of the present invention can solve the technical problem of wasting memory resources and excessive hardware interruption in the prior art, and can provide more effective data transmission, at least having the following characteristics. :

(1) The amount of data transmitted by the general-purpose processor to the co-processor is large, and the amount of data transmitted by the co-processor to the general-purpose processor is small, and the shared memory is used for data transmission without two-way communication;

(2) Shared memory does not use an interrupt mechanism;

(3) The coprocessor only performs the operation of the mathematical algorithm. After the coprocessor executes the algorithm, the flag register can be checked to confirm whether the shared memory allows the data to be read. Therefore, it is not necessary to use the interrupt mechanism to remind the coprocessor to read the data, thereby saving the use of the interrupt. ;as well as

(4) Using the mailbox mechanism, you can save memory resources without planning the space of shared memory in advance.

The present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Heterogeneous dual core asymmetric transmission system

110. . . Shared memory

120. . . mailbox

132. . . camera

CP. . . Coprocessor

DATA1. . . First data

DATA2. . . Second data

FR. . . Flag register

GPP. . . General purpose processor

400. . . Heterogeneous dual core asymmetric transmission method

S410～S450. . . step

1 is a block diagram of an asymmetric dual core asymmetric transmission system in accordance with an embodiment of the present invention.

2 is a schematic diagram of shared memory in accordance with an embodiment of the present invention.

3 is another embodiment of an asymmetric dual-core asymmetric transmission system employing the FIG.

4 is a flow chart of a method for asymmetric transmission of heterogeneous dual cores in accordance with an embodiment of the present invention.

100. . . Asymmetric transmission system

110. . . Shared memory

120. . . mailbox

CP. . . Coprocessor

DATA1. . . First data

DATA2. . . Second data

GPP. . . General purpose processor

Claims (10)

A heterogeneous dual-core asymmetric transmission system includes: a shared memory, including a flag register, the flag content of the flag register is used to record write permission, read permission, and write memory a start position of the read memory; a general-purpose processor coupled to the shared memory, the general-purpose processor writes a first data to the shared memory; a cooperative processor coupled to the a shared memory, the type of the coprocessor is different from the general purpose processor, the coprocessor reads the first data from the shared memory, and performs arithmetic processing on the first data to obtain a second data. And transmitting the second data, wherein the data flow of the second data is smaller than the data traffic of the first data; and a mailbox coupled between the general purpose processor and the coprocessor, wherein the collaborative processing The second data transmitted by the device is first written to the mailbox, and then transmitted to the general-purpose processor by the mailbox; wherein the data direction of the first data is in a single direction, and only the general processor Writing a data to the shared memory, and reading, by the coprocessor, the first data from the shared memory, and failing to return the data of the first data to the shared memory in the reverse direction from the shared memory to the shared memory The general-purpose processor is unable to write, from the coprocessor, data that is the same amount of the first data to the shared memory, where the same amount of data is equal to the size of the first data; wherein the second data The data flow direction is a single direction, and the second data is only written by the coprocessor to the mailbox, and is processed by the universal processing. The device reads the second data from the mailbox, and cannot return the data of the second data to the coprocessor in the reverse direction from the mailbox, and cannot be the same amount of the second data from the general processor. Data is written to the mailbox, wherein the same amount of data is equivalent to the amount of data of the second data; wherein the general purpose processor and the coprocessor use the shared memory in a manner of polling the flag register The general processor performs a write operation according to the flag content of the flag register, and the coprocessor performs a read operation according to the flag content of the flag register; wherein the cooperative processor The mailbox issues a request to write the second data to the mailbox, and then the mailbox issues an interrupt command to the general purpose processor to cause the general purpose processor to read the second data. The heterogeneous dual-core asymmetric transmission system according to claim 1, wherein the first data is a picture, and the operation of the coprocessor is to perform position detection on a partial pattern in the picture, the second The data is the exact location of the partial pattern in the picture. The heterogeneous dual-core asymmetric transmission system of claim 1, wherein the first data is a continuous picture, and the operation of the coprocessor is to analyze and compare two adjacent pictures in the continuous picture. The second data is a difference point of adjacent pictures in the continuous picture. The heterogeneous dual-core asymmetric transmission system according to claim 1, wherein the first data is a voice data, and the operation of the coprocessor is a voice compression calculation for the voice data, and the second data is Compressed voice material. Asymmetric dual core asymmetry as described in claim 1 The transmission system, wherein the first data is a file, the operation of the coprocessor is data compression for the file, and the second data is a compressed file. A heterogeneous dual-core asymmetric transmission method is applicable to an asymmetric transmission system. The asymmetric transmission system includes a general-purpose processor, a shared memory, a cooperative processor, and a mailbox. The shared memory includes a flag temporary The flag of the flag register is used to record the write permission, the read permission, the start position of the write memory, and the end position of the read memory, and the type of the coprocessor is different from the a general-purpose processor, the asymmetric transmission method includes: the general-purpose processor writing a first data to the shared memory; the co-processor reads the first data from the shared memory; The data is processed to obtain a second data; the coprocessor writes the second data to the mailbox, wherein the data flow of the second data is smaller than the data flow of the first data; and the mailbox will Transmitting the second data to the general-purpose processor; wherein the data direction of the first data is in a single direction, and the first data is only written by the general-purpose processor to the shared memory And the coprocessor is configured to read the first data from the shared memory, and the data that is the same amount of the first data cannot be returned from the shared memory to the general processor in the reverse direction and cannot be coordinated from the shared data. The processor writes the data of the first data to the shared memory, wherein the same amount of data is equal to the size of the first data; wherein the data flow direction of the second data is a single direction. only Writing, by the coprocessor, the second data to the mailbox, and the general processor reads the second data from the mailbox, and cannot return the data of the second data in the reverse direction from the mailbox. Passing to the coprocessor and failing to write the same amount of data from the second data to the mailbox, wherein the same amount of data is equal to the size of the second data; wherein the general purpose processor The shared memory is used by the coprocessor to poll the flag register, wherein the general processor performs a write operation according to the flag content of the flag register, and the cooperative processor according to the The flag content of the flag register is read; wherein the coprocessor issues a request to the mailbox to write the second data to the mailbox, and then the mailbox issues an interrupt command to the general purpose processor, so that The general purpose processor reads the second data. The heterogeneous dual-core asymmetric transmission method according to claim 6, wherein the first data is a picture, and the operation of the coprocessor is to perform position detection on a partial pattern in the picture, the second The data is the exact location of the partial pattern in the picture. The heterogeneous dual-core asymmetric transmission method according to claim 6, wherein the first data is a continuous picture, and the operation of the coprocessor is to analyze and compare two adjacent pictures in the continuous picture. The second data is a difference point between adjacent two pictures in the continuous picture. The heterogeneous dual-core asymmetric transmission method according to claim 6, wherein the first data is a voice data, and the operation of the coprocessor is a voice compression calculation for the voice data, and the second data is Compressed voice material. The heterogeneous dual-core asymmetric transmission method according to claim 6, wherein the first data is a file, and the operation of the coprocessor is data compression for the file, and the second data is compressed. file.