TWI463497B - Memory access method and flash memory using the same - Google Patents

Description

Memory access method and flash memory using the same

The present invention relates to a memory access method, and more particularly to a method of object access applied to a flash memory array.

In today's fast-changing world of technology, non-volatile memory devices are widely used in a variety of electronic products; for example, flash memory is one of the most widely used non-volatile memories. Generally, the memory cell in the flash memory has a programmable threshold voltage, and the programmable threshold voltage is used to indicate the value of the data stored in the memory cell.

With the increasing demand for high-storage flash memory, flash memory arrays with three-dimensional structures have been developed. However, traditional memory access methods often face data access accuracy issues. Based on this, how to design the problem of inaccurate data access that can overcome the traditional methods is one of the directions that the industry is constantly striving for.

The invention relates to a memory access method, which is applied to a memory controller for accessing a memory array, wherein the memory array comprises a plurality of memory cells, and the memory cells are arranged in a plurality of memories. The cell string is controlled by a String Select signal. The memory access method of the present invention first provides a memory cell string bias signal and a word line line (Word-line) signal during a set period to determine a selected memory cell on the selected memory cell string; during the set period, Memory accessor related to the present invention The method further biases the remaining memory cells in the memory array into a pass transit memory (Pass Transistor). The memory access method of the present invention provides a discharge path in series with each memory cell to perform a read operation on the selected memory cell to eliminate coupling charges on at least one of the unselected memory cell strings. Accordingly, compared with the conventional memory access method, the memory access method of the present invention has an access operation capable of effectively eliminating the coupling charge on the unselected memory cell string, avoiding the coupling charge affecting the selected memory cell, and realizing The advantage of higher memory access accuracy.

According to a first aspect of the present invention, a memory access method is proposed for use in a memory controller for accessing a memory array. A plurality of memory cells in the memory array are arranged in a plurality of memory cell strings, which are controlled by a String Select signal. The memory access method includes the following steps. Providing a memory string bias signal to the selected memory cell string of the memory cell string during the set period, and providing a selected word line signal to the selected memory cell of the selected memory cell string; providing a plurality of unselected word line signals to the memory The remaining memory cells in the body array are biased to turn on the transmission transistor; and a discharge path is provided during the set period to connect to the memory cell strings to eliminate coupling charges on at least one of the unselected memory cell strings. The enable column selection signal during the reading period causes the selected memory cell string to be connected to the sensing unit via a metal bit line (Metal Bit Line) and is directed to the selected memory cell via a Voltage Sensing Scheme. The memory cell is selected for reading, wherein the read period does not overlap with the set period (Overlapped).

According to a second aspect of the present invention, a flash memory is provided, comprising a sensing unit, a memory array, and a memory controller. Memory array includes A plurality of memory cells are arranged in a plurality of memory cell strings and controlled by column selection signals. The memory controller is coupled to the memory array, and the memory controller further determines a set period and a read period, wherein the read period is not overlapped with the set period. During the set period, the memory controller provides a memory string bias signal to the selected memory cell string in the memory cell string, and provides a selected word line signal to the selected memory cell of the selected memory cell string; providing multiple unselected The word line signal is sent to the remaining memory cells in the memory array to be biased to turn on the transmission transistor; and a discharge path is provided to connect to the memory strings to eliminate at least one unselected memory cell in the memory strings The coupled charge on the string. During the reading period, the memory controller enables the column selection signal such that the selected memory cell string is connected to the sensing unit via the metal bit line, and the sensing unit is configured to select the selected memory cell on the selected memory cell via the voltage sensing mechanism. Read it.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

The memory access method of this embodiment provides a discharge path to eliminate coupling charges on the unselected memory cell strings to achieve a more accurate access operation for selecting memory cells on the selected memory cell string.

Please refer to FIG. 1 , which is a block diagram of a flash memory in accordance with an embodiment of the present invention. The flash memory 1 includes a memory array 10, a memory access circuit, and a memory controller 12. For example, the memory array 10 is a three-dimensional NAND type memory array including a plurality of memory cells. Part of the memory cell line is arranged in a plurality of memory cell strings, which are selected by corresponding multiples The switch is coupled to a common metal bit line (Metal Bit-line).

Referring to FIG. 2, a circuit diagram of a sub-area of the memory array 10 is shown. For example, memory array 10 includes metal bit lines MBL that are used to access N memory cell strings S_0, S_1, S_2, ..., and S_N-1, where N is a natural number greater than one. The N memory cell strings S_0 to S_N-1 have substantially the same circuit structure. Next, the ith memory cell string S_i is taken as an example to further the memory cell strings S_0 to S_N-1. Description, where i is an integer greater than or equal to 0 and less than N.

The i-th memory cell string S_i includes M memory cells MC(i, 0), MC(i, 1), MC(i, 2), ..., and MC(i, M-1), column selection switch SW_i , ground selection switch SWG_i, PN diode D_i and node N_i. The column selection switch SW_i and the ground selection switch SWG_i are implemented by a Metal Oxide Semiconductor (MOS) transistor, and the memory cells MC(i, 0) to MC(i, M-1) are programmable with a threshold voltage. MOS transistor is used to achieve. The source and drain of the column selection switch SW_i are connected to the metal bit line MBL and the source of the memory cell MC(i, M-1), respectively. The positive and negative terminals of the PN diode D_i are connected to the node N_i and the drain of the ground selection switch SWG_i, respectively. The source of the ground selection switch SWG_i is connected to the drain of the memory cell MC(i, 0), and the memory cells MC(i, 1) to MC(i, M-2) are sequentially connected in series to the memory cell MC. The source of (i, 0) is between the drain of the memory cell MC (i, M-1).

The control terminals of the column selection switches SW_0 to SW_N-1 corresponding to the memory cell strings S_0 to S_N-1 respectively receive the column selection signal SSL, wherein the column selection signal SSL is used to select the switches SW_0 to SW_N-1 for all the columns. Take overall control. The control terminals of the ground selection switches SWG_0 to SWG_N-1 receive the ground selection signal GSL, wherein the ground selection signal The GSL system is used to control all of the ground selection switches SWG_0 to SWG_N-1. The control terminals of the respective memory cells corresponding to the same x coordinate position receive and are controlled by the same word line signal. For example, memory cells MC(0,0), MC(1,0), MC(2,0),...,MC(N-1,0) correspond to the same x coordinate position (x=0 ), and they are all controlled by the same word line signal SWL_0.

Please refer to Figure 1 again. The memory access circuit is connected to the memory array 10 and the memory controller 12, and is controlled by the memory controller 12 to perform an access operation on the memory array 10. For example, the memory access circuit includes a drain bias circuit 14a, Y multiplexers 14b1, 14b2, a sensing unit 14c, and an X decoder 14d. The drain bias circuit 14a supplies the memory string bias voltage VB to the Y multiplexer 14b1. For example, the memory array 1 performs an access operation by using a reverse read scheme in which the memory cell string bias voltage VB corresponds to a high level voltage (eg, higher than the ground voltage GND). The Y multiplexer 14b1 is coupled to the memory controller 12 to correspondingly provide the memory string bias signals CSL_0 to CSL_N-1, wherein one of the memory string bias signals CSL_0 to CSL_N-1 corresponds to the memory string. The bias voltage VB is such that one of the corresponding memory cell strings S_0 to S_N-1 is selected as the selected memory cell string; and the remaining N-1 memory cells of the memory string bias signals CSL_0 to CSL_N-1 The bias signal corresponds to the ground voltage GND. For example, the memory string bias signal CSL_0 corresponds to the memory string bias voltage VB, and the other N-2 memory string bias signals CLS_1 to CSL_N-1 correspond to the ground voltage GND; in other words, the memory The cell string S_0 is correspondingly selected to select a memory cell string.

The X decoder 14d is controlled by the memory controller 12 to provide the column selection signal SSL, the ground selection signal GSL, and the word line signals SWL_0 to SWL_M-1. For example, one of the word line signals SWL_0 to SWL_M-1 corresponds to the selected word line voltage VS for reading for one selected memory cell on the selected memory string; and the word line signals SWL_0 to SWL_M- The remaining M-1 word line voltages in 1 correspond to the turn-on word line voltage VP such that other memory cells in the memory array 10 are biased to turn on the pass transistor. For example, the word line signal SWL_0 corresponds to the selected word line voltage VS, and the word line signals SWL_1 to SWL_M-1 correspond to the on word line voltage VP. In other words, the memory cell line in which the x coordinate position in the selected memory cell string is equal to 0 is selected as the selected memory cell.

For example, the bit line selecting the word line voltage VS is related to the threshold voltage level of each of the memory cells MC(0, 0) to MC(N-1, M-1) in the memory array 10. In one embodiment, the memory cells MC(0,0) through MC(N-1, M-1) have a threshold voltage greater than the ground voltage GND, and the selected word line voltage VS has a voltage higher than the ground voltage GND. Level. In other embodiments, the threshold voltage of the memory cells MC(0,0) to MC(N-1, M-1) may also be substantially equal to the ground voltage GND; and the selected word line voltage VS may have a ground connection correspondingly The voltage GND is substantially the same voltage level. In this embodiment, the threshold voltage of the memory cells MC(0, 0) to MC(N-1, M-1) is higher than the ground voltage GND (that is, the selected word line voltage VS is higher than that of the selected cell line VS). The case of the level of the ground voltage GND is explained, and the case where the threshold voltage of the memory cells MC(0, 0) to MC(N-1, M-1) is substantially equal to the ground voltage GND can be disclosed according to the embodiment. Analogy is obtained.

The Y multiplexer 14b2 is controlled by the memory controller 12 to provide the memory cell string current C_0 (for example, the memory cell current of the selected memory cell MC(0, 0)) transmitted through the metal bit line MBL to the sensing unit. 14c, in this way, the data value of the selected memory cell can be detected. For example, the sensing unit 14c applies a Voltage Sensing Scheme to detect data values in the selected memory cells.

The memory controller 12 is coupled to the memory array 10 via a memory access circuit and performs an access operation for a selected memory cell on the selected memory string. For example, the memory controller 12 can be implemented in the flash memory 1 in a state machine manner. Next, the timing control of the memory controller 12 will be further described by an operation example of accessing the selected memory cell as the memory cell MC (0, 0).

Please refer to FIG. 3, which is a timing diagram of related signals in FIG. The memory controller 12 determines the set period T _setup and the read period T _develop , wherein the set period T _setup and the read period T _develop do not overlap each other.

During the set period T _setup , the memory controller 12 drives the Y multiplexer 14b1 to provide the memory string bias signals CSL_0 to CSL_N-1, wherein the memory string bias signal CSL_0 corresponds to the memory string bias voltage VB, and The memory string bias signals CSL_1 to CSL_N-1 correspond to the ground voltage GND. In addition, the memory controller 12 further drives the X decoder 14d to bias the word line signal SWL_0 to the selected word line voltage VS and bias the word line signals SWL_1 to SWL_N-1 to the on word line voltage VP. . Accordingly, the memory cell CM(0,0) in the selected memory cell string S_0 is selected as the selected memory cell, and the other memory cell cells are turned on as the conduction transmission transistor.

In addition, during the set period T _setup , the column selection signal SSL and the ground selection signal GSL are supplied to the high voltage HV (eg, higher than the ground voltage GND). Accordingly, during the set period T _setup , the selected memory cell string S_0 is substantially biased to turn on the transfer transistor string.

In contrast, for the unselected memory cell strings S_1 to S_N-1, the PN diodes D_1 to D_N-1 are responsive to the memory cell string bias signals CSL_1 to CSL_N corresponding to the ground voltage GND. 1 is the deadline. Thus, before the level of the column selection signal SSL is raised enough to turn on the levels of the column selection switches SW_1 to SW_N-1, the unselected memory cells S_1 to S_N-1 are substantially floating, wherein each unselected memory cell string S_1 to S_N-1 substantially form a large capacitor, one of which receives the word line signals SWL_1 to SWL_N-1, and the other end of which is floating. To make matters worse, the word line signals SWL_1 to SWL_N-1 are simultaneously boosted to the selected word line voltage VS or the on word line voltage VP during the set period T _setup . In this way, the memory cell string voltages V(S_0) to V(S_N-1) (for example, the source or drain voltage of any one of the substantially floating unselected memory cell strings S_1 to S_N-1) will be caused. And selecting the source or drain voltage of any one of the memory cells S_0 is boosted to a high voltage level via a capacitive coupling effect.

In order to solve the case where the aforementioned memory cell string voltages V(S_0) to V(S_N-1) are increased due to the capacitive coupling effect, the column selection signal SSL is also boosted to the high voltage HV during the set period SSL. In this way, the column selection switches SW_1 to SW_N-1 are turned on correspondingly in the T _setup during the set period to connect the discharge path (formed by the metal bit line MBL and the sensing unit 14c) to the memory cell strings S_0 to S_N. -1 to correspondingly pull the memory cell string voltages V(S_0) to V(S_N-1) to the ground voltage GND, and correspondingly remove the charge generated by the capacitive coupling effect during the set period T _setup .

During the read period T _develop , the metal bit line MBL is floating, and the memory controller 12 continuously provides the enable column selection signal SSL, so that the memory cell current of the memory cell MC (0, 0) can be selected via The metal bit line MBL and the Y multiplexer 14b2 charge the capacitance seen on the metal bit line MBL such that the voltage V (MBL) of the metal bit line MBL is correspondingly boosted. The memory controller 12 further drives the sensing unit 14c to detect the voltage V (MBL) to correspondingly implement the operation of accessing the selected memory cell MC(0, 0).

In summary, the memory access method of the present embodiment can remove the charges on the unselected memory cell strings S_1 to S_N-1 via the discharge path during the set period T _setup . In this way, the memory cell current of the selected memory cell MC(0, 0) obtained during the reading period _Tdevelop can be effectively prevented from being interfered by the unselected memory cell strings S_1 to S_N-1. In this way, the memory cell current can be applied to accurately find the data value stored in the selected memory cell MC(0,0).

In the present embodiment, the case where only the two operation periods (that is, the set period T _setup and the read period T _develop ) are determined by the memory controller 12, and the corresponding operation is performed therein is taken as an example. The memory controller 12 of the present embodiment is not limited to this. In other examples, the memory controller 12 further determines the second setup period T _setup' , and the memory controller 12 is configured for the page buffer in the sensing unit 14c, and for the metal bit The line MBL is biased as shown in Figure 4. For example, the column selection signal SSL is pulled down to the ground voltage GND before the second set period T _{setup '} , according to which the column selection switches SW_0 to SW_N-1 are turned off in the second setting period T _{setup '} to perform metal The bias operation of the bit line MBL and the setting operation of the page register.

In still another example, the memory controller 12 further determines the first sub-period T _{setup_1} and the second sub-period T _{setup_2} in the set period T _setup as shown in FIG. 5. In the first sub-period T _{setup_1} , the memory controller 12 provides the memory string bias signals CSL_0 to CSL_N-1 word line signals SWL_0 to SWL_N-1. In the second sub-period T _{setup_2} , the memory controller 12 provides a discharge path via the column enable signal SSL providing the enable. In other words, the memory controller 12 provides a discharge path to remove the unselected memory strings S_1 to S_N after the operations of providing the memory string bias signals CSL_0 to CSL_N-1 and the word line signals SWL_0 to SWL_N-1. 1 on the charge.

The memory access method of this embodiment is applied to a memory controller for accessing a memory array, wherein the memory array includes a plurality of memory cells, and the memory cells are arranged in a plurality of memory strings. Controlled by the column selection signal. The memory access method of the embodiment first provides a memory cell string bias signal and a selected word line signal during the set period to determine a selected memory cell on the selected memory cell string; during the set period, the memory of the embodiment The body access method further biases the remaining memory cells in the memory array to turn on the transfer memory. The memory access method of this embodiment provides a discharge path in series with each memory cell to perform a read operation on the selected memory cell to eliminate the coupled charge on at least one of the unselected memory cell strings. Accordingly, the memory of this embodiment is compared to the conventional memory access method. The bulk access method has the advantages of effectively eliminating the coupling charge on the unselected memory cell string, avoiding the coupling charge affecting the access operation of the selected memory cell, and achieving higher memory access accuracy.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

1‧‧‧flash memory

10‧‧‧ memory array

12‧‧‧ memory controller

14a‧‧‧汲polar bias circuit

14b1, 14b2‧‧‧Y multiplexer

14c‧‧‧Sensor unit

14d‧‧‧X decoder

FIG. 1 is a block diagram of a flash memory in accordance with an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a sub-area of the memory array 10.

Figure 3 is a timing diagram of the related signals in Figure 2.

Figure 4 is a timing diagram of another related signal in Figure 2.

Figure 5 is a timing diagram of still another related signal in Figure 2.

T _setup ‧‧‧Setting period

T _develop ‧‧‧Reading period

Claims (8)

A memory access method is applied to a memory controller for accessing a memory array, wherein a plurality of memory cells in the memory array are arranged in a plurality of memory cells, and the memory strings are Controlled by a string of select signals, the memory access method includes: providing a memory string bias signal to one of the memory strings in a set period, and selecting a memory string, and Providing a select word line (Word-line) signal to one of the selected memory cells to select a memory cell; during the set period, providing a plurality of unselected word line signals to the remaining memory cells in the memory array So that it is biased into a pass transistor; during the set period, a discharge path is provided to connect to the memory strings to eliminate at least one unselected memory string in the memory strings The coupled charge is coupled; and during a read period, enabling the column select signal causes the selected memory string to be coupled to a sensing unit via a metal bit line (Metal Bit Line) and via voltage sensing System (Voltage Sensing Scheme) for the selected memory cell to the strings of the selected memory cells for read, wherein the reading period does not overlap with the period setting (Overlapped). The memory access method of claim 1, wherein the step of providing the discharge path further comprises: enabling the column selection signal such that the memory strings are simultaneously coupled to the metal bit line, and Causing the at least one unselected memory cell string via the metal The bit line is discharged. The memory access method of claim 1, further comprising: determining, in the set period, a first sub-period, wherein the step of providing the memory string bias signal and the selected word line signal, And the step of providing the unselected word line signals is performed in the first sub-period. The memory access method of claim 3, further comprising: determining a second sub-period during the set period, wherein the step of providing the discharge path is performed in the second sub-period. A flash memory comprising: a sensing unit; a memory array comprising a plurality of memory cells arranged in a plurality of memory cells, and wherein the memory strings are selected by a column (String Select) a signal controller is coupled to the memory array, and the memory controller further determines a set period and a read period, wherein the read period does not overlap with the set period (Overlapped) During the set period, the memory controller provides a memory string bias signal to one of the memory strings to select a memory string, and provides a select word line signal to the Select one of the memory cell strings to select a memory cell; The memory controller provides a plurality of unselected word line signals to the remaining memory cells in the memory array to be biased into a pass transistor (Pass Transistor); During the set period, the memory controller provides a discharge path connected to the memory strings to eliminate coupling charges on at least one of the unselected memory strings of the memory strings; and during the reading period The memory controller enables the column selection signal such that the selected memory string is connected to the sensing unit via a metal bit line, and the sensing unit is via a Voltage Sensing Scheme. The selected memory cell on the selected memory string is read. The flash memory of claim 5, wherein the memory controller enables the column of signals to be coupled to the metal bit line simultaneously by enabling the column selection signal, and causing the at least An unselected memory cell is discharged via the metal bit line to provide the discharge path. The flash memory of claim 5, wherein the memory controller further determines a first sub-period during the set period, wherein the memory controller provides the memory cell during the first sub-period The string bias signal, the selected word line signal, and the unselected word line signals. The flash memory of claim 7, wherein the memory controller further determines a second sub-period during the set period, wherein the memory controller provides the discharge during the second sub-period path.