TWI462112B - Fully-buffered dual in-line memory module with fault correction - Google Patents

Description

Fully buffered double in-line memory module with error correction

The present invention relates to memory circuits, and more particularly to methods and apparatus for improving the yield and/or operation of embedded and external memory circuits.

The background description provided herein is for the purpose of generally describing the invention. The work of the inventor of the present invention, the extent of the description in the background art, and the description of the prior art in the case of the present application are not expressly or implicitly considered to be the prior art of the present invention.

As the capacity of semiconductor memory continues to increase, it becomes more difficult to obtain a sufficiently high yield. To achieve greater memory capacity, the area of the memory chip can be increased to accommodate a larger number of memory cells. Alternatively, the density of the wafer can be increased. Increasing the density involves shrinking the size and increasing the number of memory cells on the wafer, which causes the defects to increase proportionally.

To increase yield, several techniques can be used to repair or compensate for defects. A fairly expensive technique commonly used to repair standard memory chips is the wafer testing, sorting, and patching process. The cost of capital equipment for aging and testing facilities is quite high, but can be amortized when producing standard memory chips in sufficient quantities. For lower manufacturing quantities, the cost of amortized capital equipment typically exceeds the cost of discarding defective wafers.

Embedded memory devices are also facing the problem of obtaining sufficient wafer yield. Embedded memory devices combine logic and memory on a single silicon wafer and are typically not manufactured in large quantities. A wafer sorting/testing device, aging device, and repair facility typically used with a large number of standard memory devices is not economically viable. When a defect occurs on an embedded device, the device is typically discarded.

Each memory cell of an embedded device typically has more defects than standard memory. This part is typically incompatible with processing techniques used for logic and processing techniques used for memory. Most of the defects in embedded devices occur in memory because most of the wafer area is used in memory. For traditional logic devices, the primary yield is typically about 20%.

Referring now to Figure 1, a system on a wafer (SOC) 10 typically includes logic 12 and embedded memory 14 fabricated on a single wafer or microchip. For example, the SOC 10 can be used for a disc drive and includes: a read channel, a hard disk controller, an error correction coding (ECC) circuit, a high speed interface, and system memory. Logic 12 may include standard logic modules provided by the manufacturer and/or logic modules designed by the customer. Embedded memory 14 typically includes static random access memory (SRAM), dynamic random access memory (DRAM), and/or non-volatile memory, such as flash memory.

Referring now to Figure 2, the lower wafer yield portion is due to the smaller size of the memory cells in embedded memory 14. Small memory cells are used to reduce wafer size and cost. Typical defects include a random single bit failure as described at 16. For a 64Mb memory module, a random single bit failure of 1000 orders of magnitude can occur. Other defects include bit line defects shown at 18 and 20. Although bit line and word line defects occur less frequently than random single bit failures 16, they are easier and less expensive to repair.

Referring now to FIG. 3, embedded memory 14 typically includes a random data portion 24 and a cache data portion 26. The bits stored in the random data portion 24 are individually accessed. Instead, the bits stored in the cache data portion 26 are accessed in a manner having, for example, a 16 or 64 bit minimum size block.

To improve reliability, an error correction coding (ECC) circuit 28 can be used. The ECC coded bit 30 is used for ECC coding. For example, 2 extra bits are used for 16 bits, and 8 extra bits are used for 64 bits. The ECC circuit 28 requires that data be written to or read from the embedded memory 14 in blocks having the smallest size. Therefore, the ECC circuit 28 and the error correction encoding/decoding cannot be used in the random data portion 24. When accessing the random data portion 24, the ECC circuit 28 is disabled as outlined at 32. The ECC coded bit 30 also increases the cost of manufacturing memory and reduces the number of accesses.

Since each of the bits in the random data portion 24 can be read individually, a single bit failure in the random data portion 24 is problematic. During the wafer sorting test, if a single bit failure is detected in the random data portion 24, a fix to the SOC 10 must be implemented, which substantially increases the SOC 10 cost.

Memory, such as dynamic random access memory (DRAM) and/or other memory types, includes such memory cells, which may include capacitors, transistors, and/or other charge storage devices. When the memory unit is charged, the unit stores the bit "1", and when the memory unit is not charged, the memory unit stores the bit "0" (or vice versa). The memory unit can be configured in the form of a data block, such as a page including a plurality of memory units.

The charge of the memory cell tends to leak over time. Therefore, this type of memory unit needs to be updated on a periodic basis. The memory system relies on the capabilities of the memory unit to maintain charge during the period between updates. If the memory unit cannot maintain sufficient charge during the memory update, the data will be lost. Some systems implement updates at one data block or page at a time. Testing can be performed to ensure that the memory cells can maintain sufficient charge during the memory update.

It takes many milliseconds to find weak memory cells in the memory IC. Normal access to the memory unit must be terminated during the test time. When the update to a particular memory unit is terminated, access to the entire memory data block or page containing the memory unit must also be terminated.

A memory module includes: a first memory that stores data in a memory block; a second memory that temporarily stores at least one of the data from the memory blocks; and a third memory, And a relationship between an address of at least one of the memory blocks in the first memory and a corresponding address from at least one of the memory blocks in the second memory. The storage capacities of the second and third memories are smaller than the storage capacity of the first memory. The control module transmits the data in at least one of the memory blocks in the first memory to the second memory, and stores the at least one data in the memory block according to the relationship during the test to The second memory and the data retrieved from the second memory.

In other features, the content addressable memory (CAM) stores the address of the defective memory location in the first memory and stores and retrieves the data of the defective memory locations. The first memory communicates with the read data bus and the read address bus. The control module selectively generates a first matching signal when the read address on the read address bus is matched with the address stored in the third memory, and outputs the corresponding address from the second memory The data read. The multiplexer selectively outputs the read data from the second memory to the read data bus according to the first matching signal.

Among other features, content addressable memory (CAM) communicates with a read address bus, a read data bus, and a multiplexer. The CAM selectively generates a second matching signal when the read address on the read data bus bar matches the stored address in the CAM, and outputs the data related to the stored address to the multiplexer . The CAM has a smaller memory capacity than at least one of the memory blocks. The write data bus and the write address bus communicate with the first memory. The control module selectively generates the first matching signal when the write address on the write address bus matches the address stored in the third memory. The multiplexer selectively writes the data of the write address bus to the second memory according to the first matching signal. Content addressable memory (CAM) communicates with write address bus, write data bus, and multiplexer. The CAM selectively generates a second matching signal when the write address on the write data bus matches the stored address in the CAM, writes the data to the CAM, and associates the write address from the write data bus. . The CAM has a smaller capacity than the at least one of the memory blocks. The fully buffered dual in-line memory module (FB DIMM) includes the memory module.

In other features, the first buffer module buffers control signals received from the memory control module. At least one of the control module, the second memory, the third memory, and the multiplexer is integrated with the first buffer module in the integrated circuit. Y memory volume circuits (ICs) are in communication with the first buffer module, where Y is an integer greater than one. Each of the Z memory modules includes a buffer module, wherein the Z-1 buffer modules of the Z memory modules communicate with the previous one of the Z memory modules, and wherein The first of the Z memory modules communicates with the first buffer module, and wherein Z is an integer greater than zero. Each memory block includes data paging. The first, second, and third memory and control modules are disposed on the printed circuit board. The printed circuit board includes an edge connector. A device includes: the memory module, and a socket housing the edge connector. The control module tests at least one of the memory blocks.

A method for operating a memory module, comprising: storing data in a memory block of a first memory; temporarily storing data from at least one of the memory blocks into a second memory; The relationship between the address of at least one of the memory blocks in the first memory and the corresponding address of the data from at least one of the memory blocks in the second memory is stored in the third memory The storage capacity of the second and third memory is smaller than the storage capacity of the first memory; and the data in the at least one of the memory blocks in the first memory is selectively transmitted to the second memory; And storing the at least one of the data in the memory block to the second memory and extracting the data from the second memory according to the relationship during the test.

In other features, the method includes storing an address of the defective memory location in the first memory in a content addressable memory (CAM); and using the CAM to store and retrieve the defective memory Location information. The method includes providing a read data bus and a read address bus; selectively generating a first match signal when the read address on the read address bus matches the address stored in the third memory And outputting read data from the second memory corresponding to the address; and selectively reading the read data from the second memory to the read data bus according to the first matching signal.

In other features, the method includes providing a content addressable memory (CAM) that communicates with a read address bus, a read data bus, and a multiplexer. The CAM selectively generates a second match signal when the read address on the read data bus matches the stored address in the CAM, and outputs the data associated with the stored address to the multiplexer. The CAM data block has a smaller memory capacity than at least one of the memory blocks. The method further includes: providing a write data bus and a write address bus; selectively generating a first match signal when the write address on the write address bus matches the address stored in the third memory And selectively writing the data from the write address bus to the second memory according to the first matching signal.

In other features, the method includes providing a content addressable memory (CAM) that communicates with a write address bus, a write data bus, and a multiplexer. The CAM selectively generates a second matching signal, writes the data to the CAM, and associates the write from the write data bus when the write address on the write data bus matches the stored address in the CAM. Address. The CAM has a smaller capacity than the at least one of the memory blocks. The method includes providing a first buffer module that buffers control signals received from a memory control module for a memory module. At least one of the control module, the second memory, the third memory, and the multiplexer is integrated with the first buffer module in the integrated circuit. Each of these memory modules includes data paging.

In other features, the method includes disposing the first, second, and third memory and control modules on a printed circuit board, the printed circuit board including an edge connector. The control module tests at least one memory block.

A memory module includes: a first storage device for storing data in a memory block; a second storage device for temporarily storing data from at least one of the memory blocks; and a third storage device, a relationship between an address of at least one of the memory blocks in the first memory and a corresponding address of the material from at least one of the memory blocks in the second memory, wherein The storage capacity of the second and third storage devices is smaller than the storage capacity of the first storage device; and the control device is configured to selectively transmit the data in the at least one of the memory blocks in the first storage device to the second storage And means for storing, during the testing, the at least one of the data in the memory block to the second storage device and extracting the data from the second storage device in accordance with the relationship.

In other features, the content addressable storage device is configured to store an address of a defective memory location in the first storage device and to store and retrieve data for the defective memory locations. The first storage device communicates with the read data bus and the read address bus. The control device selectively generates a first matching signal when the read address on the read address bus is matched with an address stored in the third storage device, and outputs a second storage device from the corresponding address Reading data. The multiplex device selectively receives the first match signal when the first match signal is generated, and outputs the read data from the second storage device to the read data bus. This content can store the data stored in the storage device and communicate with the read address bus, the read data bus, and the multiplexer. The content addressable storage device selectively generates a second matching signal when the read address on the read data bus is matched with the address stored in the content addressable device, and is associated with the stored address The data is output to the multiplexer. The content addressable device has a smaller memory capacity than at least one of the memory blocks.

In other features, the write data bus is in communication with the write address bus and the first storage device. The control device selectively generates the first match signal when the write address on the write address bus is matched with the address stored in the third storage device. The multiplex device selectively receives the first match signal when generating the first match signal and is operative to write the data from the write address bus to the second storage device. The content addressable storage device stores the data and communicates with the write address bus, the write data bus, and the multiplexer. The content addressable storage device selectively generates a second matching signal, writes the data, and associates the stored address with the data when the write address on the write data bus matches the stored address. The content addressable storage device has a smaller capacity than the at least one of the memory blocks.

In other features, a fully buffered dual in-line memory module (FB DIMM) includes the memory module. The first buffer device buffers the control signal. At least one of the control device, the second storage device, the third storage device, and the multiplex device is integrated with the first buffer device in the integrated circuit. Y memory volume circuits (ICs) communicate with the first buffer device, and Y is an integer greater than one. Each of the Z memory modules includes a buffer device for buffering. Z-1 buffer devices in the Z memory modules communicate with the previous one of the Z memory modules. The first of the Z memory modules communicates with the first buffer device, and Z is an integer greater than zero. Each memory block includes data paging. The first, second, and third memory devices, and the control device are disposed on the printed circuit board. The printed circuit board includes an edge connector. A device includes: the memory module, and a socket housing the edge connector. The control device tests at least one memory block.

A memory module includes: a first memory, a second memory, and a non-volatile memory including a memory block. The control module stores the data from the at least one of the memory blocks in the second memory at the second address during the test of at least one of the memory blocks having the first address, And storing the first address and the second address in the non-volatile memory. The content addressable memory (CAM) stores the address of the defective memory location in the first memory, and stores and retrieves data for the memory location of the defect.

In other features, the storage capacity of the second memory and the non-volatile memory is less than the storage capacity of the first memory. The CAM has a memory capacity that is less than at least one of the memory blocks. The control module selectively tests at least one of the memory blocks. The first memory communicates with the read data bus and the read address bus. The control module selectively generates a first matching signal when the read address on the read address bus is matched with an address stored in the non-volatile memory, and the output is from the corresponding address Reading data from two memories. The multiplexer selectively outputs the read data from the second memory to the read data bus according to the first matching signal. The CAM communicates with the read address bus, the read data bus, and the multiplexer. The CAM selectively generates a second matching signal when the read address on the read data bus matches the stored address in the CAM, and outputs the data associated with the stored address to the multiplexer.

In other features, the write data bus and the write address bus are in communication with the first memory. The control module selectively generates a first match signal when the write address on the write address bus matches the address stored in the non-volatile memory. The multiplexer selectively writes the data from the write address bus to the second memory according to the first matching signal. The CAM selectively generates a second matching signal when the write address on the write data bus matches the stored address in the CAM, writes the data to the CAM, and associates the stored address with the data. . The fully buffered dual in-line memory module (FB DIMM) includes the memory module.

In other features, the first buffer module buffers the control signal. At least one of the control module, the second memory, and the non-volatile memory is integrated with the first buffer module in an integrated circuit. Y memory volume circuits (ICs) are in communication with the first buffer module, where Y is an integer greater than one. Each of the Z memory modules includes a buffer module, wherein the Z-1 buffer modules of the Z memory modules communicate with the previous one of the Z memory modules, and wherein the Z The first of the memory modules is in communication with the first buffer module, and wherein Z is an integer greater than zero. Each of these memory blocks includes a data page. The first memory, the second memory, the non-volatile memory, and the control module are disposed on a printed circuit board including the edge connector. A device includes: the memory module, and a socket that receives an edge connector.

A method for operating a memory module, comprising: providing a first memory, a second memory, and a non-volatile memory including a memory block; testing a memory block having a first address And storing at least one of the data from the memory block in the second memory at the second address, and storing the first address and the second address in the non-volatile memory Storing the address of the defective memory location in the first memory into the content addressable memory (CAM); and storing the data of the defective memory location in the CAM and extracting data from the CAM.

In other features, the storage capacity of the second memory and the non-volatile memory is less than the storage capacity of the first memory. The CAM has a memory capacity that is less than at least one of the memory blocks. The control module selectively tests at least one of the memory blocks. The method further includes: providing a read data bus and a read address bus; when the read address on the read address bus matches the address stored in the non-volatile memory, selectively Generating a first matching signal, and outputting read data from the second memory corresponding to the address; selectively outputting the read data from the second memory to the read data bus according to the first matching signal; And selectively generating a second matching signal when the read address on the read data bus matches the stored address in the CAM, and outputting the data related to the stored address from the CAM to the end Work tool.

In other features, the method includes: providing a write data bus and a write address bus; when the write address on the write address bus matches the address stored in the non-volatile memory, selectively Generating a first match signal; and selectively writing data from the write address bus to the second memory in accordance with the first match signal. The CAM selectively generates a second matching signal when the write address on the write data bus matches the stored address in the CAM, writes the data to the CAM, and stores the stored address in the CAM. This information is relevant. The method includes providing a first buffer that buffers control signals received from a memory controller for a memory module. The method includes integrating at least one of the control module, the second memory, and the non-volatile memory with the first buffer module in an integrated circuit. Each memory block includes data paging.

A memory module includes: a first storage device for storing data as a memory block; a second storage device for storing data; and a non-volatile storage device for storing data. The control device saves data from at least one of the memory blocks in the first memory at the first address to the second during testing of at least one of the memory memory blocks having the first address The second storage device at the address stores the first address and the second address into the non-volatile storage device. The content addressable storage device stores the address of the defective memory location into the first storage device and stores and retrieves the data of the defective memory location.

In other features, the storage capacity of the second storage device and the non-volatile storage device is less than the storage capacity of the first storage device. The content addressable storage device has a memory capacity that is less than at least one of the memory blocks. The control device selectively tests at least one of the memory blocks. The first storage device communicates with the read data bus and the read address bus. The control device selectively generates a first matching signal when the read address on the read address bus is matched with an address stored in the non-volatile storage device, and the output is from the second corresponding to the address Reading data from the storage device. The multiplex device outputs the read data from the second memory to the read data bus according to the first matching signal. This content can address the storage device with the read address bus, the read data bus, and the multiplexer. The content addressable storage device selectively generates a second matching signal when the read address on the read data bus is matched with the stored address in the content addressable device, and the stored address is The relevant data is output to the multiplexer.

In other features, the write data bus and the write address bus are in communication with the first storage device. The control device selectively generates a first match signal when the write address on the write address bus matches the address stored in the non-volatile storage device. The multiplexing device selectively writes the data from the write address bus to the second storage device according to the first matching signal. The content addressable storage device selectively generates a second matching signal to write the data to the content addressable device when the write address on the write data bus matches the stored address in the content addressable storage device And the stored address is associated with the material. The fully buffered dual in-line memory module (FB DIMM) includes the memory module.

In other features, the first buffer device buffers the control signal. At least one of the control device, the second storage device, and the non-volatile storage device is integrated with the first buffer device in an integrated circuit. Y memory volume circuits (ICs) are in communication with the first buffer device, where Y is an integer greater than one. The Z memory modules each include a buffer device for buffering. Z-1 buffer devices in the Z memory modules communicate with the previous one of the Z memory modules. The first of the Z memory modules communicates with the first buffer device, and Z is an integer greater than zero. Each of these memory blocks includes a data page. The first storage device, the second storage device, the non-volatile storage device, and the control device are disposed on a printed circuit board including the edge connector. A device includes: the memory module, and a socket that receives an edge connector.

A memory system includes: a first memory, the first memory including a memory unit. The content addressable memory (CAM) includes: a CAM memory unit that stores some of the addresses selected in the memory unit, and stores the data having the address into corresponding ones of the CAM memory units, and Some of the corresponding CAM memory cells retrieve data with this address. The adjustment update module stores data from some of the selected memory cells into the CAM memory unit to increase or maintain the time period between updating the memory units.

In other features, the adjustment update module uses G of the CAM memory cells to store G from the memory cells to maintain a time period between updates to the memory cells, where G is greater than or equal to 1 The integer. The adjustment update module uses H of the CAM memory cells to store H data from the memory cells, and H is an integer greater than or equal to 1, and selectively increases the update between the memory cells. During the time. The test module communicates with the first memory and the adjustment update module and tests the memory unit using at least one update rate.

In other features, the memory system further includes: a second memory and a non-volatile memory, wherein the first memory includes a memory block. During at least one test of the memory block having the first address, the control module stores the data from the at least one of the memory blocks into the second memory at the second address, and the first And the second address is stored in non-volatile memory. In other features, the capacity of the second memory and the non-volatile memory is less than the capacity of the first memory.

In other features, the CAM has a smaller memory capacity than at least one of the memory blocks. The control module selectively tests at least one of the memory blocks. A fully buffered dual in-line memory module (FB DIMM) includes the memory system. The first buffer module buffers the control signal. At least one of the control module, the second memory, the non-volatile memory, and the CAM is integrated into the integrated circuit together with the first buffer module. Y memory volume circuits (ICs) communicate with the first buffer module, and Y is an integer greater than one. Each of the Z memory modules includes a buffer module, wherein the Z-1 buffer modules of the Z memory modules communicate with the previous one of the Z memory modules, and The first of the Z memory modules communicates with the first buffer module, and Z is an integer greater than zero. Each of these memory modules includes a data page. The first memory, the second memory, the non-volatile memory, and the control module are disposed on a printed circuit board including the edge connector.

A method for operating a memory system, comprising: providing a first memory including a memory unit, and a CAM including a content addressable memory (CAM) unit; storing some of the selected addresses of the memory unit to the CAM Storing data having the address into a corresponding one of the CAM memory cells; extracting data having the address from a corresponding one of the CAM memory cells; and selecting from the selected one of the memory cells Some of the data is stored in the CAM memory unit to increase or maintain the time period between updating the memory units.

In other features, the method includes using G of the CAM memory cells to store data from the G cells in the memory cell to maintain a time period between updating the memory cells, and G is greater than or equal to 1 The integer. The method includes using H of the CAM memory cells to store H data from the memory cells (and H is an integer greater than or equal to 1). The method includes selectively updating a time period between memory cells. The method includes testing the memory unit using at least one update rate.

In other features, the first memory comprises a memory block. The method further includes: providing a second memory and a non-volatile memory; storing at least one of the memory blocks from the memory block during at least one of testing the memory blocks having the first address The second memory in the second address, and storing the first and second addresses in the non-volatile memory; storing the address of the defective memory location in the first memory to the content Addressing memory (CAM); and storing the data of these defective memory locations in the CAM and extracting the data from the CAM. The storage capacity of the second memory and the non-volatile memory is smaller than the storage capacity of the first memory. The CAM has a smaller storage capacity than at least one of the memory blocks. The control module selectively tests at least one of the memory blocks.

The method further includes: providing a first buffer for buffering control signals received from a memory controller for the memory system; and storing the second memory and the non-volatile memory At least one is integrated with the first buffer module in an integrated circuit. Each memory block includes data paging.

A memory system includes: a first storage device for storing data and including a memory unit; and a content addressable storage device for providing a second memory unit for storing selected bits of the memory unit An address for storing data having the address into a corresponding one of the second memory unit, and for extracting data having the address from a corresponding one of the second memory units; and adjusting the updating device For storing data from selected ones of the memory cells into the second memory unit to increase or maintain a time period between updating the memory cells.

In other features, the adjustment update device uses G of the second memory cells to store data from the G cells in the memory cell to maintain a time period between updates to the memory cells, and G is greater than or equal to An integer of 1. The adjustment updating device uses H of the second memory cells to store H data from the memory cells (and H is an integer greater than or equal to 1), and selectively increases between the updated memory cells. During the time. The test device is in communication with the first storage device and the adjustment update device to test the memory unit using at least one update rate.

In other features, the first storage device stores the data as a memory block, and further includes a second storage device for storing data and a non-volatile storage device for storing data. During testing at least one of the storage blocks having the first address, the control device stores the data from at least one of the memory blocks in the first memory at the first address to the second address. In the second storage device, the first and second addresses are stored in the non-volatile storage device. The content addressable storage device stores the address of the defective memory location into the first storage device, and stores and retrieves the data of the defective memory location. The storage capacity of the second device and the non-volatile device is less than the storage capacity of the first storage device. The content addressable storage device has a smaller memory capacity than at least one of the memory blocks. The control device selectively tests at least one of the memory blocks.

In other features, a fully buffered dual in-line memory module (FB DIMM) includes the memory system. The first buffer device buffers the control signal. At least one of the control device, the second storage device, the non-volatile storage device, and the content addressable storage device is integrated into the integrated circuit together with the first buffer device. The Y memory volume circuits (ICs) communicate with the first buffer device, and Y is an integer greater than one. Each of the Z memory modules includes a buffer device for buffering, wherein Z-1 buffer devices of the Z memory modules communicate with a previous one of the Z memory modules, And the first of the Z memory modules communicates with the first buffer module, and Z is an integer greater than zero. Each of these memory modules includes a data page. The first device, the second device, the non-volatile device, and the control device are disposed on a printed circuit board including the edge connector.

A memory system includes a first memory, the first memory including memory cells selectively updated at an update rate. The test module tests the operation of the memory unit at the update rate and recognizes T inoperable in the memory unit when updated at the update rate, and T is an integer greater than zero. The content addressable memory (CAM) includes D CAM memory cells, and D is an integer greater than or equal to one. The adjustment update module selectively adjusts the update rate of the first memory according to T and D.

In other features, the adjustment update module increases the update rate of the first memory when T is greater than D. The adjustment update module decreases the update rate of the first memory when T is less than the first threshold, wherein the first threshold is less than D. The adjustment update module decreases the update rate of the first memory when T is greater than the first threshold and less than the second threshold, wherein the second threshold is greater than the first threshold and less than D. The adjustment update module maintains the update rate of the first memory when T is greater than the second threshold and less than D. The CAM stores the addresses of the T memory cells, stores the data having the address into the T of the CAM memory cells, and extracts the bits from the T of the CAM memory cells. Information on the address. The adjustment update module uses T of the D CAM memory cells to store data from the T memory cells to maintain a time period between updates to the memory cells. The adjustment update module uses T of the D CAM memory cells to store data from the T memory cells and selectively increases the time period between updating the memory cells.

In other features, the memory system further includes a second memory and a non-volatile memory, wherein the first memory includes a memory block. While testing at least one of the memory blocks having the first address, the control module stores the data from the at least one of the memory blocks to the second memory at the second address. And storing the first and second address addresses in non-volatile memory. These memory blocks include data paging.

A method for operating a memory system, comprising providing a first memory, the first memory comprising a memory unit selectively updated according to an update rate; and when updating at the update rate, testing the memory at the update rate The operation of the body unit to identify T inoperable in the memory unit when updated at the update rate, where T is an integer greater than zero; providing a CAM comprising D content addressable memory (CAM) units, Where D is an integer greater than or equal to 1; and the update rate of the first memory is selectively adjusted in accordance with T and D.

In other features, the method includes selectively increasing the update rate of the first memory when T is greater than D. The method includes selectively reducing an update rate of the first memory when T is less than the first threshold, wherein the first threshold is less than D. The method includes selectively reducing an update rate of the first memory when T is greater than the first threshold and less than the second threshold, wherein the second threshold is greater than the first threshold and less than D. The method includes maintaining an update rate of the first memory when T is greater than the second threshold and less than D.

In other features, the method includes storing an address of the T memory cells in the CAM; storing the data having the address in the T of the CAM memory cells; and from the D CAM memories The data with this address is retrieved from T in the unit. The method includes using T of the D CAM memory cells for storing data from the T memory cells to maintain a time period between updating the memory cells. The method includes: using T of the D CAM memory cells to store data from the T memory cells; and selectively increasing the time period between updating the memory cells.

In other features, the method includes providing a second memory and a non-volatile memory, wherein the first memory comprises a memory block; and during testing at least one of the memory blocks having the first address And storing data from at least one of the memory blocks into a second memory at the second address, and storing the first and second address addresses in the non-volatile memory. Each of these memory blocks includes a data page.

A memory system includes: a first storage device for storing data, and for providing a memory unit selectively updated at an update rate; and a test device for testing the memory unit at the update rate And for identifying T that are inoperable in the memory unit when updated at the update rate, and T is an integer greater than zero; the content addressable storage device is for storing data and for providing D a second memory unit, and D is an integer greater than or equal to 1; and an adjustment updating device that selectively adjusts an update rate of the first storage device in accordance with T and D.

In other features, the adjustment update device increases the update rate of the first storage device when T is greater than D. The adjustment update device reduces the update rate of the first storage device when T is less than the first threshold, wherein the first threshold is less than D. The adjustment updating device decreases the update rate of the first storage device when T is greater than the first threshold and less than the second threshold, wherein the second threshold is greater than the first threshold and less than D. The adjustment update device maintains the update rate of the first storage device when T is greater than the second threshold and less than D. The CAM stores the addresses of the T memory cells, stores the data having the address into the T of the T second memory cells, and extracts from the T of the D second memory cells. Information on this address. The adjustment update device uses T of the D second memory cells to store data from the T memory cells to maintain a time period between updating the memory cells. The adjustment update device uses T of the D second memory cells to store data from the T memory cells and selectively increases the time period between updating the memory cells.

In other features, the memory system includes: a second storage device for storing data; a non-volatile storage device for storing data in a non-volatile manner, wherein the first storage device includes a memory block; and the control device And storing, during testing of at least one of the storage device blocks having the first address, data from at least one of the storage device blocks to a second storage device at the second address, And storing the first and second addresses in the non-volatile storage device. Each of these memory blocks includes a data page.

Further areas of applicability of the present invention will be apparent from the detailed description provided below. The detailed description and the specific examples are intended to be illustrative and not restrictive

A more complete understanding of the invention may be obtained by

The embodiments described below are merely exemplary in nature and are not intended to limit the invention, its application, or use. For the sake of clarity, the same reference numbers are used in the figures to identify similar elements. As used herein, the term: a module, circuit, and/or device means: a special purpose integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and a memory that is executed. One or more software or firmware programs, combined logic circuits, and/or other suitable components that provide the described functionality. As used herein, the phrase "at least one of A, B, and C" shall be taken to mean the use of non-exclusive logic or (OR) logic (A or B or C). It is to be understood that the steps in one method may be performed in a different order without changing the principles of the invention.

Referring now to Figures 4A and 4B, there is shown a system on wafer (SOC) 50 in accordance with the present invention. The SOC 50 includes logic 52, embedded memory 54, swap circuit 56, and error correction coding (ECC) circuitry 58 that are fabricated on a single wafer or microchip. The embedded memory 54 includes a random data portion 60 and a cache data portion 62. The cache data portion 62 is divided into a plurality of blocks 64-1, 64-2, ..., and 64-n. The size of the n blocks may be equal to, greater than, or less than the size of the random data portion 60. As can be appreciated, the random data portion 60 can also be divided into a plurality of blocks.

Initially, the random data portion 60 of the SOC 50 can be located in the first or top position in the embedded memory 54. If a defect is detected in the random data portion 60 during the initial test or later use, the random data portion 60 is exchanged with one of the n blocks 64 in the cache data portion 62. The defective block is logically preferably moved to the end of the cache data portion 62 so that it is less frequently used. If the random data portion 60 is larger than the block 64, one or more blocks 64 may be used. Preferably, the size of such blocks 64 is an integer multiple of the size of the random data portion 60.

For example, in Figure 4B, the location of the random data portion 60 has been physically exchanged with the first block 64-1. If additional defects are subsequently detected in the random data portion 60, the random data portion 60 can be physically exchanged with other blocks in the cache data portion 62. The block containing the random data portion 60 of the embedded memory 54 is tested to determine if there is a defect. The location of the defect is not important. If there is a defect, another block in the embedded memory is used.

More specifically, logic 52 generates a logical address (LA) that is output to switching circuit 56. Switching circuit 56 uses the LA if the exchange has not been previously implemented. Otherwise, switch circuit 56 replaces the LA with a physical address (PA). If the address corresponds to the random data portion 60, the switch circuit 56 disables the ECC circuit 58 (the random data portion 60 does not use ECC). If the address corresponds to block 64 of cache data portion 62, the switching circuit enables ECC circuit 58 and implements error correction coding (ECC). Memory test circuit 68 can be provided to test memory 54 during manufacture, assembly, operation, and/or boot. Alternatively, the test can be performed by logic circuit 52. As can be appreciated, testing of other memory circuits can be performed in a similar manner as disclosed below.

Referring now to Figure 5, a memory circuit 69 in accordance with the present invention is shown. Address data from logic circuit 52 and/or memory interface is input to CAM 70 and multiplexer 72 during read/write operations. If the address matches the address stored in CAM 70, CAM 70 informs the matching address via matching line 74. The CAM outputs an alternate address corresponding to the matched address. The multiplexer 72 selects the alternate address from the CAM for output to the memory 80. If there is no match, multiplexer 72 outputs the address from logic 52. As can be appreciated, memory 80 can be similar to memory 54, standard memory, memory with ECC bits, or any other electronic storage in Figures 4A and 4B.

Referring now to Figure 6, 100 generally shows the steps for operating embedded memory 54 of SOC 50. Control begins in step 102. In step 104, control determines if embedded memory 54 is being accessed by logic 52. If not, control returns to step 104. Otherwise, control determines in step 106 whether the logical address is in the exchange table of switch circuit 56. If so, switch circuit 56 sets the address equal to the PA in the exchange table in step 108. Otherwise, the address is set equal to LA in step 110.

Control continues to step 112 where control determines if the address is part of the cache data portion 62. If so, control continues to step 114 and ECC circuit 58 is enabled. If not, the ECC circuit 58 is disabled in step 116. The data is returned in step 118.

Referring now to Figure 7, an embedded memory circuit 150 in accordance with conventional techniques is shown. The embedded memory circuit 150 includes a memory interface 154 having address and control inputs 156 and 158, a data input 160, and a data output 162. The memory interface 154 is connected to the memory 166. Memory interface 154 is formed on a single wafer with memory 166 and other logic (not shown).

Referring now to Figure 8, an external memory circuit 170 in accordance with conventional techniques is shown. External memory circuit 170 includes a memory interface 174 having address and control inputs 176 and 178: data input 180; and data output 182. Memory interface 174 is coupled to memory 186. Memory interface 174 and memory 186 are not formed on a single wafer as shown by dashed line 190. Memory interface 174 is coupled to logic (not shown).

As can be appreciated, problems arise when the memory locations in memories 166 and 186 become defective. Error correction coding (ECC) can be used when reading data from a memory block or writing data to a memory block in the form of data blocks (for example, 16 and 64 bits). However, additional ECC bits must be added to each memory block, which greatly increases the size of the memory. In addition, ECC encoding/decoding circuitry must be added to the memory circuits 150 and 170, which increases the cost of the memory circuitry. The encoding/decoding algorithm also increases the read/write access time.

Referring now to Figure 9, an embedded memory circuit 200 in accordance with the present invention is shown. The embedded memory circuit 200 includes a first memory 202, a memory interface 204, and a second memory 206. The second memory 206 includes a semiconductor memory such as SDRAM, NRAM, or any other suitable memory. The first memory 202 includes: a first address and control inputs 208 and 210; a data input 212; and a data output 214. The memory interface 204 includes a second address and control inputs 220 and 222; a data input 224; and a data output 228. The first memory 202 is coupled to logic 229.

Referring now to Figure 10, an external memory circuit 230 in accordance with the present invention is shown. The embedded memory circuit 230 includes a first memory 232, a memory interface 234, and a second memory 236. As can be appreciated, the first memory 232 and the memory interface 234 are not formed on a single wafer or microchip as shown by dashed line 237. The first memory 232 includes: a first address and control inputs 238 and 240; a data input 242; and a data output 244. The memory interface 234 includes: a second address and control inputs 250 and 252; a data input 254; and a data output 258. The first memory 232 is coupled to logic 259.

The first memory 202 and 232 are preferably content addressable memory (CAM) or related memory. A CAM is a storage device that can be addressed using its content. The elements of the CAM bank include comparison logic. The address input to the CAM is simultaneously compared to all stored addresses. The matching result is the corresponding data used to match the address. The CAM operation is a data parallel processor. CAM has performance advantages over other memory search algorithms. This is because at the same time the desired information is compared to the entire list of stored items. Although CAM is preferred, the first memories 202 and 232 can also be standard memory, logic, or any other suitable electronic storage medium.

Referring now to Figure 11, there is shown the memory circuit implementation steps illustrated in Figures 9 and 10 during startup. Control begins in step 270. In step 272, control determines whether the memory unit is powered on. If no, the control loops to step 272. Otherwise, control continues to step 274 where control determines if a test of the second memory is required.

If the determination at step 274 is yes, then control continues to step 275 where the second memory is placed in a stress mode or condition. In step 276, the first memory is de-energized. In step 277, the memory location in the second memory is tested. In step 278, control determines if the memory location is defective. If so, then in step 280 control stores the defective address and/or block into the first memory. Control continues from step 278 (if no) and step 280 to step 284. In step 284, control determines whether all memory locations in the second memory have been checked. If not, then control identifies the next memory location in step 286 and then returns to step 276. Otherwise, control sets the second memory to the normal mode in step 290 and enables the first memory. Control ends in step 292.

Referring now to Figure 12, an exemplary method for testing the location of a memory in a second memory is shown at 300. Control begins in step 302. In step 304, the special pattern/material is written to a memory location. In step 306, the special pattern/data is read from the memory location. In step 310, control determines whether the written data is equal to the read data. If not, control continues to step 312 where the memory location is marked as defective. The address of the defective location (one or more) is stored in the first memory. Control continues from step 310 (if yes) and step 312 to step 314 where control ends.

As can be appreciated, testing of memory for storing data in a memory circuit in accordance with the present invention can be implemented in the following situations: during manufacturing and/or assembly; when the second memory is first activated; The second secondary memory is activated; periodically; or randomly during subsequent startup. Testing can be performed by logic, such as logic 229, and/or by an external testing device. As is familiar to those skilled in the art, other criteria can be used to schedule tests. In addition, all or part of the second memory can be tested.

After identifying the defective location in the second memory and storing the corresponding memory address in the first memory, the memory circuit is 320 in FIG. 13A and 320' in FIG. 13B. Generally stated operation. In Figure 13A, control begins in step 322. In step 324, control determines whether the material is being written to the second memory. If so, then control determines in step 328 whether the write data address is equal to the address in the first memory. If so, the data is written to address location step 330 stored in the first memory. If the address is not in the first memory, then control continues to step 334 where the material is written to the address in the second memory. In another alternative embodiment, the data can also be written to the original address in the second memory (even if it is bad) to simplify the memory circuit. If it is determined in step 340 that the material is to be read from the second memory, then control determines in step 342 whether the read data address is equal to the address in the first memory. If so, control continues to step 344 and the data is read from the address in the first memory. Otherwise, control continues to step 346 and the data is read from the address in the second memory.

Referring now to Figure 13B, an alternative method is shown at 320'. If it is determined in step 328 that the write address is in the first memory, the new address set by the first memory is used in step 330' to write the data to the new non-defective in the second memory. position. If it is determined in step 342 that the read address is in the first memory, the data is read from the new location in the second memory using the new address specified by the first memory in step 344'. In Figures 13A and 13B, the data can be written to the original memory address (even if it is bad) to simplify the circuit.

Referring now to Figure 14A, there is shown a read operation in memory circuit 350 in accordance with the present invention. Memory circuit 350 provides error correction coding (ECC) found in second memory 360 for defective memory locations. Memory circuit 350 includes logic 352 coupled to memory interface 354. The address line of memory interface 354 is coupled to CAM 356 and memory 360. Memory 360 includes memory locations 364-1, 364-2, ..., and 364-n. The CAM includes m memory locations. In the preferred embodiment, n>>m. The CAM 256 is preferably less than 5% of the size of the second memory 360. For example, CAM 356 is approximately 1% of the size of second memory 360.

CAM 356 is coupled to ECC circuit 366. The output of the ECC circuit is coupled to multiplexer 370. When an address is output to the second memory 360 by the memory interface 354, the CAM 356 compares the address with the stored address. If a match is found, the CAM 356 outputs a match signal to the multiplexer 370 and outputs the ECC bit to the ECC circuit 366. The ECC circuit 366 and the multiplexer also receive data from the second memory 360. The ECC circuit 370 uses the ECC bits from the CAM 356 and outputs the data to the multiplexer 370. The multiplexer 370 selects the output of the ECC circuit 370 when a match occurs. The multiplexer 370 selects the output of the second memory 360 when no match occurs.

As can be appreciated, the memory 360 is preferably a CAM. Other types of memory (eg, SDRAM, DRAM, SRAM) and/or any other suitable electronic storage medium can then be used for memory 360 without the use of CAM. The first memory 360 can be fabricated on the first microchip together with at least one of: a logic circuit 352, a memory interface 354, and an ECC circuit 366. The second memory 360 can be fabricated on the second microchip or on the first microchip.

Referring now to Figure 14B, a memory circuit 350 for a write operation is shown. The memory interface 354 outputs the write address to the second memory 360. If the address matches the address stored in CAM 356, CAM 356 stores the ECC bit generated by ECC circuit 366 into the location associated with the matching address.

Referring now to Figure 15, the steps for operating the memory circuit 350 of Figures 14A and 14B are generally shown at 400. Control begins in step 402. In step 404, control determines whether the material is to be written from the logic 352 to the second memory 360. If the determination at step 404 is yes, then control continues to step 405 where control determines if the address is defective. If not, then control continues to step 406 and the data is read from the address in the memory. If YES in step 405, then control continues to step 407 where ECC 366 generates an ECC bit. In step 408, the ECC bits are written to CAM 356. In step 410, the material is written to the second memory 360.

If the result of step 404 is no, control continues to step 412. In step 412, control determines whether data is to be read from the second memory 360. If so, control continues to step 413 where control determines if the address is defective. If no, then control continues to step 414 and the data is read from the memory. Otherwise, control continues to step 416 where the ECC bit is read back from the CAM 356. In step 418, the data is read from the second memory 360. The ECC 356 implements error correction encoding on the data using the ECC bits in step 420. In step 422, the data is output to logic 352. If step 412 is no, then control returns to step 404.

Referring now to Figure 16A, a memory circuit 400 is illustrated. The memory interface 404 is coupled to the first memory 406, and the first memory 406 includes a plurality of memory locations 414-1, 414-2, ..., and 414-n. Memory interface 404 is typically coupled to logic 408. The second memory 416 includes a plurality of memory locations 418-1, 418-2, ..., and 418-m. The second memory 416 is coupled to the address line 422. The second memory 416 is also coupled to the multiplexer 424. The multiplexer 424 is coupled to the read data line 428 from the first memory 406. Control line 430 or a match line connects second memory 416 to multiplexer 424. For the memory circuit in Figure 14, n>>m.

In use, the second memory 416 monitors the address transmitted to the first memory 406 on the address line 422. If the second memory 416 has a matching address, the second memory 416 generates a control signal via the control line 430 and outputs the corresponding material to the multiplexer 424. This data is routed by multiplexer 424 to memory interface 404.

Referring now to Figure 16B, a memory circuit 400' during a write data operation is illustrated. The second memory 416 monitors the address line 422. If the address matches the address stored in the second memory 416, the second memory 416 writes the material to a location in the second memory 416 that corresponds to the matching address. To simplify the memory circuit 400', the data can also optionally be written to the first memory. The first memory 406 can be an ECC memory with ECC bits.

As can be appreciated, the present invention contemplates the use of CAM for memory 202, 232, 358, and 416 to provide optimal memory access time. However, any other suitable electronic storage medium may be used, such as DRAM, SRAM, SDRAM, and the like. The ECC and control circuit 356 can be a combined ECC.

As can be appreciated, the memory of the stored material can be tested for defects at the time of manufacture, at the time of assembly, during operation, at power up, or at any other suitable time.

Referring now to Figure 17, a functional block diagram of a memory module 500 is shown. The memory control module 510 selectively transmits data storage and data capture commands to the memory modules 514-1, 514-2, ..., and 514-Z (collectively referred to as memory modules 514). one. Each memory module 514 includes a plurality of memory volume circuits (ICs) 520-11, 520-12, ..., and 520-ZY (collectively referred to as IC 520) and buffer modules 530-1, 530-2. , ... and 530-Z (collectively referred to as buffer module 530). The memory IC 520 can be configured on a printed circuit board (PCB) that is typically identified at 531. One or more edge connectors may be provided along one or more outer edges of the PCB shown in Figures 22 and 23. The memory module 514 can have a different number of memory ICs 520. The block generator module 534 can generate block signals for the memory control module 510 and the memory module 514. The buffer module 530 can be implemented as an integrated circuit (IC).

Communication between the memory control module 510 and the memory module 514 can be implemented using serial and/or parallel signals. The bus 531 can be used to support data flow between the memory control module 510 and the memory module 514. The bus 533 can be used to support data flow between the memory module 514 and the memory control module 510. Different signal transmissions can also be used.

The system can include a variable number of channels or memory modules 514. Each memory module 514 can also include a variable number of memory ICs 520. The memory IC 520 may include a dynamic random access memory (DRAM) IC, although other types of memory may be used. The memory IC 520 and buffer module 530 for each memory module 514 can be mounted to one or both sides of a printed circuit board (PCB) having interconnect traces and/or vias. Edge connectors and/or other connection techniques can also be used. Other packaging techniques can also be used.

The buffer module 530 can buffer signals between the memory control module 510 and the memory module 514, and/or signals on the bus bars 531 and 533. The buffer module 530 can buffer incoming control signals and address signals, such as column access and pre-charge (RAS), row address strobe (CAS), and the like. A zone control/address line (not shown) is provided on the memory module 514 to locally distribute the buffered control and address signals to the respective memory ICs 520 on the memory buffer 514. The buffer module 530 can include a phase locked loop (PLL) to generate a locally phase adjusted clock signal.

Referring now to Figure 18, a functional block diagram of a typical memory module 600 is shown. The memory control module 610 selectively transmits the data storage and data capture instructions to the plurality of memory modules 614-1, 614-2, ..., and 614-Z (collectively referred to as the memory module 614). One. Each memory module 614 includes a plurality of memory volume circuits (ICs) 620-11, 620-12, ..., and 620-ZY (collectively referred to as ICs 620) and buffer and error correction modules 630-1, 630. -2, ... and 630-Z (collectively referred to as buffer and error correction module module 630). The clock generator module 634 can generate clock signals for the memory control module 610 and the memory module 614. The buffer and error correction module 630 can be an integrated circuit.

The buffer and error correction module 630 includes: random access memory (RAM) 640-1, 640-2, ..., and 640-Z (collectively referred to as RAM 640), content addressable memory (CAM) 642- 1, 642-2, ... and 642-Z (collectively referred to as CAM 642), and non-volatile (NV) memories 644-1, 644-2, ..., and 644-Z (collectively referred to as NV) Memory 644). RAM 640, NV memory 644, and/or additional RAM and/or NV memory may be provided to support the buffer functions described above. CAM 642 can be used to perform random patching, such as patching of the random data portions described above and below. The RAM 640 can be used to temporarily store data blocks or pages during the paging test. Therefore, the storage of data and the retrieval of data are not interrupted during the memory test. The NV memory 644 can be used to store the address of the defective location and/or other information, as explained below.

After testing the paging, ECC and/or CAM can be used to detect and correct errors. Random patching can be implemented in memory 806 using CAM 642, as using CAM to temporarily store the entire page may be too expensive. In other words, the patch implemented using CAM 642 may be less than one page. During the paging test, RAM 640 is used to temporarily store one or more pages. NV memory 644 may include flash memory or other suitable NV semiconductor memory, and NV memory 644 stores a lookup table (LUT) that associates the tested paged address with the paged temporary address in RAM 640.

Memory IC 620 and/or RAM 640 can include any type of memory. For example, the memory IC 620 and/or the RAM 640 may include static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, non-volatile memory, phase change memory, and more. Bit memory, and/or any other suitable type of memory.

Referring now to Figure 19, there is shown a flow diagram illustrating the steps performed by the memory module 614 of Figure 18. Control begins in step 700. In step 704, the tested pages are mapped to RAM 640 and NV memory 644. In other words, the paged address of the tested page is stored in the NV memory 644, and the data in the page is stored in the RAM 640. In step 708, the update to the page is terminated and the test is performed on the page. Any suitable test can be performed.

For example, test values can be written to some or all of the cells in the pagination. Then, after a predetermined period, the values in these units can be read back. The predetermined period may be longer than the normal update period. If the memory unit fails to hold the charge for a sufficient period of time, the unit can be considered faulty. Other types of testing can also be implemented.

After the test is completed, if the memory unit passes the test, the data can be returned to these memory cells, and the paged address can be deleted from the NV memory 644. In step 720, control determines whether a random bit failure is detected. If so, the address of the memory unit and/or the data associated with the failed memory unit can be stored in CAM 462 in step 722. Subsequent memory storage and retrieval requests for these failed memory cells are redirected to CAM 642. In step 726, control determines if other pages are to be tested. If yes, then control returns to step 704. Otherwise, control ends in step 730.

In some embodiments, the memory module 600 can be a dual in-line memory module (DIMM), a fully buffered DIMM (FB DIMM), a single in-line memory module (SIMM), and/or any other type. Memory module.

Referring now to Figure 20, there is shown the operation of a typical memory system such as memory module 614 during a read operation. The memory module 614 includes: a CAM 814 for storing random data errors; and a random access memory (RAM) and non-volatile (NV) memory for storing paging during paging in the memory 806 of the test memory module 614. 808.

The memory control module 802, the control module 807, and/or any other device can identify one or more tested pages in the memory 806. The memory 806 can include a memory IC 620 for the memory module 614. The memory control module 802 and/or the control module 807 can include a test module 803 that tests the memory after manufacture, during power up, randomly, when an event occurs, and/or when other criteria are used. Any other suitable test method can also be used to identify the fault memory.

Control module 807 can store one or more tested paged addresses into NV memory 808. In some embodiments, the test module 803 sends the address data of the tested page to the control module 807. The test module 803 can remove the address data for paging when the test is completed. The control module 807 stores the address for the tested page into the NV memory 808. NV memory 808 can include flash memory and/or any other suitable NV semiconductor memory. Alternatively, test module 803 and/or any other test circuit may have separate connections to control module 807. The test module 803 can be integrated with the memory module 614. The control module 807 and/or the memory control module 802 can trigger the memory 806 to store the data in the tested paging in the memory 810. At the end of the test, control module 807 and/or memory control module 802 can move the data back to memory 806. The function of control module 807 can also be implemented by memory control module 610, other control modules, and/or memory controllers.

Control module 807 monitors the read address lines to match the addresses stored in NV memory 808. Memory 810 can be used to store paging data that should normally be sent to the test page. To this end, memory 810 selectively stores tested pages 810-1, 810-2, ..., and 810-P during testing, while P is an integer greater than zero. The NV memory 808 can store a lookup table that will be the logical and/or physical address of the tested page in the memory IC 620, and the assigned physical address of the page in the memory 810 used during the paging test. Associated.

When the control module 807 determines that an address match occurs, the NV memory 808 outputs the paged physical address in the selected memory 810 to the memory 810. The memory 810 outputs the stored paging material. In addition, the control module 807, the NV memory 808, and/or the CAM 814 can be integrated into the integrated circuit with the buffer and error correction module 630.

The test module 803 can also identify the address of the random data that has failed and/or cannot be otherwise manipulated during the test. The addresses of these locations can be stored in CAM 814. The CAM 814 monitors the matching of the read address lines. If a match occurs, CAM 814 outputs: match signal 832 and the read data stored corresponding to the matched address.

Control module 807 and CAM selectively output matching signals to multiplexer 816. Depending on the match signal, multiplexer 816 can select one of the outputs of memory 810, CAM 814, and memory 806. In other words, when the logical address on the address line matches the address in CAM 814 or the address in NV memory 808, CAM 814 or NV memory 808 outputs a corresponding match signal to multiplexer 816. The multiplexer 816 can be defaulted to select the output of the memory 806. If the match signal 832 from the CAM 814 shows a match, the multiplexer 816 selects the output 834 of the CAM 814. If the match signal 820 output by the control module 807 shows a match, the multiplexer 816 selects the output 822 of the memory 810. Otherwise, if the address matches the address associated with memory 806, multiplexer 816 outputs the data from memory 806. Additional memory module 614 can be coupled to the address lines and data lines as shown in Figures 18 and 20.

Referring now to Figure 21, there is shown the operation of the exemplary memory module 614 during a write operation. Control module 807 monitors the write address line to monitor the match with the address stored in NV memory 808. When the control module 807 determines that an address match occurs, the control module 807 issues a match signal 840 to the multiplexer 844. The NV memory 808 outputs the paged physical address in the selected memory 810 to the memory 810. Memory 810 writes the stored information to the identified address.

CAM 814 also compares the write address to the stored address and selectively transmits a match signal 846 when a match occurs. If a match occurs, CAM 814 writes the data on the write data bus to the location in CAM 814 that corresponds to the matching address.

Control module 807 and CAM 814 selectively output matching signals to multiplexer 844. The multiplexer 844 outputs the write data to one of the memory 810, the CAM 814, and the memory 806 in accordance with the match signal. Otherwise, if the address matches the address associated with the memory 806, the multiplexer 816 outputs the write data from the write address bus to the memory 806. The additional memory module 614 can be connected to the write address bus and the write data bus as shown in Figures 18 and 21.

Referring now to Figures 22 and 23, there are shown several exemplary embodiments of a memory module. In FIG. 22, the edge connector 900 of the memory module 902 is inserted into the slot 904 of the host device 906. Elements of the memory module 902 can be disposed on a printed circuit board (PCB) 908 having an edge connector 900. Host device 906 can be any suitable device, such as a laptop, personal digital assistant, mobile phone, MP3 player, computer, and the like. In FIG. 22, the edge connector 910 located along the edge of the PCB 918 of the memory module 912 is inserted into the slot 914 of the computer 916.

Referring now to Figure 24, an alternate memory module 950 includes memory volume circuits (IC) 952-1, 952-2, ..., and 952-M (collectively referred to as memory IC 952). The memory module 950 can include a printed circuit board (PCB) and/or other packages. Memory ICs 952-1, 952-2, ..., and 952-M include memory 953-1, 953-2, ..., and 953-M (collectively referred to as memory 953). Buffer and Error Correction (BEC) modules 954-1, 954-2, ..., and 954-M (collectively referred to as BEC modules 954). The BEC circuits 954-1, 954-2, ..., and 954-M include: RAMs 956-1, 956-2, ..., and 956-M (collectively referred to as RAM 956), CAM 960-1, respectively. , 960-2, ..., and 960-M (collectively referred to as CAM 960), and non-volatile (NV) memories 962-1, 962-2, ..., and 962-M (collectively referred to as NV memory 962).

Instead of the centralized buffering and error correction functions as described above in Figures 17-23, the memory module 950 has localized buffering and error correction functions. Otherwise, the operation of the CAM, RAM, and NV memory is similar to the above operation. In some embodiments, one or more memory modules 805 can be controlled by the memory controller 610 and controlled by the clock generator module 634 clock as shown in FIG. The buffer 530 of FIG. 17 may also be provided in each memory module 950 to buffer control and/or data from the memory controller 610. In addition, the test module 803 in FIG. 20 may be located in the remote memory control module 610, locally located in each memory IC 952, locally located in each BEC module 954, and/or in each memory module 950. .

Advantages associated with the above embodiments include improved memory performance, especially when testing pagination. In addition, the errors found can be corrected during the test.

Referring now to Figure 25, an alternate memory module 970 includes memory volume circuits (IC) 972-1, 972-2, ..., and 972-M (collectively referred to as memory IC 972). The memory module 970 can include a printed circuit board (PCB) and/or other packages. In addition to the memories 973-1, 973-2, ..., and 973-M (collectively referred to as the memory 973), the memory ICs 972-1, 972-2, ..., and 972-M include Buffer and Error Correction (BEC) modules 974-1, 974-2, ..., and 974-M (collectively referred to as BEC modules 974). The BEC circuits 974-1, 974-2, ..., and 974-M include: RAMs 976-1, 976-2, ..., and 976-M (collectively referred to as RAM 976); and CAM 980-, respectively. 1, 980-2, ..., and 980-M (collectively referred to as CAM 980).

Non-volatile (NV) memory 990 is in communication with memory IC 972 and may be shared by memory IC 972. Alternatively, each memory IC 972 can include an external NV memory IC 990, and/or other shared configurations can be used. For example, H memory ICs may be associated with each NV memory IC 990, where H is an integer greater than one and less than or equal to M. Alternatively, each memory module 970 can include more than one NV memory IC 990.

In some embodiments, one or more of the memory modules 970 can be controlled by the memory controller 610 and controlled by the clock generator module 634 clock as shown in FIG. The buffer 530 of FIG. 17 may also be provided in each memory module 970 to buffer control and/or data from the memory controller 610. In addition, the test module 803 in FIG. 20 may be located in the remote memory control module 610, locally located in each memory IC 972, locally located in each BEC module 974, and/or each memory module. 970.

Referring now to Figures 26A and 26B, other exemplary configurations can also be used. In FIG. 26A, one or more of the memory ICs 952 of FIG. 24 are disposed on the main board 992 or are connected to the memory interface or other portion of the host device 993. When the motherboard 992 is used, the processor 994 and the memory controller 996 can also be configured on the motherboard 992. The memory controller 996 can communicate with the memory IC. In FIG. 26B, one or more memory ICs 972 according to FIG. 25 may be disposed on the main board 992 of the host device 993. Processor 994 and memory controller 996 may also be configured on motherboard 992.

Referring now to Figures 27A and 27B, which show a system with an adjusted update rate. In FIG. 27A, the device 1000 includes a memory controller 1004 and a memory module 1008. The memory controller 1004 can include an adjustment update rate module 1012 and a test module 1016. The test module 1016 and/or the adjusted update rate module 1012 can be associated with the memory controller 1004, as shown, can be associated with the memory module 1008 shown in FIG. 27B, and/or as a stand-alone Device. The memory module 1008 includes a memory 1020 and a BEC module 1024. The BEC module 1024 includes a RAM 1028, a CAM 1032, and an NV memory 1036. As shown above, the NV memory can be integrated with the BEC module 1024 or external to the BEC module 1024. One or more of memory 1020, RAM 1024, CAM 1032, NV memory 1036, adjustment update module 1012, and/or test module 1016 may be integrated as a system on a wafer.

Referring now to Figure 28, the exemplary steps performed by the adjustment update rate module begin at step 1050. In step 1054, a test is performed to determine if the memory unit can operate at the current update rate. If the memory unit cannot maintain the correct state during the current update time period, it fails during the test. In step 1058, control determines if some of the memory cells have failed during the current update rate test. If NO at step 1058, then control returns to step 1054. If YES at step 1058, the adjusted update rate module 1012 reduces the time period between updates to all of the memory cells in the memory module in step 1062. In other words, the adjustment update rate module 1012 updates the memory unit more quickly to prevent the memory unit from malfunctioning. Thus, there is a tendency to increase the power consumption of the memory module and/or its associated host device. This also tends to reduce the usability of the memory unit, which tends to reduce performance.

Referring now to Figure 29, the steps performed by the adjustment update rate module begin at step 1100. In step 1104, the memory unit is tested at the current update rate. In step 1108, control determines if some memory cells have failed during the test. If no at step 1108, then control returns to step 1104. If YES at step 1108, then control determines in step 1112 whether the number of failed memory cells is less than or equal to the available number of CAM memory cells. If YES at step 1112, then control replaces the failed memory unit with the CAM unit in step 1118 and maintains the current update rate. If step 1112 is no and there are not enough CAM cells available, then control reduces the time between updating all of the memory cells in step 1120.

Referring now to Figure 30, there is shown an alternate step implemented by the Adjust Update Rate module. Control begins in step 1150. In step 1154, control determines a minimum time period between updates that will not result in a failed memory unit. In step 1158, control determines the number of available CAM memory cells. In step 1162, control optimizes the relationship between the number of CAM memory cells for the failed memory cell and the update rate. This step also balances the number of failed memory cells that fail due to reasons other than the above update rate. In step 1168, control uses the CAM memory unit instead of identifying the failed memory unit with the update rate issue in step 1154.

Referring now to Figure 31, control begins in step 1200. In step 1208, control sets the update rate to an initial value. In step 1212, control is implemented to determine if the memory unit failed the test during the initial time between updates. If YES at step 1212, then control determines (due to the current update rate) whether the number of failed memory cells is less than the first threshold CAM _TH1 . The first threshold CAM _TH1 may be an integer greater than one and less than the number of CAM memory cells. If no at step 1214, then control determines whether the number of failed memory cells having the update rate problem is less than or equal to the second threshold CAM _TH2 . The second threshold may be an integer greater than the first threshold CAM _TH1 and less than the number of CAM memory cells.

If no at step 1218, then control increases the update rate in step 1220 and then returns to step 1212. If no, step 1212, then control reduces the update rate in step 1224, and control returns to step 1212. If YES at step 1214, then control replaces the failed memory unit with the update rate issue using the CAM memory unit in step 1228, increasing the time period between updates by a predetermined amount, and then control returns to step 1212. If YES at step 1218, then control replaces the failed memory unit with the update rate issue using the CAM memory unit in step 1234 and maintains the current update rate. Control then continues from step 1234 to step 1212.

The above method identifies the optimal time period between updates using the CAM memory unit. Therefore, the power consumed during the life of the device is optimized. This improvement is important for battery powered devices.

Reference is now made to the Figures 32A-32G, which show various exemplary embodiments including the teachings of the present invention.

Referring now to Figure 32A, the teachings of the present invention can be performed in the memory of a hard disk drive (HDD) 1300. The HDD 1300 includes a hard disk component (HDA) 1301 and an HDD PCB 1302. The HDA 1301 may include magnetic media 1303 (eg, one or more discs that store material), and a read/write device 1304. The read/write device 1304 can be configured on the actuator arm 1305 and can read and write material on the magnetic media 1303. Further, the HDA 1301 includes a spindle motor 1306 that rotates the magnetic medium 1303, and a voice coil motor (VCM) 1307 that drives the actuator arm 1305. The preamplifier 1308 amplifies the signal generated by the read/write device 1304 during a read operation and provides the signal to the read/write device 1304 during a write operation.

The HDD PCB 1302 includes a read/write channel module (hereinafter referred to as "read channel") 1309, a hard disk controller (HDC) module 1310, a buffer 1311, a non-volatile memory 1312, a processor 1313, and a spindle/ VCM driver module 1314. Read channel 1309 processes the data received or transmitted to preamplifier device 1308. The HDC module 1310 controls the elements of the HDA 1301 and communicates with an external device (not shown) via an input/output (I/O) interface 1315. The external device may include: a computer, a multimedia device, a mobile computing device, and the like. The I/O interface 1315 can include: a wired and/or wireless communication link.

The HDC module 1310 can receive data from the HDA 1301, the read channel 1309, the buffer 1311, the non-volatile memory 1312, the processor 1313, the spindle/VCM driver module 1314, and/or the I/O interface 1315. The processor 1313 can process the data including: encoding, decoding, filtering, and/or formatting. The processed data can be output to: HDA 1301, read channel 1309, buffer 1311, non-volatile memory 1312, processor 1313, spindle/VCM driver module 1314, and/or I/O interface 1315.

The HDC module 1310 can use the buffer 1311 and/or the non-volatile memory 1312 to store data related to the HDD 1300 control and operation. The buffer 1311 may include a DRAM, an SDRAM, or the like. The non-volatile memory 1312 may include: flash memory memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, or multi-state memory, wherein each memory cell has more Two states. Spindle/VCM driver module 1314 controls spindle motor 1306 and VCM 1307. The HDD PCB 1302 includes this power supply 1316 that provides power to the components of the HDD 1300.

Referring now to Figure 32B, the teachings of the present invention can be performed in the memory of a DVD drive 1318 or a CD drive (not shown). The DVD drive 1318 includes a DVD PCB 1319 and a DVD assembly (DVDA) 1320. The DVD PCB 1319 includes a DVD control module 1321, a buffer 1322, a non-volatile memory 1323, a processor 1324, a spindle/FM (feed motor) driver module 1325, an analog front end module 1326, and a write strategy module 1327. And the DSP module 1328.

The DVD control module 1321 controls the elements of the DVDA 1320 and communicates with an external device (not shown) via the I/O interface 1329. The external device may include: a computer, a multimedia device, a mobile computing device, and the like. The I/O interface 1329 can include: wired and/or wireless communication links.

The DVD control module 1321 can receive from the buffer 1322, the non-volatile memory 1323, the processor 1324, the spindle/FM driver module 1325, the analog front end module 1326, the write strategy module 1327, the DSP module 1328, and / or I / O interface 1329 information. The processor 1324 can process the data including: encoding, decoding, filtering, and/or formatting. The DSP module 1328 performs signal processing, such as video and/or audio encoding/decoding. The processed data can be output to buffer 1322, non-volatile memory 1323, processor 1324, spindle/FM driver module 1325, analog front end module 1326, write strategy module 1327, DSP module 1328, and/or I/O interface 1329.

The DVD control module 1321 can use the buffer 1322 and/or the non-volatile memory 1323 to store data related to the control and operation of the DVD drive 1318. The buffer 1322 may include a DRAM, an SDRAM, or the like. The non-volatile memory 1323 may include flash memory memory (including NAND and NOR flash memory), phase change memory, magnetic RAM or multi-state memory, wherein each memory cell has more than two status. The DVD PCB 1319 includes a power supply 1330 that supplies power to components of the DVD drive 1318.

The DVDA 1320 may include a preamplifier device 1331, a laser driver 1332, and an optical device 1333, which may be an optical read/write (ORW) device or an optical read only (OR) device. Spindle motor 1334 rotates optical storage medium 1335 and feed motor 1336 drives optical device 1333 relative to optical storage medium 1335.

When reading material from the optical storage medium 1335, the laser driver provides read power to the optical device 1333. Optical device 1333 detects material from optical storage medium 1335 and transmits the data to preamplifier device 1331. The analog front end module 1326 receives the material from the preamplifier device 1331 and performs functions such as filtering and A/D conversion. In order to write to optical storage medium 1335, write strategy module 1327 communicates power level and timing information to laser driver 1332. The laser driver 1332 controls the optical device 1333 and writes the material to the optical storage medium 1335.

Referring now to Figure 32C, the teachings of the present invention can be performed in the memory of a High Definition Television (HDTV) 1337. The HDTV 1337 includes an HDTV control module 1338, a display 1339, a power supply 1340, a memory 1341, a storage device 1342, a WLAN interface 1343 and associated antenna 1344, and an external interface 1345.

The HDTV 1337 can receive input signals from the WLAN interface 1343 and/or the external interface 1345 that transmit and receive information via cables, broadband internet, and/or satellites. The HDTV control module 1338 can process input signals including: encoding, decoding, filtering, and/or formatting, and generating output signals. The output signal can be transmitted to one or more of display 1339, memory 1341, storage device 1342, WLAN interface 1343, and external interface 1345.

The memory 1341 may include random access memory (RAM) and/or non-volatile memory, and the non-volatile memory is, for example, a flash memory, a phase change memory, or a multi-state memory, each of which The memory unit has more than two states. The storage device 1342 can include an optical storage drive, such as a DVD drive and/or a hard disk drive (HDD). The HDTV control module 1338 communicates with the outside via the WLAN interface 1343 and/or the external interface 1345. Power supply 1340 provides power to the components of HDTV 1337.

Referring now to Figure 32D, the teachings of the present invention can be performed in the memory of vehicle 1346. The vehicle 1346 can include a vehicle control system 1347, a power source 1348, a memory 1349, a storage device 1350, a WLAN interface 1352, and an associated antenna 1353. The vehicle control system 1347 may be a powertrain control system, a main body control system, an entertainment control system, an anti-lock brake system (ABS), a navigation system, an in-vehicle mobile communication device system, a lane departure system, an adjustment cruise control system, and the like.

Vehicle control system 1347 can communicate with one or more sensors 1354 and generate one or more output signals 1356. The sensor 1354 may include a temperature sensor, an acceleration sensor, a pressure sensor, a rotation sensor, a gas flu detector, and the like. Output signal 1356 can control: engine operating parameters, transmitting operating parameters, terminating parameters, and the like.

Power source 1348 provides power to the components of vehicle 1346. The vehicle control system 1347 can store the data in the memory 1349 and/or the storage device 1350. The memory 1349 may include random access memory (RAM) and/or non-volatile memory, such as: flash memory memory, phase change memory, or multi-state memory, each of which The memory unit has more than two states. The storage device 1350 can include an optical storage drive, such as a DVD drive; and/or a hard disk drive (HDD). Vehicle control system 1347 can communicate with the outside using WLAN interface 1352.

Referring now to Figure 32E, the teachings of the present invention can be implemented in memory in a mobile telephone 1358. The mobile phone 1358 includes a phone control module 1360, a power source 1362, a memory 1364, a storage device 1366, and a mobile network interface 1367. The mobile phone 1358 can include a WLAN interface 1368 and associated antenna 1369, a microphone 1370, an audio output 1372 (eg, a speaker and/or output jack), a display 1374, and a user input device 1376 (eg, a keyboard and/or a click) Device).

The telephony control module 1360 can receive input signals from the mobile network interface 1367, the WLAN interface 1368, the microphone 1370, and/or the user input device 1376. The telephony control module 1360 can process signals (including encoding, decoding, filtering, and/or formatting) and generate output signals. The output signal can be transmitted to one or more of memory 1364, storage device 1366, mobile network interface 1367, WLAN interface 1368, and audio output 1372.

The memory 1364 may include: random access memory (RAM) and/or non-volatile memory, for example, a flash memory memory, a phase change memory, or a multi-state memory, wherein Each memory cell has more than two states. The storage device 1366 can include an optical storage drive (eg, a DVD drive) and/or a hard disk drive (HDD). Power supply 1362 provides power to the components of mobile telephone 1358.

Referring now to Figure 32F, the teachings of the present invention can be implemented in the memory of the set-top box 1378. The set-top box 1378 includes a set-top box control module 1380, a display 1381, a power source 1382, a memory 1383, a storage device 1384, and a WLAN interface 1385 and an associated antenna 1386.

The set-top box control module 1380 can receive input signals from the WLAN interface 1385 and the external interface 1387, both of which can transmit and receive information via cable, broadband Internet, and/or satellite. The set-top box control module 1380 can process signals (including encoding, decoding, filtering, and/or formatting) and generate output signals. The output signals may include: audio and/or video signals in standard and/or high definition formats. The output signal can be transmitted to WLAN interface 1385 and/or display 1381. Display 1381 can include a television, a projector, and/or a monitor.

Power supply 1382 provides power to the components of set-top box 1378. The memory 1383 may include random access memory (RAM) and/or non-volatile memory, such as a flash memory memory, a phase change memory, or a multi-state memory, wherein each memory A unit has more than two states. The storage device 1384 can include an optical storage drive (eg, a DVD drive) and/or a hard disk drive (HDD).

Referring now to Figure 32G, the teachings of the present invention can be performed in the memory of mobile device 1389. The mobile device 1389 can include a mobile device control module 1390, a power supply 1391, a memory 1392, a storage device 1393, a WLAN interface 1394 and associated antenna 1395, and an external interface 1399.

The mobile device control module 1390 can receive input signals from the WLAN interface 1394 and the external interface 1399. The external interface 1399 can include: USB, infrared, and/or Ethernet. The input signal can include: compressed audio and/or video signals and can follow the MP3 format. In addition, the mobile device control module 1390 can receive input from a user input 1396 such as a keyboard, touch pad, or individual button. The mobile device control module 1390 can process input signals (including encoding, decoding, filtering, and/or formatting) and generate output signals.

The mobile device control module 1390 can output an audio signal to the audio output 1397 and output the video signal to the display 1398. The audio output 1397 can include a speaker and/or an output jack. Display 1398 can present a graphical user interface, which can include: menus, images, and the like. Power supply 1391 provides power to the components of mobile device 1389. The memory 1392 may include: random access memory (RAM) and/or non-volatile memory, for example, a flash memory memory, a phase change memory, or a multi-state memory, wherein Each memory cell has more than two states. The storage device 1393 may include an optical storage drive (eg, a DVD drive) and/or a hard disk drive (HDD). The mobile device can be a media player, a personal digital assistant, a game console, and/or other types of mobile devices.

It will now be apparent to those skilled in the art from this disclosure that the broad teachings of the invention can be implemented in various forms. Therefore, although the invention has been described in terms of specific examples, the true scope of the invention should not be limited. This is due to the fact that other modifications will be apparent to those skilled in the art after studying the specification, the drawings, and the scope of the following claims.

10. . . System on Chip (SoC)

12. . . logic

14. . . Embedded memory

16. . . Random single bit failure

18, 20. . . Bit line defect

twenty four. . . Random data section

26. . . Cache data section

28. . . Error correction coding (ECC) circuit

30. . . ECC coded bit

32. . . ECC circuit can go

50. . . System on Chip (SoC)

52. . . Logic (circuit)

54. . . Embedded memory

56. . . Switching circuit

58. . . Error correction coding (ECC) circuit

60. . . Random data section

62. . . Cache data section

64-1, -2, -n. . . Block

68. . . Memory test circuit

69. . . Memory circuit

70. . . Content addressable memory (CAM)

72. . . Multiplexer

74. . . Matching line

80. . . Memory

100. . . method

102, 104, 106, 108, 110, 112, 114, 116, 118. . . step

150. . . Embedded memory circuit

154. . . Memory interface

156. . . Address and control input

158. . . Address and control input

160, 180. . . Data entry

162, 182. . . Data output

166. . . Memory

170. . . External memory circuit

174. . . Memory interface

176, 178. . . Address and control input

186. . . Memory

190. . . dotted line

200. . . Embedded memory circuit

202. . . First memory

204. . . Memory interface

206. . . Second memory

208, 210. . . Address and control input

212, 224. . . Data entry

214, 228. . . Data output

220, 222. . . Address and control input

229. . . logic

230. . . External memory circuit

232. . . First memory

234. . . Memory interface

236. . . Second memory

237. . . dotted line

238, 240. . . Address and control input

242, 254. . . Data entry

244, 258. . . Data output

250, 252. . . Address and control input

259. . . logic

270. . . step

272, 274, 275, 276, 277, 278, 280, 284, 286, 290, 292. . . step

300. . . method

302, 304, 306, 310, 312, 314. . . step

320. . . method

320’. . . method

322, 324, 328, 330, 334, 340, 342, 344, 346, 330', 344'. . . step

350. . . Memory circuit

352. . . logic

354. . . Memory interface

356. . . Content addressable memory (CAM)

360. . . Memory

364-1, -2, -n. . . Memory location

366. . . ECC circuit

370. . . Multiplexer

400. . . method

402, 404, 405, 406, 407, 408, 410, 412, 413, 414, 416, 418, 420, 422. . . step

400. . . Memory circuit

400’. . . Memory circuit

404. . . Memory interface

406. . . First memory

408. . . logic

414-1, -2, -n. . . Memory location

416. . . Second memory

418-1, -2, -m. . . Memory location

422. . . Address line

424. . . Multiplexer

428. . . Reading data line

430. . . Control line

500. . . Memory module

510. . . Memory control module

514-1, -2, -Z. . . Memory module

520-1, -2, -Z. . . Memory volume circuit

530-1, -2, -Z. . . Buffer module

531. . . Printed circuit board (PCB) / bus

533. . . Busbar

534. . . Block generator module

600. . . Memory module

610. . . Memory control module

614-1, -2, -Z. . . Memory module

620-11~-1Y. . . Memory volume circuit

620-21~-2Y. . . Memory volume circuit

620-Z1~-ZY. . . Memory volume circuit

630-1, -2, -Z. . . Buffer and Error Correction (BEC) Module

640-1, -2, -Z. . . Random access memory (RAM)

634. . . Clock generator module

642-1, -2, -Z. . . Content addressable memory (CAM)

644-1, -2, -Z. . . Non-volatile (NV) memory

700~730. . . step

800. . . Memory system

802. . . Memory control module

803. . . Test module

806. . . Memory

807. . . Control module

808. . . Non-volatile (NV) memory

810-1, -2, -P. . . Tested paging

814. . . Content addressable memory (CAM)

816. . . Multiplexer

818. . . Address line

820. . . Matching signal

822. . . Output

830. . . Address line

832. . . Matching signal

834. . . Output

840. . . Matching signal

844. . . Multiplexer

846. . . Matching signal

900. . . Edge connector

902. . . Memory module

904. . . Slot

906. . . Host device

908. . . Printed circuit board (PCB)

910. . . Edge connector

912. . . Memory module

914. . . Slot

916. . . computer

918. . . Printed circuit board (PCB)

950. . . Replacement memory module

952-1, -2, -M. . . Memory volume circuit

953-1, -2, -M. . . Memory

954-1, -2, -M. . . Buffer and Error Correction (BEC) Module

956-1, -2, -M. . . Random access memory (RAM)

960-1, -2, -M. . . Content addressable memory (CAM)

962-1, -2, -M. . . Non-volatile (NV) memory

970. . . Replacement memory module

972-1, -2, -M. . . Memory volume circuit

973-1, -2, -M. . . Memory

974-1, -2, -M. . . Buffer and Error Correction (BEC) Module

976-1, -2, -M. . . Random access memory (RAM)

980-1, -2, -M. . . Content addressable memory (CAM)

990. . . Non-volatile (NV) memory

992. . . Motherboard

993. . . Host device

994. . . processor

996. . . Memory controller

1000. . . Device

1004. . . Memory controller

1008. . . Memory module

1012. . . Adjust update rate module

1016. . . Test module

1020. . . Memory

1024. . . Buffer and Error Correction (BEC) Module

1028. . . Random access memory (RAM)

1032. . . Content addressable memory (CAM)

1036. . . Non-volatile (NV) memory

1050, 1054, 1058, 1062. . . step

1100, 1104, 1108, 1112, 1118. . . step

1150, 1154, 1158, 1162, 1168, 1170. . . step

1200, 1208, 1212, 1214, 1218, 1220, 1224, 1228, 1234. . . step

1300. . . Hard disk drive (HDD)

1301. . . Hard disk assembly (HDA)

1302. . . Hard disk drive PCB

1303. . . Magnetic media

1304. . . Read/write device

1305. . . Actuator arm

1306. . . Spindle motor

1307. . . Voice coil motor (VCM)

1308. . . Preamplifier

1309. . . Read/write channel module

1310. . . Hard Disk Controller (HDC) Module

1311. . . buffer

1312. . . Non-volatile memory

1313. . . processor

1314. . . Spindle/VCM driver module

1315. . . Input/output interface

1316. . . power supply

1318. . . DVD drive

1319. . . DVD PCB

1320. . . DVD assembly

1321. . . DVD control module

1322. . . buffer

1323. . . Non-volatile memory

1324. . . processor

1325. . . Spindle/feed motor (FM) driver

1326. . . Analog front end module

1327. . . Write strategy module

1328. . . DSP module

1329. . . Input/output interface

1330. . . power supply

1331. . . Preamplifier device

1332. . . Laser driver

1333. . . Optical device

1334. . . Spindle motor

1335. . . Optical storage medium

1336. . . Feed motor

1337. . . High definition television (HDTV)

1338. . . HDTV control module

1339. . . monitor

1340. . . power supply

1341. . . Memory

1342. . . Storage device

1343. . . WLAN interface

1344. . . Related antenna

1346. . . vehicle

1347. . . Vehicle control system

1348. . . power supply

1349. . . Memory

1350. . . Storage device

1352. . . WLAN interface

1353. . . Related antenna

1354. . . Sensor

1356. . . output signal

1358. . . mobile phone

1360. . . Telephone control module

1362. . . power supply

1364. . . Memory

1366. . . Storage device

1367. . . Mobile network interface

1368. . . WLAN interface

1369. . . Related antenna

1370. . . microphone

1372. . . Audio output

1374. . . monitor

1376. . . User input device

1378. . . Set-top box

1380. . . Set-top box control module

1381. . . monitor

1382. . . power supply

1383. . . Memory

1384. . . Storage device

1385. . . WLAN interface

1386. . . Related antenna

1387. . . External interface

1389. . . Mobile device

1390. . . Mobile device control module

1391. . . power supply

1392. . . Memory

1393. . . Storage device

1394. . . WLAN interface

1395. . . Related antenna

1396. . . User input

1397. . . Audio output

1398. . . monitor

1399. . . External interface

1 is a functional block diagram of a system on a wafer (SOC) according to the prior art, the system on the wafer includes logic and embedded memory fabricated on the microchip; and FIG. 2 illustrates the embedded memory of FIG. 3 is a functional block diagram of an SOC including an error correction coding circuit (ECC) according to the prior art; FIGS. 4A and 4B are functional block diagrams illustrating a first SOC according to the present invention; To illustrate a functional block diagram of a memory circuit in accordance with the present invention; FIG. 6 is a flow chart illustrating a method for operating a memory of the SOC of FIGS. 4A and 4B in accordance with the present invention; FIG. 7 is a conventional Functional block diagram of the embedded memory circuit of the technology; FIG. 8 is a functional block diagram of the external memory circuit according to the prior art; FIG. 9 is a functional block diagram of the embedded memory circuit according to the present invention; Figure 1 is a functional block diagram of an external memory circuit in accordance with the present invention; Figure 11 is a flow chart illustrating the steps performed to identify a defective memory address in accordance with the present invention; and Figure 12 is a flow chart illustrating Identifying defective memories Steps of an exemplary method of address; FIGS. 13A and 13B are flowcharts illustrating steps for operating a memory circuit in accordance with the present invention; FIGS. 14A and 14B are diagrams showing a CAM, an ECC circuit, and a second according to the present invention. Functional block diagram of the memory circuit of the memory; Fig. 15 is a flow chart for explaining the operation of the memory circuit of Fig. 14; and Figs. 16A and 16B are memories of the first memory and the second memory according to the present invention. Functional block diagram of the body circuit; FIG. 17 is a functional block diagram of the memory module; FIG. 18 is a functional block diagram of the memory module according to the present invention; and FIG. 19 is a diagram illustrating the memory module of FIG. A flowchart of the steps performed by the group; FIG. 20 is a functional block diagram illustrating the operation of the exemplary memory module during the read operation; and FIG. 21 is a functional block diagram illustrating the operation of the exemplary memory module during the write operation; 22 is a functional block diagram of a memory module having an edge connector inserted in a slot of a host device; and FIG. 23 is a functional block diagram of a memory module having an edge connector inserted in a computer slot. Figure 24 Functional block diagram of an alternative memory module with a buffer and error correction module; Figure 25 is a functional block diagram of an alternative memory module; and panels 26A and 26B are functional blocks of a host device including a memory module Figure 27A and 27B are functional block diagrams of a memory module having an adjustment update rate module; Fig. 28 is a flow chart illustrating exemplary steps for providing an adjustment update rate; and Fig. 29 is a diagram for providing A flowchart of exemplary steps for adjusting the update rate; Figure 30 is a flow chart illustrating exemplary steps for providing an adjusted update rate; and Figure 31 is a flow chart illustrating exemplary steps for providing an adjusted update rate; Figure 32A is a flowchart Functional block diagram of the hard disk drive; Fig. 32B is a functional block diagram of the DVD drive; Fig. 32C is a functional block diagram of the high definition television; Fig. 32D is a functional block diagram of the vehicle control system; and Fig. 32E is a mobile phone Functional block diagram; Figure 32F is a functional block diagram of the set-top box; and Figure 32G is a functional block diagram of the mobile device.

1000. . . Device

1004. . . Memory controller

1008. . . Memory module

1012. . . Adjust update rate module

1016. . . Test module

1020. . . Memory

1024. . . Buffer and Error Correction (BEC) Module

1028. . . Random access memory (RAM)

1032. . . Content addressable memory (CAM)

1036. . . Non-volatile (NV) memory

Claims (15)

A memory system comprising: a first memory comprising a memory unit; a content addressable memory (CAM) comprising: a content addressable memory (CAM) unit; storing the selected one of the memory units a location; and storing data having the addresses in corresponding memories of the CAM memory cells, and extracting from the corresponding ones of the CAM memory cells Data and an adjustment update module for storing data from selected memory cells of the memory unit into the CAM memory unit to increase or maintain the memory unit update of the first memory Between the time periods. The memory system of claim 1, wherein the adjustment and update module uses G of the CAM memory cells to store data from the G cells in the memory cells to maintain the The time period between updates of the memory cells, and G is an integer greater than or equal to one. The memory system of claim 1, wherein the adjustment and update module uses H of the CAM memory cells to store H data from the memory cells, and selectively increases The time period between updates of the memory cells, and H is an integer greater than or equal to one. The memory system of claim 1, further comprising: a test module that communicates with the first memory and the adjustment update module, and uses at least one update rate to test the memory units . The memory system of claim 1, further comprising: a second memory; a non-volatile memory, wherein the first memory comprises a memory block; a control module for storing data from the at least one of the memory blocks into the second memory during testing of at least one of the memory blocks having the first address The second address is stored, and the first address and the second address are stored in the non-volatile memory. The memory system of claim 5, wherein the storage capacity of the second memory and the non-volatile memory is less than: a storage capacity of the first memory. The memory system of claim 5, wherein the CAM has a memory capacity that is less than the at least one of the memory blocks. The memory system of claim 5, wherein the control module selectively tests at least one of the memory blocks. A fully buffered dual in-line memory module (FB DIMM) comprising a memory system as in claim 5 of the patent application. The memory system of claim 5, further comprising: a first buffer module that buffers the control signal. The memory system of claim 10, wherein the control module, the second memory, the non-volatile memory, and at least one of the CAMs are integrated with the first buffer module. In the body circuit. The memory system of claim 10, further comprising: Y memory volume circuits (ICs) in communication with the first buffer module, and Y being an integer greater than one. For example, the memory system described in claim 10 of the patent scope further includes: Z memory modules each including a buffer module, wherein the Z-1 memory modules of the Z memory modules communicate with the previous one of the Z memory modules, and The buffer module of the first one of the Z memory modules communicates with the first buffer module, and wherein Z is an integer greater than zero. The memory system of claim 5, wherein each of the memory blocks comprises a data page. The memory system of claim 5, wherein the first memory, the second memory, the non-volatile memory, and the control module are disposed on a printed circuit board including an edge connector .