TWI461884B - Clock generating circuit and associated method for generating output clock signal - Google Patents

Description

Clock generation circuit and related method for generating output clock signal

The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit and related method that can generate a specific duty cycle.

For some circuits, such as a switching-capacitor circuit or a double data rate (DDR) dynamic random access memory (DRAM), clock signal The duty cycle is very important. If the duty cycle of the clock signal deviates too much from 50%, it may affect the performance of the circuit. In the most serious case, the function of the circuit may be abnormal. Therefore, in general, there is a need in the system for a circuit that can adjust the duty cycle of the clock signal.

In general, the conventional technique uses a digital delay line to adjust the duty cycle of the clock signal, such as "An all-digital 50% duty-cycle corrector, IEEE, 2004, page II-925-II-928", however, The length of the digital delay line is affected by the frequency of the clock signal. When the frequency of the pulse signal is low, a long digital delay line is required, resulting in an increase in the area of the chip. In addition, the design of the digital delay line itself also requires a long length to reduce the quantization error of the above circuit.

Accordingly, it is an object of the present invention to provide a clock generation circuit and associated method that can generate a specific duty cycle, the wafer area of which is not affected by the frequency of the clock signal and the quantization error of the circuit to solve the above problem.

According to an embodiment of the invention, a clock generation circuit for generating an output clock signal includes a pulse generator, a counter, a processing unit, and a clock generator. The pulse generator is configured to generate a first pulse signal; the counter is coupled to the pulse wave generator, wherein the counter uses a reference clock signal after the pulse wave generator generates the first pulse signal Starting to count to generate a count value; the processing unit is coupled to the counter for receiving the count value, and when the count value reaches a critical value, generating a second pulse signal; the clock generator coupling The pulse wave generator and the processing unit are configured to generate the output clock signal according to the first pulse signal and the second pulse signal.

According to another embodiment of the present invention, a method for generating an output clock signal includes: generating a first pulse signal; and after generating the first pulse signal, using a reference clock signal to start counting, Generating a first count value; receiving the first count value, and when the first count value reaches a threshold value, generating a second pulse signal; and according to the first pulse signal and the second pulse wave Signal to generate the output clock signal.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a clock generation circuit 100 for generating an output clock signal CLK_OUT according to a first embodiment of the present invention. As shown in FIG. 1, the clock generation circuit 100 includes a pulse generator 110, a counter 120, a processing unit 130, and a clock generator (in this embodiment, the clock generator is a set/weight Set (Reset, SR) latch 140). The clock generation circuit 100 is configured to receive an input clock signal CLK_IN and adjust the input clock signal CLK_IN to an output clock signal CLK_OUT having a specific duty cycle.

Please refer to Fig. 1 and Fig. 2 at the same time. Fig. 2 is a timing chart of each signal shown in Fig. 1. In the operation of the clock generation circuit 100, first, the pulse generator 110 receives the input clock signal CLK_IN and triggers by the edge of the input clock signal CLK_IN (in this embodiment, a positive edge trigger) to generate a first A pulse signal PA, wherein the pulse signal PA has the same period as the input clock signal CLK_IN. Then, the counter 120 is triggered by the edge of the first pulse signal PA (in this embodiment, a positive edge trigger) to start counting by using a reference clock signal CLK_REF generated by the oscillator 150 to generate a first meter. The value CV is passed and the first count value CV is transmitted to the processing unit 130. Then, the processing unit 130 receives the first count value CV, and when the first count value CV reaches a critical value, generates a second pulse signal PB, wherein the threshold is used to indicate the corresponding corresponding period of the work cycle. For example, if the period width T of the first pulse signal PA corresponds to a count value of 10, it is assumed that the clock generation circuit 100 is used to generate an output clock signal CLK_OUT of 50% duty cycle. The value is 5; if the clock generation circuit 100 is used to generate the output clock signal CLK_OUT of 30% duty cycle, the threshold value is 3... and so on. In addition, the threshold may be set by the designer or generated by the clock generation circuit 100, and the details are described below. Finally, the SR latch 140 receives the first pulse signal PA and the second pulse signal PB to generate an output clock signal CLK_OUT.

Regarding the threshold value used by the processing unit 130, in an embodiment of the invention, the counter 120 uses the reference clock signal CLK_REF to calculate before the clock generation circuit 100 starts generating the output clock signal CLK_OUT having the specific duty cycle. a period width T of the first pulse signal PA to generate a second count value, after which the processing unit 130 generates the threshold value according to the second count value and the specific duty cycle (for practical examples, refer to the previous paragraph) The threshold is temporarily stored in the processing unit 130 for use in subsequent operations.

In the clock generation circuit 100, regardless of the frequency of the input clock signal CLK_IN, the clock generation circuit 100 can surely generate the output clock signal CLK_OUT having an ideal duty cycle, and therefore, the wafer area of the clock generation circuit 100 does not It is affected by the frequency of the input clock signal CLK_IN and the quantization error of the circuit.

In addition, in the clock generation circuit 100, the processing unit 130 operates using the first pulse signal PA. However, in other embodiments of the present invention, the processing unit 130 can also use the input clock signal CLK_IN instead. Operation, these design changes are subject to the scope of the present invention.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of a clock generation circuit 300 for generating an output clock signal CLK_OUT according to a second embodiment of the present invention. As shown in FIG. 3, the clock generation circuit 300 includes a pulse generator 310, a counter 320, a processing unit 330, and a clock generator (in this embodiment, the clock generator is an SR latch). 340). The clock generation circuit 300 is configured to receive an input clock signal CLK_IN and adjust the input clock signal CLK_IN to an output clock signal CLK_OUT having a specific duty cycle.

Referring to FIG. 2 and FIG. 3 simultaneously, in the operation of the clock generation circuit 300, first, the pulse generator 310 receives the input clock signal CLK_IN and is triggered by the edge of the input clock signal CLK_IN (in this embodiment A positive edge trigger generates a first pulse signal PA, wherein the pulse signal PA has the same period as the input clock signal CLK_IN. Then, the counter 320 is triggered by the edge of the input clock signal CLK_IN (in this embodiment, a positive edge trigger) to start counting by using a reference clock signal CLK_REF generated by the oscillator 350 to generate a first count value. CV, and the first count value CV is transmitted to the processing unit 330. Then, the processing unit 330 receives the first count value CV, and when the first count value CV reaches a critical value, generates a second pulse signal PB, wherein the threshold is used to indicate the corresponding corresponding period of the work cycle. The value is set by the designer or generated by the clock generation circuit 300. Finally, the SR latch 340 receives the first pulse signal PA and the second pulse signal PB to generate an output clock signal CLK_OUT.

In addition, in the clock generation circuit 300, the processing unit 330 operates by using the input clock signal CLK_IN. However, in other embodiments of the present invention, the processing unit 330 can also use the first pulse signal PA instead. Operation, these design changes are subject to the scope of the present invention.

Please refer to FIG. 4, which is a diagram of a method for generating an output clock signal according to an embodiment of the invention. Referring to Figures 1~4, the process is described as follows:

Step 400: Generate a first pulse signal.

Step 402: After generating the first pulse signal, use a reference clock signal to start counting to generate a first count value.

Step 404: Receive the first count value, and when the first count value reaches a critical value, generate a second pulse signal.

Step 406: Generate the output clock signal according to the first pulse signal and the second pulse signal.

Briefly summarized, the present invention, in a clock generation circuit and related method for generating an output clock signal, uses a pulse generator, a counter, a processing unit, and a clock generator to generate The output clock signal of a specific duty cycle is different from the conventional technique of adjusting the duty cycle of the clock signal by using the digital delay line. The chip area of the clock generating circuit of the present invention is not affected by the frequency of the input clock signal and The influence of the quantization error of the circuit is therefore more efficient and lower cost.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 300. . . Clock generation circuit

110, 310. . . Pulse generator

120, 320. . . counter

130, 330. . . Processing unit

140, 340. . . SR latch

150, 350. . . Oscillator

400~406. . . step

1 is a schematic diagram of a clock generation circuit for generating an output clock signal according to a first embodiment of the present invention.

Fig. 2 is a timing chart of the signals shown in Fig. 1.

FIG. 3 is a schematic diagram of a clock generation circuit for generating an output clock signal according to a second embodiment of the present invention.

Figure 4 is a diagram of a method for generating an output clock signal in accordance with an embodiment of the present invention.

100. . . Clock generation circuit

110. . . Pulse generator

120. . . counter

130. . . Processing unit

140. . . SR latch

150. . . Oscillator

Claims (11)

A clock generation circuit for generating an output clock signal includes: a pulse generator for generating a first pulse signal; and a counter coupled to the pulse generator, wherein the pulse After the wave generator generates the first pulse signal, the counter starts counting by using a reference clock signal to generate a first count value; a processing unit coupled to the counter for receiving the first count value And generating a second pulse signal when the first count value reaches a threshold value; and a clock generator coupled to the pulse wave generator and the processing unit for using the first pulse signal And the second pulse signal to generate the output clock signal, wherein the output clock signal is the same as the period of the first pulse signal, and a duty cycle of the output clock signal is the first pulse signal And the edge distance of the second pulse signal is determined. The clock generation circuit of claim 1, wherein the counter is triggered by an edge of the first pulse signal to start counting using the reference clock signal. The clock generation circuit of claim 1, wherein the pulse wave generator is triggered by an edge of an input clock signal to generate the first pulse signal. The clock generation circuit of claim 3, wherein the counter is triggered by an edge of the input clock signal to start counting using the reference clock signal. The clock generation circuit of claim 1, wherein the clock generation circuit is configured to generate the output clock signal having a specific duty cycle, and the counter uses the reference clock signal Calculating a period width of the first pulse signal to generate a second count value, and the processing unit generates the threshold according to the second count value and the specific duty cycle. The clock generation circuit of claim 1, wherein the clock generator is a Set/Reset (SR) latch. A method for generating an output clock signal includes: generating a first pulse signal; after generating the first pulse signal, using a reference clock signal to start counting to generate a first count value Receiving the first count value, and when the first count value reaches a critical value, generating a second pulse signal; and generating the output clock according to the first pulse signal and the second pulse signal a signal, wherein the output clock signal is the same as the period of the first pulse signal, and a duty cycle of the output clock signal is determined by the edge distance of the first pulse signal and the second pulse signal. The method of claim 7, wherein the step of using the reference clock signal to start counting comprises: triggering by using an edge of the first pulse signal to start using the reference clock signal count. The method of claim 7, wherein the step of generating the first pulse signal comprises: triggering an edge of an input clock signal to generate the first pulse signal. The method of claim 9, wherein the step of using the reference clock signal to start counting comprises: triggering by using an edge of the input clock signal to start counting using the reference clock signal. The method of claim 7 is for generating the output clock signal having a specific duty cycle, and the method further comprises: calculating the first by using the reference clock signal The period width of the pulse signal is generated to generate a second count value; and the threshold value is generated according to the second count value and the specific duty cycle.