TWI460574B - Method of calibrating signal skews in mipi and related transmission system - Google Patents

Description

Method for correcting signal offset in mobile processor interface and related transmission system

The invention relates to a method for correcting signal offset and related transmission system, in particular to a method for correcting signal offset in a processor interface of an action industry and a related transmission system.

With the evolution of technology, electronic information products need to use high-speed serial transmission technology to support the increasing volume of data transmission, such as the use of mobile industry processor interface (MIPI), mobile display digital interface (Mobile Display Digital Interface (MDDI) and general serial bus (USB) transmission technologies. Among them, MIPI specifies a differential clock lane and scalable (from one to four) data lanes, which can adjust the data rate according to processor and peripheral requirements, and are widely used. Handheld devices such as smart phones or personal digital assistants (PDAs).

Figure 1 is a schematic illustration of a transmission system 10 of the prior art. The transmission system 10 employs four data channel MIPIs including a host side circuit HS, transmission channels 200-204, and a client side circuit CS. The main control circuit HS includes transmission circuits 110 to 114 for transmitting a clock signal CLK and data signals DATA1 to DATA4, respectively. The client circuit CS includes receiving circuits 310-314 for receiving the clock signal CLK and the data signals DATA1 to DATA4, respectively. The transmission circuits 110 to 114 transmit the clock signal CLK and the data signals DATA1 to DATA4 to the reception circuits 310 to 314 through the transmission channels 200 to 204, respectively.

2A-2D are signal diagrams of the prior art transmission system 10, showing waveforms of the clock signal CLK and the data signals DATA1 to DATA4. The client circuit CS reads the data signals DATA1 to DATA4 at the rising edge or the falling edge of the clock signal CLK. The setup time T _S is the shortest time between the rising edge of the clock signal CLK and the rising edge of the data signals DATA1 to DATA4, or the falling edge of the clock signal CLK and the falling edge of the data signals DATA1 to DATA4. The shortest time between. The hold time T _H is the shortest time between the rising edge of the clock signal CLK and the falling edge of the data signals DATA1 to DATA4, or the falling edge of the clock signal CLK and the rising edge of the data signals DATA1 to DATA4. The shortest time between.

In an ideal case, the phase of the clock signal CLK and the data signal DATA1 are balanced, that is, T _S =T _H , as shown in FIG. 2A. However, in practical applications, the length or load of the transmission channels 200 to 204 may be asymmetric, the output of the transmission circuits 110 to 114 may be asymmetric, the load of the receiving circuits 310 to 314 may be asymmetric, or the host circuit HS and the user terminal may be used. There are various factors such as the discontinuity of impedance between the circuits CS, and there is a skew in the MIDI, which causes the time of the clock signal CLK and the data signals DATA1 to DATA4 to reach the user circuit CS to be different. For example, the phase of the clock signal CLK may lead the data signal DATA2 (T _S <T _H ), as shown in Figure 2B; the phase of the clock signal CLK may lag behind the data signal DATA3 (T _S >T _H ) As shown in Fig. 2C; the phase difference between the clock signal CLK and the data signal DATA4 may be greater than the unit period UI (T _S <0), as shown in Fig. 2D.

In practical applications, MIDI usually contains a plurality of data transmission channels. If there is a different degree of phase lead or lag between the clock signal and the plurality of data signals, the fault-tolerant space of the signal offset is gradually increased in the trend of the clock signal frequency. (Settling time T _S and holding time T _H ) are getting narrower and narrower, so it is easy to cause data acquisition errors. In order to maintain the correct rate of data transmission, a method of correcting the signal offset in MIPI is needed.

The present invention provides a method for correcting a signal offset in a mobile industry processor interface, including transmitting, in a calibration mode, a clock signal and a first channel through a clock channel and a data channel of the mobile industry processor interface. Data signal; adjusting the phase of the clock signal and the first data signal to provide a corresponding one of the test clock signal and a first test data signal; and extracting the first test data signal according to the test clock signal Obtaining a first captured data; determining an optimal phase relationship corresponding to the one of the clock channel and the data channel according to the first captured data; and transmitting the clock signal and the data signal in a normal mode The signal delay of the clock channel and the data channel is adjusted according to the optimal phase relationship.

The present invention further provides a transmission system using a mobile industry processor interface, which includes a host terminal circuit for transmitting a clock signal and a first channel and a second channel respectively through the mobile industry processor interface. a data signal; a user terminal circuit for adjusting a signal delay of the first channel and the second channel according to an optimal phase relationship, comprising a receiving circuit for receiving the clock signal and the data signal; a correction circuit for adjusting a phase of the clock signal and the data signal to respectively provide a corresponding one of the test clock signal and a test data signal, and extracting the test data signal according to the test clock signal to obtain a Take the data and find the best phase relationship based on the captured data.

FIG. 3A is a schematic diagram of a transmission system 20 according to an embodiment of the present invention. The transmission system 20 uses the MIPI of four data channels, and includes a master terminal circuit HS, transmission channels 200-204, and a client circuit CS. The main control circuit HS includes transmission circuits 110 to 114 for transmitting a clock signal CLK and data signals DATA1 to DATA4, respectively. The client circuit CS includes receiving circuits 310-314 and a correction circuit 300. The receiving circuits 310-314 are respectively configured to receive the clock signal CLK and the data signals DATA1 to DATA4, and the correction circuit 300 is used for the clock signal CLK and the data. Signal offset between signals DATA1 to DATA4. The transmitting circuits 110 to 114 each include two low power transmitters LP_TX and one high speed transmitter HS_TX, and the receiving circuits 310 to 314 each include two low power receivers LP_RX and one high speed receiver HS_RX. The low power transmitter LP_TX and the low power receiver LP_RX can handle single-single-ended signals in a low power state, and the high speed transmitter HS_TX and high speed receiver HS_RX can handle high speed differential signals. Therefore, the transmission circuits 110 to 114 can transmit the sequence differential clock signal CLK and the data signals DATA1 to DATA4 to the receiving circuits 310 to 314 through the transmission channels 200 to 204, respectively.

FIG. 3B is a functional block diagram of the correction circuit 300 in the transmission system 20 of the embodiment of the present invention. The correction circuit 300 includes delay units DL0 DL DL4, serial-to-parallel conversion units S2P1 S S2P4, a frequency divider CD, a storage unit 320, a comparison unit 330, a calculation unit 340, and a control Unit 350. The correction circuit 300 can perform different signal delays on the clock signal CLK or the data signals DATA1 to DATA4, and then obtain the data pass zone of each channel, thereby obtaining the optimal delay time of each channel.

Figure 4 is a flow chart of the operation of the correction circuit 300, which includes the following steps:

Step 410: Enter the calibration mode, and perform step 420.

Step 420: Find an offset calibration table and perform step 430.

Step 430: Determine the correct area of the data corresponding to each channel according to the offset calibration table, and perform step 440.

Step 440: Determine whether the corresponding channel is successfully corrected according to the correct area of each data; if yes, go to step 450; if no, go to step 470.

Step 450: Find the center point of the correct region of each data, and determine the optimal phase relationship of each channel accordingly, and perform step 460.

Step 460: Enter the normal mode, and adjust the phase of the clock signal or the corresponding data signal according to the optimal phase relationship of each channel.

Step 470: Determine that the correction failed.

After entering the calibration mode in step 410, the delay units DL0-DL4 can provide different signal delays of the clock signal CLK and the data signals DATA1 to DATA4, respectively. Under different signal delay conditions, the phase relationship between the clock signal CLK and the data signals DATA1 to DATA4 is as shown in FIG. In this embodiment, the delay units DL0-DL4 can provide 31 sets of offset adjustment stages S0-S30: the offset adjustment stage S0 represents that the clock signal and the data signal are delayed by 0 unit time Td; the offset adjustment stage S1-S15 The clock signal is delayed by 1~15 unit time Td, and the data signals DATA1~DATA4 are delayed by 0 unit time Td; the offset adjustment stage S16~S30 represents the delay of the clock signal by 0 unit time Td, and the data signal DATA1 Each of DATA4 is delayed by 1 to 15 unit times Td. Each offset adjustment phase corresponds to a specific clock delay index (an integer between -15 and 15).

Figures 6A to 6D are signal diagrams under different signal delay conditions. For the sake of explanation, only the clock signal CLK and the data signal DATA1 are taken as an example. 6A and 6B are timing charts showing signals in the offset adjustment stages S0 to S15, and FIGS. 6C and 6D are timing charts showing signals in the offset adjustment stages S0, S16 to S30.

In the embodiment shown in FIG. 6A, the master terminal circuit HS transmits the clock signal CLK to the receiving circuit 310 of the client circuit CS through the transmitting circuit 110, and transmits the data signal DATA1 of "01010101" through the transmitting circuit 111 to The receiving circuit 311 of the client circuit CS. Then, the delay unit DL0 delays the clock signal CLK by 0 unit time Td, and the delay unit DL1 delays the data signal DATA1 by 0 to 15 unit time Td, respectively, thereby providing a test clock signal CLK0' and 16 pens. Test data signals DT0'~DT15'. The client circuit CS can capture the test data signals DT0'-DT15' at the rising/falling edge of the pulse signal CLK' during the test, and can extract 8 sequence bits BT1~BT8 from each test data signal, and then transmit the sequence. The parallel conversion unit S2P1 is merged into parallel data DP0 to DP15, respectively.

In the embodiment shown in FIG. 6B, the master terminal circuit HS transmits the clock signal CLK to the receiving circuit 310 of the client circuit CS through the transmitting circuit 110, and transmits the data signal DATA1 of "00110011" through the transmitting circuit 111 to The receiving circuit 311 of the client circuit CS. Then, the delay unit DL0 delays the clock signal CLK by 0 unit time Td, and the delay unit DL1 delays the data signal DATA1 by 0 to 15 unit time Td, respectively, thereby providing a test clock signal CLK0' and 16 pens. Test data signals DT0'~DT15'. The client circuit CS can capture the test data signals DT0'-DT15' at the rising/falling edge of the pulse signal CLK' during the test, and can extract 8 sequence bits BT1~BT8 from each test data signal, and then transmit the sequence. The parallel conversion unit S2P1 is merged into parallel data DP0 to DP15, respectively.

In the embodiment shown in FIG. 6C, the master terminal circuit HS transmits the clock signal CLK to the receiving circuit 310 of the client circuit CS through the transmitting circuit 110, and transmits the data signal DATA1 of "01010101" through the transmitting circuit 111 to The receiving circuit 311 of the client circuit CS. Then, the delay unit DL0 delays the clock signal CLK by 0 to 15 unit times Td, and the delay unit DL1 delays the data signal DATA1 by 0 unit time Td, thereby providing 16 test clock signals CLK0' to CLK15. 'and a test data signal DT0'. The client circuit CS can capture the test data signal DT0' at the rising/falling edge of the pulse signal CLK0'~CLK15' during the test, and can respectively capture 8 sequence bits according to each test clock signal CLK0'~CLK15' BT1 to BT8 are further combined into parallel data DP0 to DP15 through the sequence-to-parallel conversion unit S2P1.

In the embodiment shown in FIG. 6D, the master terminal circuit HS transmits the clock signal CLK to the receiving circuit 310 of the client circuit CS through the transmitting circuit 110, and transmits the data signal DATA1 of "00110011" through the transmitting circuit 111 to The receiving circuit 311 of the client circuit CS. Then, the delay unit DL0 delays the clock signal CLK by 0 to 15 unit time Td, and the delay unit DL1 delays the data signal DATA1 by 0 unit time Td, thereby providing 16 test clock signals CLK0'~ CLK15' and a test data signal DT0'. The client circuit CS can capture the test data signal DT0' at the rising/falling edge of the pulse signal CLK0'~CLK15' during the test, and can respectively capture 8 sequence bits according to each test clock signal CLK0'~CLK15' BT1 to BT8 are further combined into parallel data DP0 to DP15 through the sequence-to-parallel conversion unit S2P1.

Figure 7 is a graph showing the results of the 6A to 6D graphs. The comparing unit 330 can compare the values of each of the captured data and the corresponding expected data, and then generate comparison results R1 and R2 corresponding to each offset adjustment phase and different value data signals. If the comparison result R1 shows that the "01010101" data signal DATA1 is processed by the offset adjustment stages S0 to S30, it will contain two data correct areas, and the instantaneous pulse delay index is between -6 and 3 and between 14 and 15; If the comparison result R2 shows that the "00110011" data signal DATA1 is processed by the offset adjustment stages S0 to S30, it will contain a single data correct area, and the instantaneous pulse delay index is between -6 and 3. When determining the optimal phase relationship, the correct area of multiple data will increase the difficulty of judgment. Therefore, the comparison circuit of the present invention performs specific logic operations on R1 and R2, for example, performing an AND operation (R1 & R2) to ensure that each expected data has only a single data correct region. For each offset adjustment phase, the present invention can determine the optimal phase relationship based on the result of a particular data signal (R1 or R2); alternatively, the present invention can simultaneously determine the results (R1 and R2) of different specific data signals. The best phase relationship.

Figures 8A-8B and 9A-9B illustrate the operation of the calibration circuit 300 of the present invention when performing steps 420-470. The foregoing embodiments shown in FIGS. 6A to 6D and FIG. 7 are described by the data signal DATA1. After the data signals DATA2 to DATA4 are processed in the offset adjustment stages S0 to S30 in the same manner, a step 420 can be found. The calibration table is offset and stored in storage unit 320.

Figures 8A and 9A show the offset calibration tables obtained in both cases. REG1~4 are 32-bit registers in the storage unit 310 for storing the calibration results of the transmission channels 201-204, wherein "1" represents the correct area of the data, and "0" represents the data error area.

In Figures 8B and 9B, steps 431-439 perform the operation of step 430 for computing unit 340, the detailed steps of which are illustrated as follows:

Step 431: Translating the memory data D1(A) to D4(A) of the registers REG1 to REG4 to the right by one bit to obtain the data D1(B) to D4(B), respectively.

Step 432: AND data D1 (A) to D4 (A) and data D1 (B) to D4 (B) are respectively ANDed to obtain data D1 (C) to D4 (C), respectively.

Step 433: The data D1 (C) to D4 (C) are shifted to the right by one bit to obtain the data D1 (D) to D4 (D), respectively.

Step 434: XOR the data D1 (C) to D4 (C) and the data D1 (D) to D4 (D) to obtain the data D1 (E) to D4 (E), respectively.

Step 435: The data D1(E) to D4(E) are shifted to the left by one bit to obtain the data D1(F) to D4(F), respectively.

In step 440, the present invention calculates the total value SUM of all the bits in the data D1(F) - D4(F). If SUM is 2, it is determined that the calibration is successful, and then step 450 is performed to obtain the corresponding center point according to the position of the bit 1 in the data D1(F) to D4(F), and the optimal phase of each channel is obtained accordingly. The relationship is as shown in Figs. 8A-8B; if SUM is not 2, step 470 is performed to determine the correction failure, as shown in Figs. 9A and 9B.

After determining the optimal phase relationship for each channel, the present invention can enter the normal mode in step 460 and adjust the phase of the clock signal or the corresponding data signal according to the optimal phase relationship of each channel.

For each transmission channel in MIDI, the present invention can perform offset adjustment for different stages of data signals of one or more specific values, and then find the optimal phase relationship of each transmission channel, so that it can be based on the most Good phase relationship to adjust the phase of the clock signal or the corresponding data signal.

In summary, in a non-ideal transmission environment, even if there is a different degree of signal offset in each channel of MIDI, the present invention can synchronize the timing of all signals, thereby ensuring the correctness of data reading.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 20. . . Transmission system

300. . . Correction circuit

320. . . Storage unit

330. . . Comparison unit

340. . . Computing unit

350. . . control unit

200～204. . . Transmission channel

110～114. . . Transmission circuit

310～314. . . Receiving circuit

200～204. . . Transmission channel

CD. . . Frequency divider

HS. . . Master terminal circuit

CS. . . Client circuit

LP_TX. . . Low power transmitter

HS_TX. . . High speed transmitter

LP_RX. . . Low power receiver

HS_RX. . . High speed receiver

DL0~DL4. . . Delay unit

S2P1～S2P4. . . Sequence to parallel conversion unit

410～470. . . step

Figure 1 is a schematic diagram of a transmission system of the prior art.

Figures 2A through 2D show signal diagrams of prior art transmission systems in operation.

FIG. 3A is a schematic diagram of a transmission system in an embodiment of the present invention.

FIG. 3B is a functional block diagram of a correction circuit in the transmission system according to the embodiment of the present invention.

Figure 4 is a flow chart showing the operation of the correction circuit in the embodiment of the present invention.

Figure 5 shows the phase relationship between the clock signal and the data signal under different signal delay conditions.

Figures 6A to 6D are signal diagrams of the correction results under different signal delay conditions.

Figure 7 is a graph showing the results of the 6A to 6D graphs.

8A-8B and 9A-9B are schematic diagrams showing the operation of the correction circuit in accordance with an embodiment of the present invention.

20. . . Transmission system

300. . . Correction circuit

320. . . Storage unit

330. . . Comparison unit

340. . . Computing unit

350. . . control unit

200～204. . . Transmission channel

110～114. . . Transmission circuit

310～314. . . Receiving circuit

200～204. . . Transmission channel

CD. . . Frequency divider

HS. . . Master terminal circuit

CS. . . Client circuit

LP_TX. . . Low power transmitter

HS_TX. . . High speed transmitter

LP_RX. . . Low power receiver

HS_RX. . . High speed receiver

S2P1～S2P4. . . Sequence to parallel conversion unit

Claims (4)

A method for correcting a signal offset in a Mobile Industry Processor Interface (MIPI), comprising: a calibration channel, a clock channel and a data channel through a processor interface of the mobile industry Transmitting a clock signal and a first data signal respectively; delaying the clock signal by 0 to (N-1) unit time respectively to provide the first to N test clock signals, wherein N is an integer greater than 1; Delaying the first data signal by 0 to (N-1) unit time to provide the first to N first test data signals respectively; and extracting the first to N pens according to the first test clock signal The first test data signal is obtained according to the first to N test clock signals to obtain the first first test data signal, thereby obtaining the first data of the 2N pen; determining whether each of the first captured data is Corresponding to the predetermined data corresponding to one of the first data signals; determining, in each of the first captured data, the bit that meets the predetermined data as a correct area of the data; and determining the most central point according to one of the correct areas of the data Good phase System; and When the clock signal and the data signal are transmitted in a normal mode, the signal delay of the clock channel and the data channel is adjusted according to the optimal phase relationship. A method for correcting a signal offset in an action industry processor interface, comprising: transmitting, in a calibration mode, a clock signal through a clock channel of a processor interface of the mobile industry; and in the correcting mode, transmitting the signal One of the data channels of the industrial processor interface transmits a first data signal and a second data signal, wherein the first data signal and the second data signal have different values; delaying the clock signal by 0 to (N- 1) unit time to provide the first to N test clock signals respectively, where N is an integer greater than 1; delay the first data signal by 0 to (N-1) unit time respectively to provide the first to N pen first test data signal; delay the second data signal by 0 to (N-1) unit time to provide the first to N second test data signals respectively; according to the first test clock signal Taking the first to N first test data signals and extracting the first first test data signal according to the first to N test clock signals respectively, thereby obtaining the first data of the 2N pen; The first test clock signal is used to capture 1 to N second measured Pen Test the data signal and retrieve the first second test data signal according to the first to N test clock signals respectively, thereby obtaining the second data of the 2N pen; determining whether each of the first captured data meets the corresponding Determining, according to one of the first data signals, a first predetermined data; determining whether each of the second captured data meets a second predetermined data corresponding to one of the second data signals; and matching each of the first captured data to the first The bit of the predetermined data is determined as a first data correct area and the bit of each second captured data that meets the second predetermined data is determined as a second data correct area; according to the first data correct area and the The correct area of the second data determines the correct area corresponding to one of the data channels; and the center point of one of the correct areas of the best data determines an optimal phase relationship between the clock channel and the data channel; When the clock signal and the first data signal are transmitted in a normal mode, the signal delay of the clock channel and the data channel is adjusted according to the optimal phase relationship. A transmission system using an action industry processor interface, comprising: a host side circuit for transmitting a clock signal through one of the first channel and the second channel of the mobile industry processor interface And a data signal; a client side circuit for adjusting a signal delay of the first channel and the second channel according to an optimal phase relationship, comprising: a receiving circuit, configured to receive the clock signal and the data signal a correction circuit for: delaying the clock signal by 0 to (N-1) unit time respectively to provide the first to N test clock signals, wherein N is an integer greater than 1: the data signal Delaying from 0 to (N-1) unit time to provide the first to N test data signals respectively; and extracting the first to N test data signals according to the first test pulse signal and respectively according to the first 1 to N test clock signals to capture the first test data of the first test, and then obtain 2N pen data; determine whether each of the captured data meets the predetermined data corresponding to one of the data signals; The bit in the captured data that meets the predetermined data is determined as a data correct region; and an optimal phase relationship between the first channel and the second channel is determined according to a central point of the correct region of the data. The transmission system of claim 3, wherein the correction circuit comprises: a delay unit for adjusting the phase of the clock signal and the data signal a comparison unit for comparing the value of the captured data with the predetermined data corresponding to the data signal; a storage unit for storing the comparison result of the comparison unit; and a calculation unit for using the comparison unit The comparison result finds the optimal phase relationship; and a control unit is configured to control the delay unit according to the optimal phase relationship to adjust the signal delay of the first channel and the second channel.