TWI459507B - Method for fabricating through-silicon via structure - Google Patents

Description

Method for making 矽through electrode

The present invention relates to a method for fabricating a through-silicon via (TSV), and more particularly to a method for fabricating a tantalum through-electrode while maintaining the thickness of the interlayer dielectric layer.

The through-electrode (TSV) technology is a novel semiconductor technology.矽Through-electrode technology mainly solves the problem of interconnection between wafers, and belongs to a new three-dimensional space three-dimensional packaging technology. The popular 矽 through-electrode technology provides wafer level for micro-electromechanical systems (MEMS), optoelectronics and electronic components through the stacking of three-dimensional space and the creation of products that are more suitable for light, thin, short and small through the through-electrode. The packaging process technology required for packaging.

The through-electrode technology is to etch holes on the wafer by etching or laser, and then electrically conductive materials such as copper, polysilicon, tungsten, etc. are filled into the vias (Via) to form conductive channels (ie, the inner and outer bonding lines are connected). ). Finally, the wafer or the grain is thinned and then stacked and bonded to become a three-dimensional stacked integrated circuit (3D IC). In this way, the wire bonding method can be removed. By etching or lasering the Via and turning on the electrodes, it not only eliminates the wiring space, but also reduces the use area of the board and the volume of the package. Due to the internal bonding distance of the 矽-through electrode technology, that is, the thickness of the thinned wafer or the die, the internal connection path of the three-dimensional space-stacked integrated circuit is more than that of the conventional stacked package with wire bonding. Short, the relative transfer speed between the wafers is faster, the noise is smaller, and the performance is better. Especially in the central unit (CPU) and cache memory, as well as data transfer in memory card applications, it can highlight the performance advantages of the short-distance internal joint path of the through-electrode technology. In addition, the package size of the three-dimensional space-stacked integrated circuit is equivalent to the grain size. In the field of portable electronic products that emphasize multi-function and small size, the miniaturization of three-dimensional space-stacked integrated circuits is the primary factor in market introduction.

At present, the process of widely fabricating a through electrode is mainly performed on a surface of a semiconductor substrate to complete a desired MOS transistor, such as a complementary MOS transistor, and then formed through the interlayer dielectric layer and connected to the MOS transistor. Contact the plug. Next, a tantalum through electrode filled with a dielectric layer for isolation and a copper metal for conduction is formed in the interlayer dielectric layer and the semiconductor substrate. In the process of forming the contact plug and the through electrode, multiple chemical mechanical polishing is required, and each chemical mechanical polishing process is used to grind different materials.

It should be noted that the polishing process generally performed by chemical mechanical polishing relies on different removal rates to stop the polishing process to a specific material layer. Since the interlayer dielectric layer and the dielectric layer covering the pass-through electrode for separating the same are the same dielectric materials, the two material layers are easily removed by the same process in the chemical mechanical polishing process. The rate does not effectively stop the grinding step. Under these conditions, the thickness of the interlayer dielectric layer will become difficult to control, and in most cases, it is easy to lose too much interlayer dielectric layer to cause a problem of insufficient interlayer dielectric thickness.

Therefore, the present invention discloses a method for fabricating a tantalum through electrode to improve the problem that the interlayer dielectric layer is easily lost in the current process.

A preferred embodiment of the invention discloses a method of fabricating a germanium through electrode, comprising the steps of: providing a semiconductor substrate; forming at least one MOS transistor on the surface of the semiconductor substrate; forming a dielectric layer on the semiconductor substrate And covering the MOS transistor; forming a contact plug opening connecting the MOS transistor in the dielectric layer; forming a first conductive layer on the dielectric layer and filling the contact plug Forming an etching process, forming a via via in the conductive layer, the dielectric layer and the semiconductor substrate; filling a second conductive layer in the through via and covering a portion of the first a surface of the conductive layer; and performing a planarization process to remove a portion of the second conductive layer up to the surface of the first conductive layer.

Please refer to FIG. 1 to FIG. 6 . FIG. 1 to FIG. 6 are schematic diagrams showing a method for fabricating a through-electrode according to a preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 12 is first provided, for example, a monocrystalline germanium (monocrystalline). Silicon), gallium arsenide (GaAs) or other substrate made of a semiconductor material well known in the art. Then, at least one MOS transistor 14 is formed on the surface of the semiconductor substrate 12 according to a standard MOS transistor process, such as a P-type MOS transistor, an N-type MOS transistor, or a complementary type. A metal oxide semiconductor (CMOS) transistor, or various other semiconductor components. The MOS semiconductor transistors 14 may each have a standard transistor structure such as a gate, a sidewall, a lightly doped source drain, a source/drain region, and a deuterated metal layer, which are not described herein.

An interlayer dielectric layer 16 having a thickness of several thousand angstroms, such as about 3000 angstroms, is then formed and covers the entire MOS transistor 14. The interlayer dielectric layer 16 is preferably composed of a composite material layer composed of tetraethylorthosilicate (TEOS) and phosphosilicate glass (PSG), but is not limited thereto. The interlayer dielectric layer 16 may also be composed of a BPSG, a low-k material, and a stress material such as a tensile layer may be selectively interposed between the interlayer dielectric layer 16 and the MOS transistor 14. A stress or tensile stress tantalum nitride material, an etch stop layer such as a tantalum nitride material, a liner such as a thin oxide layer, or a combination thereof.

Then, a pattern transfer process is performed. For example, a patterned photoresist layer (not shown) is used as a mask to etch at least one contact hole 18 in the interlayer dielectric layer 16, and then a conductive material composed of tungsten is formed. The contact hole 18 is filled on the surface of the interlayer dielectric layer 16 to connect the conductive material filling the contact hole 18 to the gold oxide. The semiconductor transistor 14 is formed with a conductive layer 20 on the interlayer dielectric layer 16, as shown in FIG. Wherein, before the formation of the conductive layer 20, an adhesive layer composed of tantalum (Ta), tantalum (Tatan), titanium (Ti), titanium nitride (TiN) or a combination thereof may be selectively formed ( Adhesive layer). The conductive material of the conductive layer 20 may be other conductive materials other than W such as aluminum, copper, or alloys thereof.

As shown in FIG. 3, another pattern transfer process is subsequently performed, for example, another patterned photoresist layer (not shown) is formed on the surface of the conductive layer 20, and then the patterned photoresist layer is used as a mask for a single time. Or a plurality of etching processes to form a via via 22 in the conductive layer 20, the interlayer dielectric layer 16, and the semiconductor substrate 12.

As shown in FIG. 4, an insulating layer 24 is then formed to penetrate the sidewalls and the bottom of the via 22 while covering the surface of the conductive layer 20. The insulating layer 24 is preferably used as a barrier between the subsequent tantalum through electrode and the semiconductor substrate 12 so that the through electrode and the semiconductor substrate 12 are not directly electrically connected. In the present embodiment, the insulating layer 24 may comprise an insulating material such as an oxide or a nitride, and may be composed of a single layer or a composite material layer.

Then, a barrier layer 26 and a seed layer 28 are formed on the surface of the insulating layer 24 by chemical vapor deposition (CVD), and then a metal layer 30 made of copper is formed by electroplating. The layer 28 is surfaced and fills the entire through hole 22 . The barrier layer 26 may be composed of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) or a combination thereof. In order to prevent the copper ions in the metal layer 30 from migrating outwardly into the insulating layer 24, the seed layer 28 is attached to the insulating layer 24 with copper ions in the metal layer 30. Follow-up copper plating process. It should be appreciated that the metal layer 30 can be other conductive materials than copper, and the seed layer 28 is selectively present and its material will vary with the metal layer 30.

As shown in FIG. 5, a planarization process is then performed using the conductive layer 20 as a stop layer, for example, removing a portion of the metal layer 30, the seed layer 28, and the barrier layer provided on the surface of the conductive layer 20 by a chemical mechanical polishing process. 26 and the insulating layer 24, such that the surface of the metal layer 30 filled in the through-via via 22 is flush with the conductive layer 20 and simultaneously exposes the surface of the conductive layer 20. Then, as shown in FIG. 6, another planarization process is performed, for example, the conductive layer 20 is completely removed by chemical mechanical polishing and the interlayer dielectric layer 16 disposed underneath and the conductive material disposed in the contact hole 18 are exposed. The contact plug 34 and the tantalum through electrode 32 of the preferred embodiment of the present invention are simultaneously formed in the interlayer dielectric layer 16. In addition, a stop layer having a different removal rate from the conductive layer 20 may be selectively formed on the conductive layer 20, and this embodiment is also within the scope of the present invention.

It should be noted that the present invention mainly preserves the tungsten conductive layer 20 on the surface of the interlayer dielectric layer 16 before forming the via hole 22, and then stops the polishing process on the tungsten conductive layer 20 after subsequently grinding the copper metal layer 30. The surface, followed by another polishing process, removes the remaining tungsten conductive layer 20 in an in-situ or off-site manner. Due to the tungsten conductive layer 20 and the interlayer dielectric layer disposed therebelow 16 will have different removal rates during the grinding process, so that the removal of the conductive layer 20 by the chemical mechanical polishing process can effectively control the end point of the polishing and thereby control the thickness of the interlayer dielectric layer 16 to make the grinding In the process, too much interlayer dielectric layer 16 is not lost, resulting in a problem of insufficient thickness.

Finally, after the conductive layer 20 is removed, a back-end-of-the-line (BEOL) process is performed. For example, a plurality of dielectric layers may be formed on the interlayer dielectric layer 16 and the germanium through electrode 32 (FIG. Not shown) and with a metal interconnect and contact pad process to complete a plurality of metal interconnect structures and contact pads connecting the contact plugs 34.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

12‧‧‧Semiconductor substrate

14‧‧‧Gold Oxygen Semiconductor Crystal

16‧‧‧Interlayer dielectric layer

18‧‧‧Contact hole

20‧‧‧ Conductive layer

22‧‧‧Wear through the guide hole

24‧‧‧Insulation

26‧‧‧Barrier layer

28‧‧‧ seed layer

30‧‧‧metal layer

32‧‧‧矽through electrode

34‧‧‧Contact plug

1 to 6 are schematic views showing a method of fabricating a solid electrode according to a preferred embodiment of the present invention.

12. . . Semiconductor substrate

14. . . Metal oxide semiconductor transistor

16. . . Interlayer dielectric layer

18. . . Contact hole

twenty two. . . Through the guide hole

twenty four. . . Insulation

26. . . Barrier layer

28. . . Seed layer

30. . . Metal layer

32. . .矽through electrode

34. . . Contact plug

Claims (12)

A method of fabricating a germanium through electrode, comprising: providing a semiconductor substrate; forming at least one semiconductor component on a surface of the semiconductor substrate; forming a dielectric layer on the semiconductor substrate and covering the semiconductor component, and having the dielectric layer At least one contact hole; forming a first conductive layer on the dielectric layer and filling the contact hole; performing an etching process to form a via guide in the first conductive layer, the dielectric layer and the semiconductor substrate a second conductive layer is filled in the through-via via and covers a portion of the surface of the first conductive layer; and a first planarization process is performed to remove a portion of the second conductive layer until the surface of the first conductive layer . The method of claim 1, wherein before the filling the second conductive layer, an insulating layer is formed on the surface of the first conductive layer and the sidewalls and the bottom of the through-via. The method of claim 2, wherein the first planarization process further comprises removing a portion of the second conductive layer and a portion of the insulating layer up to a surface of the first conductive layer. The method of claim 2, wherein the filling of the second conductive layer further comprises forming a barrier layer on the surface of the insulating layer. The method of claim 4, wherein the barrier layer is selected from the group consisting of tantalum (Ta), tantalum (TaN), titanium (Ti), titanium nitride (TiN), or combinations thereof. The method of claim 4, wherein the filling of the second conductive layer further comprises forming a seed layer on the surface of the barrier layer. The method of claim 1, wherein the first planarization process comprises a chemical mechanical polishing process. The method of claim 1, wherein the performing the first planarization process further comprises performing a second planarization process to remove the first conductive layer to form a contact plug connection in the contact hole. The semiconductor component. The method of claim 8, wherein the second planarization process comprises a chemical mechanical polishing process. The method of claim 8, wherein the first conductive layer and the contact plug comprise tungsten. The method of claim 1, wherein the second conductive layer comprises copper. The method of claim 1, wherein the semiconductor component comprises a complementary MOS transistor.