TWI455138B - Nonvolatile semiconductor memory device - Google Patents

Description

Non-volatile semiconductor memory device

The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having a dual gate sharing a back gate.

With the advancement of the times, a large number of electrical or electronic products have become an indispensable auxiliary tool for life. The basic architecture of these products requires a microprocessor to perform computing functions, and a microprocessor is usually used with multiple memories. These memories are responsible for storing the code required for microprocessor operations or for storing user data. The programs required by the microprocessor and the data that needs to be permanently saved must be stored in Non Volatile Memory (NVM) or Read Only Memory. In this type of memory, the data can be saved after the power interruption. For example, the flash memory used for data storage is exemplified by a reverse NAND structure, which is small in size and shock-resistant; and has low power saving and fast access speed. It has become the most watched memory component in recent years and is widely used in electronics, computers, and communication products.

As shown in FIG. 1, a conventional flash memory device includes a control gate 12 and a source/drain semiconductor layer 14 configured with a plurality of flash memory cells 10, and a charge storage layer is deposited therebetween. 16. When reading, it is often limited by a low read current. In addition to applying a read bias to the control gate 12 of the cell to be read, in order to reduce the parasitic resistance, a relatively large read pass voltage must be applied. (Vread-pass) in the same column of the control gate 12 of the flash memory cell 10; as a result, it is easy to cause serious read disturb. In response to this problem, an independent double gate element structure has been proposed for improvement. As shown in FIG. 1, an independent back gate 18 corresponding to each control gate 12 is formed on the other side of the semiconductor layer 14, so that the control gate 12 is The back gate 18 has a one-to-one configuration. In operation, in addition to applying a read bias voltage to the control gate 12 of the cell to be read, a read pass voltage can be applied to the corresponding back gate. 18 to avoid reading interference. However, the fabrication steps of this structure are relatively complicated, including the problem of mutual alignment when there are lithography between the two independent gates, which causes difficulty in the process, which is quite difficult to achieve in actual mass production, and the price is quite expensive.

In view of the above, the present invention has been directed to the absence of the prior art described above, and proposes a non-volatile semiconductor memory device to effectively overcome the above problems.

The main object of the present invention is to provide a non-volatile semiconductor memory device which can effectively improve the short channel effect, facilitate the miniaturization of components, and effectively eliminate the problem of read-pass disturb. .

A secondary object of the present invention is to provide a non-volatile semiconductor memory device that can increase the storage capacity by using a double-gate memory element in a stacked manner, which is highly competitive in the industry in response to market demands.

Another object of the present invention is to provide a non-volatile semiconductor memory device which can effectively increase the efficiency of charge tunneling into the charge access layer by applying write or erase conduction voltage to the common gate, thereby improving non-volatile Write/removal efficiency of sexual memory.

Still another object of the present invention is to provide a non-volatile semiconductor memory device fabricated using a low-temperature polysilicon film (poly-Si TFT) process, which can be effectively applied to monolithic 3-D integration. A large increase in component density of non-volatile memory.

It is still another object of the present invention to provide a non-volatile semiconductor memory device that uses a separate dual gate that shares a back gate to solve the problem of poor alignment of prior independent dual gate devices.

To achieve the above object, the present invention provides a non-volatile semiconductor memory device suitable for fabricating a NAND 矽-矽 矽-矽 矽-矽 矽-矽 (Silicon-Oxide) having an independent double gate. -Nitride-Oxide Silicon,SONOS) Memory Element or Structure of Metal Oxide Nitride Oxide Silicon (MONOS) Memory Element, Non-volatile Semiconductor Memory Device The first semiconductor channel layer includes a first surface and a second surface, and a first interface layer having a stored charge is deposited on the first surface; and the plurality of first gates are spaced apart from the first interface a second interface layer having no charge access is disposed on the second surface; a second gate is located on the second interface layer as a common gate of the first gates, so no need to consider making The second gate is aligned with each of the first gates and can be used as a separate double gate; wherein the components are disposed on a substrate having an insulating layer.

The present invention provides another non-volatile semiconductor memory device suitable for fabricating a three-dimensional structure of a non-volatile semiconductor memory device, comprising a tubular first semiconductor channel layer comprising a first outer surface and a second inner side a surface, a first interface layer having a charge storage capability is formed on the first surface, and a second interface layer is formed on the second surface to form a hollow body; and the plurality of first gate lines are successively spaced Provided on the first interface layer such that the first gates are located outside the hollow body; a second gate is located on the second interface layer, such that the second gate is located inside the hollow body, and as such A common gate of a gate, in this way, a three-dimensional structure of the non-volatile semiconductor memory device can be fabricated.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

In recent years, the role of the development and application of non-volatile memory semiconductor memory components has become increasingly important due to non-volatility, high integration, fast write/read/erase and The advantages of low power consumption, etc., with the popularization of portable products such as notebook computers, digital cameras, mobile phones, flash drives, digital electronic memory cards or solid state drives, have gradually become the mainstream of market applications, but currently non- Volatile memory still has some insurmountable difficulties in the process. Therefore, the present invention provides a novel non-volatile semiconductor memory device, which can overcome the prior art process defects in addition to the market demand.

As shown in FIG. 2, a schematic view of a first embodiment of the present invention, the non-volatile semiconductor memory device includes a first semiconductor channel layer 20, such as a single crystal germanium layer or a polysilicon layer, including a first one of the first surfaces 22 And a second surface 24. A first interface layer 26 is disposed on the first surface 22, and the first interface layer 26 is sequentially stacked by using a hafnium oxide 28, a tantalum nitride 30, and an Oxide-Nitride-Oxide (ONO) layer. The charge storage dielectric layer, since the tantalum nitride has a deeper trap level, so that the tunneling oxide layer has a possibility of miniaturization, thereby facilitating the miniaturization of the element and effectively improving the short channel effect, so the first use of the present invention The interface layer 26 is exemplified by an ONO charge storage dielectric layer. Of course, a charge storage dielectric layer formed by sequentially stacking yttrium oxide, polycrystalline germanium, or osmium oxide (Oxide-Poly Silcon-Oxide) may also be used. A plurality of first gates 34 are spaced apart from each other on the first interface layer 26. A second interface layer 36 is disposed on the second surface 24 of the first semiconductor channel layer 20, such as a ruthenium oxide layer, and a second gate 38 is disposed on the second interface layer 36 as the plurality of first gates 34. Shared gate.

Each of the first gates 34 can independently apply a bias voltage, and the turn-on voltage of the second gates 38 provides a common auxiliary voltage of the first gates 34. For example, during writing or erasing, a negative bias voltage is applied to the first gate 34 for selective writing or erasing, and at this time, the other first gates 34 are kept in a floating or low voltage state, and then one is applied. A suitable turn-on voltage is applied to the second gate 38 to assist in accelerating charge in the semiconductor channel layer 20 into the tantalum nitride 30 under a quantum tunneling mechanism, and the tantalum oxide 28, 32 can coat the charge on the tantalum nitride 30. In this way, the two-bit operation can be completed. In other words, the present invention only needs to apply a write or erase conduction voltage to the second gate 38 (common gate), and a charge storage dielectric layer using an ONO having a lower write/erase voltage characteristic. Effectively increase the efficiency of charge tunneling into the charge access layer, thereby improving the write or erase removal efficiency of the non-volatile memory. During reading, a positive bias may be applied to the first gate 34 that is selectively read. At this time, the other first gates 34 are maintained in a floating or low voltage state, and then a turn-on voltage is applied to the second gate 38. The data is read by judging the level of the turn-on voltage. Therefore, the read disturb problem of a single gate memory element can be improved.

Among them, it is particularly important to note that the independent dual gate (control gate and back gate) memory components fabricated by the prior art have problems of mutual alignment in the presence of lithography, which causes difficulty in the process and is actually mass-produced. The time is quite difficult to achieve, and the price is quite expensive; and the present invention connects the prior art using a plurality of back gates, that is, a whole layer of the second gate 38 is used as a common to the plurality of first gates 34. The gate can solve the difficulty of the mutual alignment of the independent double gates. In addition, the non-volatile semiconductor memory device can be formed by sequentially depositing the second gate 38, the second interface layer 36, the first semiconductor channel layer 20, the first interface layer 26, and the plurality of first gates from bottom to top. Extremely 34. In the above embodiments, the doping step performed on the semiconductor channel layer is not mentioned, but if necessary, the semiconductor channel layer may be doped to achieve an optimum dopant concentration; or more executable A step of self-aligning ion implantation is performed to implant the dopant into a specific region of the first semiconductor channel layer 20, such as a source and a drain, in an ionic state to obtain an accurate Electronic characteristics. Since the method of fabricating the non-volatile semiconductor memory device is much like a star, the present invention is not limited to the fabrication method, and only the preferred fabrication process of the structure of the present invention in the process is exemplified herein.

In addition to having high density and high data retention capability, the present invention can also be configured to increase the storage data capacity. It is assumed that the structure of the first embodiment can produce a memory of 64 G capacity, as long as at least one layer of the same structure and capacity is stacked. With memory components, you can create 128G-capacity memory chips and even larger-capacity memory chips. For example, please refer to FIG. 2 and FIG. 3 at the same time. FIG. 3 is a schematic view of a second embodiment of the present invention, as long as at least one third dielectric layer 40 is disposed on the first gates 34, for example. The ruthenium oxide layer is further subjected to chemical-mechanical polishing (CMP) to polish the height difference generated by the third dielectric layer 40 in the lithography process to achieve comprehensive planarization. Subsequently, at least one first stacked memory unit 42 is disposed on the third dielectric layer 40, wherein the first stacked memory unit 42 includes a third gate 44 and a fourth interface layer sequentially deposited from bottom to top (eg, a yttrium oxide layer 46, a second semiconductor channel layer 48, a fifth interface layer (such as a charge storage dielectric layer of the ONO) 50, and a plurality of fourth gates 52 disposed on the fifth interface layer 50, the third gate The pole 44 is connected to the third dielectric layer 40; wherein the third gate 44 serves as a common gate of the fourth gates 52. It should be noted that the structure of the first stacked memory unit 42 is the same as that of the first embodiment, so that the same memory structure can be stacked in the same manner as described above to obtain a large-capacity non-volatile semiconductor. The memory device, in turn, overcomes the difficulty of making large-capacity non-volatile memory components at present, and the progress of the present invention is highlighted.

In addition to the above-mentioned structure for increasing the storage capacity, please refer to FIG. 3 and FIG. 4 simultaneously. FIG. 4 is a schematic view of a third embodiment of the present invention. The non-volatile semiconductor memory device further includes a substrate 54 and A sixth dielectric layer 56 is disposed on the substrate 54 , and a plurality of first gates 34 and a first interface layer (eg, a charge storage dielectric layer of the ONO) are sequentially disposed on the sixth dielectric layer 56 . a semiconductor channel layer 20, a second interface layer 36 and a second gate 38; and a second dielectric layer (such as a hafnium oxide layer) 58 and a third semiconductor channel layer 60 are sequentially disposed on the second gate 38. An eighth dielectric layer (such as a charge storage dielectric layer of the ONO) 62, and a plurality of fifth gates 64 spaced apart from the eighth dielectric layer 62 to form a second memory stacking unit 66 on the substrate 54. . It should be noted that the second gate 38 is a common gate of the first gates 34 and the fifth gates 64. Compared with the second embodiment, a common gate can be omitted, and not only the stacking manner can be utilized. By making double the memory capacity, the advantages of the simplified process can be achieved. Furthermore, at least another second memory stacking unit can be stacked on the second memory stacking unit 66, and the number of stacks can be determined according to requirements.

In addition, the present invention can also produce a non-volatile semiconductor memory device having a three-dimensional structure. Please refer to FIG. 2 and FIG. 5 at the same time. FIG. 5 is a schematic view of a fourth embodiment of the present invention. The non-volatile semiconductor memory device includes a first interface layer (such as a charge storage dielectric layer of ONO) 26, a first semiconductor channel layer 20 and a second interface layer 36 formed in a hollow body 68, for example, from outside to inside. In the cylinder, a plurality of first gates are arranged in a series on the outer side of the first interface layer 26; the second gate 38 is located on the inner side of the hollow body 68 to form a three-dimensional structure of the non-volatile semiconductor. Memory device. Wherein, the second gate 38 is a common gate of the first gates 34, thereby improving the process complexity of the prior art fabrication of the independent double gate components, and improving the feasibility of mass production of the three-dimensional structure. Application potential.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, any changes or modifications of the features and spirits of the present invention should be included in the scope of the present invention.

10. . . Flash memory unit

12. . . Control gate

14. . . Semiconductor layer

16. . . Charge storage layer

18. . . Back gate

20. . . First semiconductor channel layer

twenty two. . . First surface

twenty four. . . Second surface

26. . . First interface layer

28. . . Yttrium oxide

30. . . Tantalum nitride

32. . . Yttrium oxide

34. . . First gate

36. . . Second interface layer

38‧‧‧second gate

40‧‧‧ Third dielectric layer

42‧‧‧First stacked memory unit

44‧‧‧third gate

46‧‧‧Fourth interface layer

48‧‧‧Second semiconductor channel layer

50‧‧‧ fifth interface layer

52‧‧‧fourth gate

54‧‧‧Substrate

56‧‧‧ sixth dielectric layer

58‧‧‧ seventh dielectric layer

60‧‧‧ third semiconductor channel layer

62‧‧‧ eighth dielectric layer

64‧‧‧ fifth gate

66‧‧‧Second memory stacking unit

68‧‧‧ hollow body

Figure 1 is a schematic diagram of a prior art flash memory device.

Figure 2 is a schematic view showing the structure of the first embodiment of the present invention.

Figure 3 is a schematic view showing the structure of a second embodiment of the present invention.

Figure 4 is a schematic view showing the structure of a third embodiment of the present invention.

Fig. 5 is a three-dimensional perspective view showing a fourth embodiment of the present invention.

20. . . First semiconductor channel layer

twenty two. . . First surface

twenty four. . . Second surface

26. . . First interface layer

28. . . Yttrium oxide

30. . . Tantalum nitride

32. . . Yttrium oxide

34. . . First gate

36. . . Second interface layer

38. . . Second gate

Claims (16)

A non-volatile semiconductor memory device includes: a first semiconductor channel layer including a first surface and a second surface; a first interface layer on the first surface; a plurality of first gates a second interface layer is disposed on the second surface; and a second gate is disposed on the second interface layer as the first gate Shared brake. The non-volatile semiconductor memory device of claim 1, wherein each of the first gates can independently apply a bias voltage, and the turn-on voltage of the second gate provides a common auxiliary voltage of the first gates. . The non-volatile semiconductor memory device of claim 1, wherein the first semiconductor channel layer is a single crystal germanium layer or a poly germanium layer. The non-volatile semiconductor memory device of claim 1, wherein the first interface layer is a charge storage dielectric layer formed by sequentially stacking germanium oxide, germanium nitride, and germanium oxide. The non-volatile semiconductor memory device of claim 1, wherein the first interface layer is a charge storage dielectric layer formed by sequentially stacking germanium oxide, polycrystalline germanium, and germanium oxide. The non-volatile semiconductor memory device of claim 1, wherein the second interface layer is a hafnium oxide layer. The non-volatile semiconductor memory device of claim 1, wherein the first gates further comprise at least one third dielectric layer on which at least one first memory stacking unit is disposed. The non-volatile semiconductor memory device of claim 7, wherein the first memory stacking unit comprises a third gate, a fourth interface layer, and a second semiconductor pass sequentially deposited from bottom to top. a track layer, a fifth interface layer having a charge storage capability, and a plurality of fourth gates connected to the third dielectric layer. The non-volatile semiconductor memory device of claim 1, further comprising a substrate and a sixth dielectric layer on the substrate, the first gate being located on the sixth dielectric layer, the first gate Forming a seventh dielectric layer, a third semiconductor channel layer, an eighth dielectric layer, and a plurality of fifth gates spaced apart from the eighth dielectric layer to form a The second memory stacking unit. The non-volatile semiconductor memory device of claim 9, wherein at least the other of the second memory stacking units is disposed on the second memory stacking unit. A non-volatile semiconductor memory device comprising: a tubular first semiconductor channel layer comprising a first outer surface and a second inner surface; a first interface layer on the first surface; a first gate is disposed on the first interface layer, a second interface layer is disposed on the second surface; and a second gate is disposed on the second interface layer as the first gate A common gate of a gate. The non-volatile semiconductor memory device of claim 11, wherein each of the first gates can independently apply a bias voltage, and the turn-on voltage of the second gate provides a common auxiliary voltage of the first gates . The non-volatile semiconductor memory device of claim 11, wherein the first semiconductor channel layer is a single crystal germanium layer or a poly germanium layer. The non-volatile semiconductor memory device of claim 11, wherein the first interface layer is a charge storage dielectric layer formed by sequentially stacking hafnium oxide, hafnium nitride, and hafnium oxide. The non-volatile semiconductor memory device of claim 11, wherein the first interface layer is a charge storage dielectric layer formed by sequentially stacking germanium oxide, polysilicon germanium, and germanium oxide. The non-volatile semiconductor memory device of claim 11, wherein the second interface layer is a hafnium oxide layer.