TWI427802B - Printable semiconductor structures and related methods of making and assembling - Google Patents

Description

Printable semiconductor structure and related methods of manufacture and assembly

This invention relates to a printable semiconductor structure and related methods of fabrication and assembly.

Since the first demonstration of printed all-polymeric crystals in 1994, there has been great interest in a potential new electronic system that includes flexible integrated electronic devices on plastic substrates. [Gamier, F., Hajlaoui, R., Yassar, A. and Srivastava, P., Science, Vol. 265, pgs 1684-1686] Recently, a great deal of capabilities have been developed for use in flexible plastic electronic devices. A new material that can be treated by a solution of conductors, dielectrics, and semiconductor components. However, advances in the field of flexible electronic devices are not only driven by the development of new solution-processable materials, but also by new device component geometries, effective devices and device component processing methods, and high resolution for plastic substrates. Degree patterning technology to promote. It is expected that these materials, device configurations and manufacturing methods will play an important role in the rapid emergence of new flexible integrated electronic devices, systems and circuits.

The focus on the field of flexible electronics is due to the fact that this technology offers several important advantages. First, the mechanical robustness of the plastic substrate material makes the electronic device less susceptible to damage and/or less susceptible to degradation of electronic performance due to mechanical stress. Second, the inherent flexibility of the substrate materials allows them to be integrated into a wide variety of shapes, providing a large number of usable device configurations that are not possible with fragile traditional electronic devices based on germanium. For example, bendable flexible electronic devices are expected to be able to make new devices, such as electronic paper, headsets, and large-area high-resolution displays, which are not easily achieved using known sputum-based techniques. . Finally, the combination of the solution-treated component material and the plastic substrate allows one to manufacture using continuous, high-speed printing techniques that produce electronic devices at large substrate areas at low cost.

However, there are many major challenges in designing and manufacturing flexible electronic devices with good electronic performance. First, the conventional methods for fabricating conventional electronic devices based on germanium are incompatible with most plastic materials. For example, conventional high quality inorganic semiconductor components such as single crystal germanium or germanium semiconductors are typically processed by growing the film at temperatures significantly above the melting or decomposition temperature of most plastic substrates (>1000 degrees Celsius). In addition, most inorganic semiconductors are inherently insoluble in convenient solvents that are capable of achieving solution-based processing and delivery. Secondly, although many amorphous germanium, organic or hybrid organic-inorganic semiconductors are compatiblely incorporated into plastic substrates and can be processed at relatively low temperatures, such materials do not have the ability to provide integrated bodies with good electronic properties. Electronic properties of electronic devices. For example, thin film transistors having semiconductor components made of such materials exhibit field effect mobility that is about three orders of magnitude smaller than polysilicon based complementary devices. Because of these limitations, flexible electronic devices are currently limited to certain applications that do not require high performance, such as in switching elements for active matrix flat panel displays with non-luminescent pixels or in light emitting diodes.

Recently, advances in expanding the electronic performance capabilities of integrated electronic devices on plastic substrates have made them suitable for use in a wider range of electronic applications. For example, several new thin film transistor (TFT) designs have emerged that are compatible with the processing of plastic substrate materials and exhibit a thinner film than amorphous, organic or hybrid organic-inorganic semiconductor components. Higher device performance characteristics of the transistor. One type of higher performance flexible electronic device is based on a polycrystalline germanium thin film semiconductor device fabricated by pulsed laser annealing of an amorphous germanium film. While such flexible electronic devices provide enhanced device electronic performance characteristics, the use of pulsed laser annealing limits the ease and flexibility of manufacturing such devices, resulting in significant cost increases. Another new class of promising, higher-performance flexible electronic devices uses solution-processable nanoscale materials (such as nanowires, nanoribbons, nanoparticles, and many other devices in many giant electronics and microelectronic devices). Carbon nanotubes) as a device for active functional components.

The use of discrete single crystal nanowires or nanostrips has been assessed as a possible method for providing printable electronic devices on plastic substrates that exhibit enhanced device performance characteristics. Duan et al. describe a thin-film transistor design using a plurality of selectively oriented single crystal germanium wires or CdS nanowire strips as semiconductor channels [Duan, X., Niu, C, Sahl, V., Chen , J., Parce, J., Empedocles, S. and Goldman, J., Nature, Vol. 425, pp. 274-278]. The above authors report a manufacturing process in which the manufacturing process is compatible with solution processing on a plastic substrate in which a single crystal germanium wire or CdS nath having a thickness of less than or equal to 150 nm is made. The rice strips are dispersed in the solution and combined onto the surface of the substrate using a flow-directed alignment method to form semiconductor elements in the thin film transistor. The optical micrographs provided by the above authors indicate that the disclosed manufacturing process can produce a single layer of nanowires or nanoribbons in a substantially parallel orientation with an interval of about 500. Nano to about 1,000 nm. Although according to the authors above, a single nanowire or nanobelt has a relatively high intrinsic field-effect mobility ( 119 cm ² V ^{- 1} s ^{- 1} ), however, it has recently been determined that the field-effect mobility of the overall device is "about two orders of magnitude smaller" than the intrinsic field-effect mobility value reported by Duan et al. [Mitzi, DB, Kosbar, LL,, Murray, CE, Copel, M. Afzali, A., Nature, Vol. 428, pp. 299-303]. The field effect mobility of such devices is several orders of magnitude lower than that of conventional single crystal inorganic thin film transistors, and may be due to alignment, dense packaging, and electrical contact using methods and device configurations disclosed by Duan et al. Caused by the practical challenges faced when separating nanowires or nanoribbons.

As a possible way to provide a printable electronic device capable of exhibiting higher device performance characteristics on a plastic substrate, it has been explored to use a nanocrystal solution as a precursor of a polycrystalline inorganic semiconductor film. Ridley et al. disclose a solution processing process in which a cadmium selenide crystal of a solution having a size of about 2 nm is treated at a temperature compatible with the plastic to provide a semiconductor device of a field effect transistor. [Ridley, BA, Nivi, B. and Jacobson, JM, Science, Vol. 286, pp. 746-749 (1999)] The above authors report a method in which a low temperature is carried out in a cadmium selenide crystal solution. The grain grows to provide a single crystal region comprising hundreds of nanocrystals. Although according to Ridley et al., electrical properties are improved relative to comparable devices with organic semiconductor components, the device mobility obtained by such techniques ( 1 cm ² V ^{- 1} s ^{- 1} ) is several orders of magnitude lower than the field effect mobility of conventional single crystal inorganic thin film transistors. The limitations of the field effect mobility obtained by the device construction and fabrication methods disclosed by Ridley et al. may be due to electrical contact formed between individual nano ions. In particular, the use of organic end groups to stabilize the nanocrystal solution and prevent agglomeration may hinder the formation of good electrical contact between adjacent nanoparticles to provide high device field mobility.

Although Duan et al. and Ridley et al. provide a method of fabricating a thin film transistor on a plastic substrate, the device configuration employs a transistor comprising mechanically rigid device components (eg, electrodes, semiconductors, and/or dielectrics). . The use of a plastic substrate with good mechanical properties provides an electronic device that can operate in the direction of deflection or distortion. However, such motion is expected to produce mechanical strain on each rigid transistor assembly. Such mechanical strain can damage individual components (eg, cracks) and can also degrade or interrupt electrical contact between components of the various devices.

U.S. Patent Nos. 11/145,574 and U.S. Patent No. 11/145,542, both issued on June 2, 2005, disclose the use of a versatile, low-cost, large-area printing technique using printable semiconductor components. High-yield manufacturing platform for electronic devices, optoelectronic devices, and other functional electronic assemblies. The disclosed methods and configurations can use dry transfer contact printing techniques and/or solution printing techniques to transfer, combine, and/or integrate micron-sized and/or nano-sized semiconductor structures to achieve good results over large substrate areas. Arrangement accuracy, alignment and pattern fidelity. The disclosed method provides important processing advantages that can be independently implemented by relatively low temperatures (< about 400 degrees Celsius) that are compatible with a variety of suitable substrate materials, including flexible plastic substrates, High quality semiconductor materials made using conventional high temperature processing methods are integrated onto the substrate. Flexible thin film transistors made of printable semiconductor materials exhibit good electronic performance characteristics in both flexed and non-flexed configurations, such as device field mobility greater than 300 cm ² V ^{- 1} s ^{- 1} and on/ The off ratio is greater than 10 ³ .

It will be appreciated from the above description that a method of making high quality printable semiconductor components from low cost, bulk starting materials will enhance the commercial use of printing techniques for producing large area flexible electronic and optoelectronic devices and arrays of devices. The attraction. In addition, a printable semiconductor construction and a printing-based combination method that enable a high degree of control over the physical dimensions, spatial orientation, and alignment of semiconductor components printed onto the substrate will also enhance the applicability of such methods to the fabrication of a wide variety of functional devices. .

The present invention provides a high yield method for fabricating, transferring and combining high quality printable semiconductor components having selected physical dimensions, shapes, compositions and spatial orientation. The compositions and methods of the present invention enable the transfer and integration of micro-sized and/or nano-sized semiconductor structures onto a substrate with high precision alignment, including large area substrates and/or flexible substrates. In addition, the present invention provides methods for fabricating printable semiconductor components from low cost bulk materials such as bulk germanium wafers, and smart material processing strategies that can be used to fabricate a wide variety of functions. A versatile and commercially attractive print-based manufacturing platform for semiconductor devices. The semiconductor fabrication, transfer and integration platforms of the present invention have a number of advantages including a very high degree of control over the geometry, relative spatial orientation and organization, doping levels and material purity of the printable semiconductor structure.

The methods and compositions of the present invention are capable of forming a complex array of integrated electronic or optoelectronic devices or arrays of devices, including large area, flexible, high performance giant electronic devices that exhibit and use conventional high temperature processing methods. A device based on a single crystal semiconductor has comparable performance characteristics. Compositions of the present invention and related methods for combining, positioning, organizing, transferring, patterning, and/or integrating printable semiconductor components onto or into a substrate can be used to fabricate virtually any one or more semiconductor components The structure. However, such methods are particularly useful for fabricating complex integrated electronic or optoelectronic devices or arrays of devices, such as diodes, light-emitting diodes, solar cells, and transistors (eg, thin film transistors (TFTs), metal-semiconductor fields Array of effect transistor (MESFET) FETs and bipolar transistors). The compositions and related methods of the present invention are also suitable for use in the fabrication of system-level integrated electronic circuits, such as NOA and NAND logic gates and complementary logic circuits, in which printed semiconductor components are printed in a clear spatial orientation onto a substrate and interconnected. And form the required circuit design.

In one aspect, the present invention provides a method of providing a printable semiconductor component having a selected physical size, shape, and spatial orientation with high precision using a reprocessable processed bulk wafer starting material. In one embodiment of this aspect of the invention, a tantalum wafer having a (111) orientation and having an outer surface is provided. In a commercially attractive embodiment, the wafer is a low cost, bulk (111) wafer. A plurality of recess features are formed on the outer surface of the (111) germanium wafer, wherein each recess feature includes a bottom surface and a plurality of side surfaces of the exposed germanium wafer. At least a portion of the side surfaces of the recessed features are masked. In the context of the present description, the phrase "mask" means providing a masking material, such as a resist mask material, that is capable of preventing or inhibiting the etching of the masked surface or that reduces the etch rate of the masked surface. Etching the regions between the recess features such that the etching is performed along the <110> direction of the (111) germanium wafer to form one or more germanium structures including a partial or complete undercut. Printable semiconductor components. In a suitable embodiment, the undercut is applied to the region between adjacently positioned recess features by etching along the <110> direction of the germanium wafer to produce a printable semiconductor component. The position, shape and spatial orientation of the recessed features are selected to form alignment retention elements, such as bridging elements for connecting the printable semiconductor components to the wafer, as desired.

In one embodiment, some, but not all, of the side surfaces of the recessed features are masked to create a masked area and an unmasked area of the side surfaces. The unmasked regions of the side surfaces are etched by, for example, an anisotropic etch process such that the regions between the recess features in the (111) germanium wafer are undercut. In this embodiment of the invention, etching is performed between the recessed features along the <110> direction of the germanium wafer to form a printable semiconductor component comprising a partially or fully undercut tantalum structure.

In another embodiment, the side surfaces of the recessed features are completely masked and the regions between the recessed features are etched by, for example, etching a material underlying the masked regions to cause etching along the The <110> direction of the wafer is performed. This causes the region between the recessed features in the (111) germanium wafer to be undercut. Such a process results in a printable semiconductor component comprising a partially or fully undercut structure. In some embodiments, the material underlying the bottom surface of the recess features is removed by, for example, an anisotropic etch process. The bottom surface of the recessed features is partially masked as needed to leave an etchant inlet on the bottom surface of the recessed feature. The method of making a full mask of the side surfaces of the recessed features enables more precise definition and selection of the thickness of the printable element than partial masking of some of the opposite side surfaces.

Optionally, the method of the present invention may further comprise the step of modifying the geometry, physical dimensions and morphology of the recessed features prior to fabricating the printable semiconductor component. In this context, "improvement" refers to the material removal treatment of the surfaces of the recessed features, such as the side and bottom surfaces of the recessed features. The improvement includes processing to smoothen the surface of the recessed features and/or to treat the recessed features to have a more uniform physical size and surface morphology, thereby providing a smoother surface and features and/or more uniformity of the printable semiconductor component Physical size and shape. In one embodiment, the geometry, physical dimensions, and/or morphology are improved by an anisotropic etch technique (eg, etching using a hot KOH solution). The method of the present invention, including the processing steps involved in improving the geometry, physical dimensions and morphology of the depressed features, is suitable for use in the fabrication of microelectromechanical systems (MEMS) and nanoelectromechanical systems (NEMS).

In such an aspect of the method of the present invention, patterning the outer surface of the (111) wafer with a plurality of recessed features having selected physical dimensions, locations, and relative spatial orientations is suitable for simultaneous fabrication with high precision large (e.g., about 1 × 10 ³ to about 1.0 × 10 ^{1 0} th) printable semiconductor element to a selected position and spatial orientation of the array constitutes provided, which facilitate the integration into the final composition and device system. The method of the present invention is capable of producing an array of printable semiconductor elements corresponding to a majority (e.g., from about 75% to about 95%) of the outer surface of the tantalum wafer.

The invention includes wherein etching in the <110> direction of the (111) germanium wafer is continued between adjacent recessed features such that the region between the recessed features in the (111) germanium wafer is completely A method of undercutting to form a printable semiconductor component. Alternatively, the present invention includes a method in which etching in the <110> direction of the germanium wafer is not completed, whereby a region between the recessed features in the (111) germanium wafer is subjected to partial undercutting. This results in one (or more) printable semiconductor components that are partially undercut. In some methods in which the printable semiconductor component is subjected to a complete undercut by the etch process step, the spatial orientation and physical dimensions of the recessed features on the outer surface of the wafer are selected to produce a printable The semiconductor component remains connected to, and optionally connected to, the germanium wafer at one or more ends of the printable semiconductor component. In some embodiments, the printable semiconductor component is directly connected to the germanium wafer, while in other embodiments, the printable semiconductor component is coupled to the twin via one or more alignment retention components (eg, bridging components) circle.

The use of a (111) oriented germanium wafer in conjunction with the etching system of the present invention provides a suitable for at least partially or completely undercutting a printable semiconductor component and optionally an undercut alignment holding component (e.g., a bridging component). The organic etch stop layer. In some embodiments, for example, an anisotropic etch system that preferentially etches along the <110> direction of the germanium wafer is selected. In such embodiments, the etch rate of etching along the <110> direction of the germanium wafer is faster than the etch rate of etching along the <111> direction of the germanium wafer, and preferably, in some applications, along The <110> direction of the germanium wafer is etched at a rate that is at least 100 times faster than the <111> direction of the germanium wafer, and in some embodiments, is etched along the <110> direction of the germanium wafer. The rate is at least 600 times faster than etching in the <111> direction of the germanium wafer. Under certain processing conditions, an anisotropic etch system is used to substantially etch along the <111> direction of the germanium wafer. In the context of this description, "substantially not etching in the <111> direction" means that the degree of etching is less than about a few percent of the usual manufacturing process of the printable semiconductor device. An etching system suitable for the undercutting process produces a printable semiconductor component having a smooth, undercut surface, such as an undercut surface having a surface roughness of less than or equal to 0.5 nanometers. Anisotropic etching systems suitable for use in the method of the present invention include, but are not limited to, wet chemical etching using a base solution such as, for example, at room temperature or at a temperature above 298 K: KOH, an alkali metal hydroxide solution, EDP (ethylenediamine pyrocatechol), TMAH (tetramethylammonium hydroxide), amine gallate (gallium acid, ethanolamine, aqueous surfactant solution), and hydrazine.

Suitable methods for masking the side surfaces of the recessed features include oblique beam electron beam deposition of a masking material (e.g., a combination of metals or metals), chemical vapor deposition of the masking material, thermal oxidation, and solution deposition. An exemplary method includes performing a Ti/Au bimetallic oblique electron beam deposition to achieve localized coverage of the side surfaces of the recessed features. In this embodiment, the "shadow" cast during the bevel evaporation process at least partially defines the thickness of the printable semiconductor component. The method of the present invention includes the step of completely masking the side surface of the recessed feature, and the other option is to include a step of partially masking only the side surface of the recessed feature, such as a selected portion of the opposite side surface Process steps for masking, zone, area or depth.

In one embodiment of this aspect of the invention, a pattern of recessed features having a selected physical size, orientation and location is provided on the outer surface. In this embodiment, the physical dimensions (i.e., length, width, and depth), shape, position, and relative spatial orientation of the recessed features on the outer surface are selected to at least partially define the physical dimensions of the printable semiconductor component and optionally the bridging component. , shape, position and spatial orientation. The relative position (e.g., pitch), shape, and spatial orientation of adjacent features of the recess are selected to define the shape, width, or length of the printable semiconductor component. For example, the distance between adjacent recessed features defines the width or length of the printable semiconductor component, and the depth of the recessed features can be selected to at least partially determine the thickness of the printable semiconductor component. In some embodiments, it is preferred that the recessed features have one or more physical dimensions that are substantially uniform (ie, within about 5%) to produce one or more uniform physical dimensions (eg, uniform thickness, width, or length). Printable semiconductor components. The recess features can be formed by any method known in the art including, but not limited to, lithographic processing such as near-field phase shift lithography, soft lithography, lift-off, dry chemical etching, plasma etching. , wet chemical etching, micromachining, electron beam writing, and reactive ion etching. In a suitable embodiment capable of providing a recessed feature pattern having a selected physical size and relative spatial orientation, the step of creating one or more recessed features on the outer surface of the tantalum wafer includes the following steps: (i) by applying one Masking one or more regions of the outer surface to create a masked region and an unmasked region in the outer surface; and (ii) etching (eg, anisotropic dry etching or orientation) Isotropic dry etching technique) at least a portion of an unmasked area of the outer surface of the wafer.

In one embodiment of this aspect of the invention, the recessed feature includes a plurality of channels in the outer surface of the wafer having a selected physical size, location, and relative spatial orientation. For example, the recess features comprising the first and second channels can be patterned on the germanium wafer such that they are physically separated from one another. The step of etching between the recess features in the embodiment proceeds from the first channel to the second channel along the <110> direction of the germanium wafer, thereby undercutting the germanium wafer between adjacent channels. At least a portion of the region is such that a printable semiconductor component and an optional bridging component are formed between the first trench and the second trench from the (111) germanium wafer. The process produces one (or more) printable semiconductor components comprising a partially or fully undercut germanium structure between the first channel and the second channel. In a suitable embodiment for fabricating a printable semiconductor device array, a pattern comprising a plurality of channels having well defined locations and dimensions is created on the outer surface of the germanium wafer to enable simultaneous fabrication of a large number of individual processing protocols. Printable semiconductor components.

In one embodiment, the first and second channels on the outer surface of the wafer are oriented longitudinally in a substantially parallel configuration. In this embodiment, the step of etching between the recess features produces a partially or fully undercut printable semiconductor component between the first trench and the second trench. Preferably, in some embodiments, the locations and physical dimensions of the first and second channels are selected to maintain the printable semiconductor strips integrally connected to the germanium wafer until further processing is performed - for example, until To a processing step in contact with a transfer device, including but not limited to a flexible stamp. In one embodiment, for example, the first channel terminates at a first end and the second channel terminates at a second end, and the printable semiconductor strip remains directly or via, for example An alignment retention element, such as a bridging element, is coupled to a region of the germanium wafer between the first end of the first trench and the second end of the trench. Additionally, the first channel and the second channel may terminate at the third end and the fourth end, respectively, and the printable semiconductor strip may also be aligned to the holding element directly or via, for example, a bridging element, etc., as desired. Connected to a region of the germanium wafer between the third end and the fourth end.

The method of this aspect of the invention may further comprise a plurality of optional processing steps including, but not limited to, material deposition and/or patterning to produce a conductive structure such as an electrical contact, an insulating structure, and the like on the printable semiconductor component. / or other semiconductor structure; annealing step; wafer cleaning; surface treatment, such as surface polishing, to reduce the roughness of the outer surface; material doping treatment; transfer, patterning, combination and use, for example, using elastic or solution printing techniques / or integration of printable semiconductor components; refurbishing the surface of the wafer; functionalizing the surface of the printable semiconductor component by, for example, making hydrophilic or hydrophobic groups; removing the material by, for example, etching; on the printable semiconductor component Growing and/or removing the thermal oxide layer, and any combination of such optional processing steps.

The method of the present invention for fabricating a printable semiconductor component can further comprise the step of releasing the (these) printable semiconductor component from the germanium wafer. In the context of this description, "release" refers to a process in which a printable semiconductor component is separated from a germanium wafer. The release treatment in the present invention may involve breaking an alignment holding element, such as a bridging element, that connects the printable semiconductor component to a mother substrate. The release of the printable semiconductor component from the wafer can be effected by contacting the printable semiconductor component with a transfer device, such as a flexible stamp. In some embodiments, the outer surface of the semiconductor component is brought into contact and, if desired, conformally contacted with a contact surface of a transfer device (e.g., a conformal elastic stamp) to bond the semiconductor component to the contact surface. Optionally, the method of this aspect of the invention further includes the step of sequentially transferring the (printable) semiconductor elements to a transfer device. Optionally, the method of this aspect of the invention further includes using a power controlled separation rate to achieve an aligned transfer of the printable semiconductor component to an elastic stamp.

One of the advantages of the method of the present invention for fabricating a printable semiconductor component is that it can be implemented more than once using a predetermined (111) wafer starting material (e.g., a one-by-one (111) wafer). The repetitive processing capability of the method of the present invention is advantageous because it makes it possible to repeat the process of the invention multiple times using a single starting wafer, thereby enabling fabrication from 1 square foot of bulk wafer starting material. Dozens or even hundreds of square feet of printable semiconductor components. In one embodiment, the method further includes the step of refurbishing the outer surface of the tantalum wafer after releasing and transferring the (s) printable semiconductor component. In the context of this description, the term "refining wafer" refers to the processing steps of producing a flat, as desired, smooth outer surface of the wafer after, for example, releasing and/or transferring one or more printable semiconductor components. . The refurbishment can be performed by any of the techniques known in the art including, but not limited to, polishing, etching, grinding, micromachining, chemical-mechanical polishing, and anisotropic wet etching. In a suitable embodiment, the following steps are repeated after refurbishing the outer surface: (i) producing a plurality of recessed features on the outer surface of the tantalum wafer, (ii) one of the side surfaces of the recessed features, and optionally The entire side surface is masked, and (iii) etching is performed between the side surfaces to create other printable semiconductor components. The inventive method comprising the release and refurbishing process steps can be repeated many times using a single ruthenium wafer starting material.

In another aspect, the present invention provides a printable semiconductor composition and structure that can be transferred in a highly precise alignment, alignedly combined, and/or aligned to a receiving substrate. In the context of the present description, the terms "aligned transfer", "alignedly combined", and "alignedly integrated" mean that the relative spatial orientation of the transferred elements is preferably within about 5 microns and in some applications. More preferably, the synergistic process is within about 0.1 microns. The alignment process of the present invention may also refer to the method of the present invention capable of transferring, combining and/or integrating a printable semiconductor component to a receiving substrate of a preselected 5 micron and, in some embodiments, preferably 500 nanometers. Ability within the region. The printable semiconductor composition and structure of the present invention can improve the accuracy, precision and reproducibility of the transfer printing combination and integration technology, thereby providing a robust for manufacturing high performance electronic and electro-optical devices. And a commercially viable manufacturing platform. A variety of transfer devices can be used to carry out the alignment process of the present invention including, but not limited to, a stamp transfer device such as an elastic and inelastic stamp.

In one embodiment of such aspects, the present invention provides a printable semiconductor structure comprising: a printable semiconductor component; and one or more connected to and optionally connected to the printable semiconductor structure and A bridging element of a mother wafer. The physical dimensions, composition, shape and geometry of the printable semiconductor component and the bridging component are selected to enable the printable semiconductor to contact a transfer device (eg, an elastic stamp) The bridging element is broken to separate the printable semiconductor component from the mother wafer in a controlled manner.

In one embodiment, the bridging elements, the printable semiconductor component, and the mother wafer are connected in a unitary manner to form a unitary structure. In the context of the present description, "integral structure" means a configuration in which a mother wafer, a bridging element, and a printable semiconductor element constitute a monolithic structure. In one embodiment, for example, a unitary structure includes a single continuous semiconductor structure in which one or more bridging elements are integrally connected to the mother wafer and the printable semiconductor component. However, the present invention also includes a printable semiconductor structure in which the bridging element, the printable semiconductor element, and the mother wafer do not constitute a unitary structure, but are interconnected via a bonding mechanism such as: covalent bonding , binders, and / or intermolecular forces (such as van der Waals force, hydrogen bonding, bipolar-bipolar interaction, London dispersion).

The printable semiconductor structure of this aspect of the invention can include a single or a plurality of bridging elements that are connected to and, if desired, integrally connected to the printable semiconductor component and the mother wafer. The bridging element of the present invention includes a structure for connecting the surface of the printable semiconductor component to the mother wafer. In one embodiment, one or more bridging elements connect the ends and/or the bottom of the printable semiconductor component to the mother wafer. In one embodiment, each bridging element connects one end of the length of a printable semiconductor strip to the mother wafer. In some embodiments, the printable semiconductor strip and the bridging element are at least partially undercut from the mother wafer. In an embodiment in which high precision alignment transfer can be achieved, the printable semiconductor component and the bridging component are completely undercut from the mother wafer. However, the present invention also includes a bridging element that is not an undercut structure for attaching a printable semiconductor component to a mother wafer. One example of such a non-undercut configuration is a bridging element that connects and/or anchors the bottom of the printable semiconductor component to a mother wafer.

The invention includes embodiments in which a bridging element connects at least two different ends or surfaces of a printable semiconductor component to a mother wafer. A printable semiconductor structure having a plurality of bridging elements is suitable for use in applications where improved high precision alignment transfer is required because it causes the semiconductor component to contact and transfer to the contact surface of a transfer device and/or a receiving substrate during contact Higher alignment, spatial orientation and positional stability.

The bridging element of this aspect of the invention is an alignment holding element for connecting and/or anchoring a printable semiconductor component to a mother substrate, such as a semiconductor wafer. The bridging elements are adapted to maintain a selected orientation and/or position of the printable semiconductor component during the transfer, assembly and/or integration process steps. The bridging elements are also suitable for maintaining the relative position and orientation of the semiconductor element array pattern during the transfer, assembly and/or integration process steps. In the method of the present invention, the bridging element maintains the position of the printable semiconductor component during contact, bonding, transfer and integration processes involving the contact surface of a transfer device (e.g., a conformal elastic stamp) Spatial orientation to achieve alignment transfer from a parent wafer to the transfer device.

The bridging element of this aspect of the invention is capable of being detached from the printable semiconductor component without significantly altering the position and orientation of the printable semiconductor component when contacting and/or moving the transfer device. Disengagement can be achieved by breaking and/or breaking the bridging element during contact and/or movement of the transfer device. The detachment caused by the rupture can be enhanced by a conformal transfer device such as an elastic stamp, and/or a power-controlled separation rate that facilitates transfer to the contact surface of the transfer device.

In one embodiment of this aspect of the invention, the spatial arrangement, geometry, composition, and physical dimensions of the bridging elements are selected to achieve high precision alignment transfer. In the context of this description, the term "high precision alignment transfer" refers to the transfer of a printable semiconductor component with a relative spatial orientation and relative position change of less than about 10%. High-precision alignment transfer also refers to the transfer of a printable semiconductor component from a mother substrate to a transfer device and/or a receiving substrate with good placement accuracy. High-precision alignment transfer also refers to the transfer of a printable semiconductor device pattern to a transfer device and/or a receiving substrate with good pattern fidelity.

The bridging elements of the present invention can include structures that are partially or completely undercut. The bridging elements suitable for use in the present invention may have a uniform width or a regularly variable width, e.g., the width is tapered to a narrow neck that facilitates release by rupture. In some embodiments, the bridging elements have an average width selected from the range of from about 100 nanometers to about 1000 microns, an average thickness selected from the range of from about 1 nanometer to about 1000 microns, and selected from about 100 nanometers to about 1000. The average length in the micrometer range. In some embodiments, the physical size and shape of the bridging element is defined relative to the physical dimensions of the printable semiconductor component that is connected to the mother wafer by the bridging element. It is possible, for example, to use an average width that is at least two times smaller than the average width of the printable semiconductor component and preferably 10 times smaller in some applications, and/or an average thickness that is less than the average thickness of the printable semiconductor component of 1.5. Double bridge the components to achieve alignment transfer. The bridging element can also be provided with sharp features to facilitate cracking and facilitate alignment transfer of the printable semiconductor component from the mother wafer to the transfer device and/or the receiving substrate.

In one embodiment of this aspect, the printable semiconductor component includes a printable semiconductor strip extending a length along a major longitudinal axis, the length terminating at a first end and a second end. A first bridging element connects the first end of the printable semiconductor strip to the mother wafer, and a second bridging element connects the second end of the semiconductor strip to the mother wafer. The printable semiconductor strip, the first bridging element, and the second bridging element are subjected to a completely undercut structure, as desired. In one embodiment, the first bridging element, the second bridging element, the printable semiconductor strip, and the mother wafer form a single semiconductor structure. In one embodiment, the average width of the first and second bridging elements is from about 1 to about 20 times less than the average width of the printable semiconductor strip. In one embodiment, the first and second bridging elements are each connected to less than 1% to about 100% of the cross-sectional area of the first end and the second end of the printable semiconductor strip, respectively. The invention includes embodiments in which the first and second bridging elements have a spatial configuration that is close to each other or away from each other.

In the present invention, the outer surface of the printable semiconductor component and/or the bridge component can be functionalized to enhance alignment transfer to a transfer device such as an elastic stamp. Functionalized solutions suitable for alignment transfer include the addition of hydrophilic and/or hydrophobic groups to the surface of the printable semiconductor component to enhance bonding to the contact surface of the transfer device. An alternative chemical strategy is to apply one or more contact surfaces (surfaces on and/or on the printable surface) to a metal, including but not limited to gold. The metals are treated in a self-assembled monolayer that can be chemically bridged to the printable element.

The printable semiconductor component of the present invention can be made from a wide variety of materials. Suitable for manufacturing printable semiconductor components, including semiconductor wafer sources, including: bulk semiconductor wafers, such as single crystal germanium wafers, polycrystalline germanium wafers, germanium wafers; ultrathin semiconductor wafers, such as ultra Thin silicon wafers; doped semiconductor wafers, such as P-type or N-type doped wafers, and wafers with selected dopant spatial distribution (insulator-on-insulator semiconductor wafers, such as on insulators) Overlay (eg, Si-SIO ₂ , SiGe); and the substrate is overlaid with a semiconductor wafer, such as a substrate overlying the wafer and an overlying insulator. Furthermore, the printable semiconductor component of the present invention can be fabricated from scratches or unused high quality or reprocessed semiconductor materials used in conventional semiconductor methods for processing semiconductor devices. In addition, the printable semiconductor component of the present invention can be fabricated from a variety of non-wafer sources, such as amorphous, polycrystalline, and self-deposited on a sacrificial layer or substrate (eg, SiN or SiO ₂ ) and subsequently annealed. Single crystal semiconductor materials (eg, polycrystalline germanium, amorphous germanium, polycrystalline GaAs, and amorphous GaAs) films, or fabricated from other bulk crystals, including but not limited to: graphite, MoSe ₂ and other transition metal chalcogenides, and Beryllium copper oxide.

An exemplary transfer device of the present invention includes a dry transfer stamp (e.g., an elastic transfer stamp or composite), a conformal transfer device (e.g., a conformal elastic stamp), and a multilayer transfer device (e.g., multiple layers) Elastic impression). The transfer device of the present invention is conformed as needed. A transfer device suitable for use in the present invention includes a transfer device comprising a plurality of polymer layers, as applied to the U.S. Patent and Trademark Office on April 27, 2005, and entitled "Composite Patterning for Soft Micro-Film The teachings of U.S. Patent Application Serial No. 11/115,954, the entire disclosure of which is incorporated herein by reference. An exemplary patterning device useful in the method of the present invention comprises a polymer layer having a low Young's Modulus, such as a poly(dimethyloxysiloxane) (PDMS) layer, preferably in some The application has a thickness selected from the range of from about 1 micron to about 100 microns. The use of a low modulus polymer layer is advantageous because it provides good printable semiconductor components that can be bonded to one or more printable semiconductor components, particularly curved, rough, flat, smooth, and/or profiled exposed surfaces. A transfer device that conforms to contact and is capable of forming good conformal contact with a substrate surface having a variety of surface configurations, such as curved, rough, flat, smooth, and/or shaped substrate surfaces.

The invention also includes a method for transferring a printable semiconductor component (including high precision alignment transfer) onto a transfer device (eg, an elastic stamp), and/or for combining printable semiconductor components and/or A method of integrating (including high precision alignment and/or integration) on a receiving substrate. One advantage of the printing method and construction of the present invention is that the printable semiconductor component pattern can be transferred and assembled to the surface of the substrate in a manner that maintains the selected spatial orientation of the semiconductor component used to define the pattern. This aspect of the invention is particularly advantageous in applications where a plurality of printable semiconductor components are fabricated in a well-defined position and relative spatial orientation that corresponds directly to a selected device configuration or device array configuration. The transfer printing method of the present invention is capable of transferring, positioning and combining printable semiconductor components and/or printable functional devices, including but not limited to: transistors, optical waveguides, microelectromechanical systems, nanomechanical systems, laser diodes Body, or a fully fabricated circuit.

In addition to semiconductor materials, the methods and configurations of the present invention are also applicable to agglomerated semi-metallic materials. For example, the methods, constructions, and structures of the present invention can be used with carbonaceous materials such as graphite and saturated graphite, as well as other layered materials such as mica.

In one embodiment, the present invention provides a method for transferring a printable semiconductor component to a transfer device, comprising the steps of: (i) providing a printable semiconductor structure comprising a printable semiconductor component; And at least one bridging element coupled to the printable semiconductor structure and to a mother wafer, wherein the printable semiconductor component and the bridging element are at least partially undercut from the mother wafer; (ii) The printable semiconductor component contacts a transfer device having a contact surface, wherein contact between the contact surface and the printable semiconductor component causes the printable semiconductor component to bond to the contact surface; and (iii) The transfer device is moved in such a manner that the bridging element is broken, whereby the printable semiconductor structure is transferred from the mother wafer to the transfer device.

In one embodiment, the present invention provides a method for combining a printable semiconductor component on a receiving surface of a substrate, comprising the steps of: (i) providing a printable semiconductor component; and at least one connecting to The printable semiconductor structure and a bridging element coupled to a mother wafer, wherein the printable semiconductor component and the bridging element are at least partially undercut from the mother wafer; (ii) the printable semiconductor component Contacting a transfer device having a contact surface, wherein contact between the contact surface and the printable semiconductor component causes the printable semiconductor component to bond to the contact surface; (iii) to cause the (the) Moving the transfer device in such a manner that the bridging element is broken, whereby the printable semiconductor structure is transferred from the mother wafer to the transfer device, thereby forming the contact surface with the printable semiconductor component thereon; (iv) The printable semiconductor component disposed on the contact surface contacts the receiving surface of the substrate; and (v) the contact surface of the conformal transfer device and the printable semiconductor component Wherein the printable semiconductor element is transferred onto the receiving surface, whereby the combination of the printable semiconductor element on the receiving surface of the substrate.

In one embodiment, the present invention provides a method for fabricating a printable semiconductor component comprising the steps of: (1) providing a germanium wafer having a (111) orientation and having an outer surface; (2) Generating a plurality of recess features on the outer surface of the germanium wafer, wherein each of the recess features comprises a bottom surface and a plurality of side surfaces of the exposed germanium wafer; (3) masking the recess features At least a portion of the side surfaces; and (4) etching between the recess features, wherein etching is performed along the <110> direction of the germanium wafer to form the printable semiconductor component.

BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings, like reference numerals refer to the In addition, hereinafter, the following definition is used: "printable" means that the substrate can be transferred, combined, patterned, organized and/or integrated without subjecting the substrate to high temperatures (ie, at temperatures below or equal to about 400 degrees Celsius). Materials, structures, device components, and/or integrated functional devices on or in the substrate. In one embodiment of the invention, the printable material, component, device assembly, and device can be transferred, combined, patterned, organized, and/or integrated onto a substrate or substrate by solution printing or dry transfer contact printing. Inside.

The "printable semiconductor component" of the present invention includes a semiconductor structure that can be combined and/or integrated onto the surface of a substrate, for example, by dry transfer contact printing and/or solution printing. In one embodiment, the printable semiconductor component of the present invention is a monolithic, polycrystalline or microcrystalline inorganic semiconductor structure as a whole. In one embodiment, the printable semiconductor component is connected to a substrate, such as a mother wafer, via one or more bridging elements. In the context of this description, a unitary structure is a monolithic component having a number of mechanically connected features. The semiconductor device of the present invention may be doped or undoped, may have a selected dopant spatial distribution and may be doped with a plurality of different dopant materials, including P-type and N-type dopants. . The present invention includes microstructured printable semiconductor components having a cross-sectional dimension greater than or equal to about 1 micron and nanostructured printable semiconductor components having a cross-sectional dimension of less than or equal to 1 micron. Printable semiconductor components suitable for use in many applications include components obtained by top-down processing of high quality bulk materials, such as high purity crystalline semiconductor wafers produced using conventional high temperature processing techniques. In one embodiment, the printable semiconductor component of the present invention comprises a composite structure having an operative connection to at least one other device component or structure (eg, a conductive layer, a dielectric layer, an electrode, other semiconductor structures, or the like) A semiconductor of any combination of device components or structures. In one embodiment, the printable semiconductor component of the present invention comprises a stretchable semiconductor component and/or a heterogeneous semiconductor component.

"Sectional dimension" means the dimension of the section of the device, device component or material. Section dimensions include width, thickness, radius and diameter. For example, a printable semiconductor component having a strip shape is characterized by length and two cross-sectional dimensions - thickness and width. For example, a printable semiconductor component having a cylindrical shape is characterized by a length and a cross-sectional dimension diameter (or radius).

"Orientation in a substantially parallel configuration in the machine direction" refers to an orientation in which the orientation of the longitudinal axis of a group of elements (e.g., printable semiconductor elements) is substantially parallel to a selected alignment axis. In the context of the present description, substantially parallel to a selected axis means that the orientation is within 10 degrees of an absolutely parallel orientation, more preferably within 5 degrees of an absolutely parallel orientation.

As used herein, the terms "flexible" and "flexible" are used synonymously and mean that a material, structure, device or device component is not subject to significant strain (eg, characterizing a failure point of a material, structure, device or device component). The change in strain can be transformed into a curved shape. In an exemplary embodiment, the flexible material, structure, device or device component can be deformed to form a curved shape without introducing greater than or equal to about 5%, preferably greater than or equal to about 1% and in some applications. Good strain greater than or equal to 0.5% in some applications.

"Semiconductor" means any of the following materials: it is an insulator at very low temperatures, but has a considerable electrical conductivity at a temperature of about 300 Kelvin. In this description, the use of the term "semiconductor" is intended to be consistent with the use of the term in the field of microelectronics and electronic devices. Semiconductors suitable for use in the present invention may include elemental semiconductors such as ruthenium, osmium, and diamond, and compound semiconductors such as Group IV compound semiconductors such as SiC and SiGe; Group III-V semiconductors such as AlSb, AlAs, Aln, AlP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP; III-V ternary semiconductor alloys, such as Al _x Ga _{1 - x} As; II-VI semiconductors, such as CsSe, CdS, CdTe, ZnO , ZnSe, ZnS and ZnTe; Group I-VII semiconductor CuCl; Group IV-VI semiconductors such as PbS, PbTe and SnS; layered semiconductors such as Pbl ₂ , MoS ₂ and GaSe; oxide semiconductors such as CuO and Cu ₂ O . The term "semiconductor" includes an intrinsic semiconductor and an exogenous semiconductor doped with one or more selected materials, including a semiconductor having a P-type dopant material and an n-type dopant material to provide an advantageous electrical power for a given application or device. characteristic. The term "semiconductor" includes composite materials comprising a mixture of semiconductors and/or dopants. Specific semiconductor materials suitable for use in certain applications of the invention include, but are not limited to, Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO , ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP. Porous germanium semiconductor materials are suitable for use in the present invention in sensors and luminescent materials, such as in light emitting diodes (LEDs) and solid state lasers. Impurities in the semiconductor material are atoms, elements, ions and/or molecules other than the semiconductor material itself, or any dopant provided to the semiconductor material. Impurities are materials that are undesirable in semiconductor materials that may adversely affect the electrical properties of the semiconductor material, including but not limited to oxygen, carbon, and metals, including heavy metals. Heavy metal impurities include, but are not limited to, a family of elements between the copper and lead on the periodic table of elements, calcium, sodium, and all of their ions, compounds, and/or complexes.

"Good electronic performance" and "high performance" as used in this specification are synonymous, meaning that the device and device components have electronic characteristics that provide the required functionality (eg, electronic signal switching and/or amplification), such as Effective mobility, threshold voltage and on-off ratio. Exemplary printable semiconductor devices of the present invention that exhibit good electronic performance have an intrinsic field effect mobility greater than or equal to 100 cm ² V ^{- 1} s ^{- 1} , preferably greater than or equal to about 300 cm ² in some applications. V ^{- 1} s ^{- 1} . Exhibit field effect mobility transistor device of the present exemplary good electron effectiveness of the invention may have greater than or equal to ^{100 cm 2 V - 1 s -} 1, preferably greater than or equal to about 300 cm ² V in certain applications ^{- 1} s ^{- 1} , and more preferably greater than or equal to about 800 cm ² V ^{- 1} s ^{- 1} in some applications. Exhibit good electronic performance of the present invention, an exemplary transistor may have less than about 5 volts of the threshold voltage and / or greater than about 1 x 10 ⁴ of the opening - off ratio.

"Plastic" means any synthetic or naturally occurring material or combination of materials that can be molded or formed (usually when heated) and hardened to the desired shape. Exemplary plastics suitable for use in the devices and methods of the present invention include, but are not limited to, polymers, resins, and cellulose derivatives. In the present description, the term "plastic" is intended to include composite plastic materials containing one or more plastics and one or more additives, such as structural reinforcing agents, fillers, fibers, plasticizers, stabilizers or Additives that provide the desired chemical or physical properties.

"Elastomer" means a polymeric material that can be stretched or deformed and returned to its original shape without significant permanent deformation. Elastomers are generally able to withstand significant elastic deformation. Exemplary elastomers suitable for use in the present invention can include polymers, copolymers, or composites or mixtures of polymers and copolymers. An elastic layer refers to a layer comprising at least one elastomer. The elastic layer may also contain dopants and other non-elastic materials. Elastomers suitable for use in the present invention may include, but are not limited to, thermoplastic elastomers, styrenic materials, olefin materials, polyolefins, polyurethane thermoplastic elastomers, polyamines, synthetic rubbers, PDMS, polybutadiene. , polyisobutylene, poly(styrene-butadiene-styrene), polyurethane, polychloroprene and polyfluorene.

"Transfer device" means a device or device component that is capable of receiving and/or repositioning an element or array of elements, such as a printable semiconductor component. A transfer device suitable for use in the present invention includes a conformal transfer device having one or more contact surfaces capable of forming a conformal contact with the member being transferred. The method and construction of the present invention is particularly suitable for use in conjunction with a transfer device comprising an elastic stamp.

"Large area" means that the area (e.g., the area of the receiving surface in the substrate used for device fabrication) is greater than or equal to about 36 square feet.

"Field effect mobility of a device" refers to the field effect mobility of the electrical device calculated using output current data corresponding to an electrical device (eg, a transistor).

"Conformal contact" means a contact formed between each surface, the coated surface and/or the surface on which the material is deposited, wherein the material deposited on the surface is suitable for transfer, assembly, organization and integration of a substrate surface. The structure above (for example, a printable semiconductor component). In one aspect, the conformal contact involves macroscopically adapting one or more contact surfaces of a conformal transfer device to the overall shape of the surface of the substrate or the surface of an object (e.g., a printable semiconductor component). In another aspect, the conformal contact involves microscopically fitting one or more contact surfaces of a conformal transfer device to a substrate surface to form a void-free, intimate contact. The term "conformal contact" is intended to be consistent with the use of this term in the field of soft lithography. A conformal contact can be formed between one or more exposed contact surfaces of a conformal transfer device and a substrate surface. Alternatively, a conformal formation may be formed on one or more coated surfaces of a conformal transfer device, such as a transfer surface on which a transfer material, a printable semiconductor component, a device component, and/or a device are deposited. contact. Alternatively, one or more exposed surfaces or coated contact surfaces of a conformal transfer device may be coated with a material (eg, transfer material, solid photoresist layer, prepolymer, liquid, A conformal contact is formed between the surfaces of the substrate of the film or fluid.

"Placement accuracy" means a transfer method or apparatus that transfers a printable component (eg, a printable semiconductor component) to or from a selected one of a plurality of device components, such as an electrode, The ability to choose a location. "Good placement" precision means that the method or device is capable of transferring a printable element relative to another device or device component or to a selected one of a receiving surface to a selected position relative to absolute accuracy The spatial offset of the location is less than or equal to 50 microns, more preferably less than or equal to 20 microns in some applications and even more preferably less than or equal to 5 microns in some applications. The present invention provides a device comprising at least one printable element that is transferred with good placement accuracy.

"Fidelity" refers to a measure of how well a selected component pattern (e.g., a printable semiconductor component pattern) is transferred to a receiving surface of a substrate. Good fidelity refers to maintaining the relative position and orientation of the various elements during transfer during transfer of a selected component pattern, for example, where the individual elements are positioned relative to their position in the selected pattern. The deviation is less than or equal to 500 nm, more preferably less than or equal to 100 nm.

"Undercutting" means that the bottom surface of one of the components (eg, a printable semiconductor component, a bridging component, or both components) is at least partially separated or unsecured from another structure (eg, a mother wafer or a bulk material). To the structural structure of the other structure. Full undercut refers to a structural structure in which the bottom surface of one of the components (eg, a printable semiconductor component, a bridge component, or both components) is at least partially completely separated from another structure (eg, a mother wafer or a bulk material). . The undercut structure can be partially self-standing or fully self-standing. The undercut structure may be partially or completely supported by another structure with which it is separated, such as a mother wafer or a bulk material. The undercut structure can be attached, secured, and/or attached to another structure (eg, wafer or other agglomerated material) at a surface other than the bottom surface. By way of example, the invention includes methods and configurations in which a printable semiconductor component and/or bridging component is attached to a wafer at an end located on a surface other than its bottom surface (see, for example, Figures 2A and 2B).

In the following description, numerous specific details of the device, device components and methods of the present invention are set forth to illustrate the precise nature of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without the specific details.

The present invention provides methods and apparatus for making printable semiconductor components and combining printable semiconductor components and printable semiconductor component patterns onto the surface of a substrate. Methods are provided for making high quality printable semiconductor components from low cost bulk semiconductor materials. The present invention also provides a semiconductor structure and method for achieving high precision alignment of a printable semiconductor component from a mother wafer to a transfer device and/or a receiving substrate. The method, apparatus and device assembly of the present invention are capable of producing high performance electronic and optoelectronic devices and arrays of devices on flexible plastic substrates.

1A provides a schematic cross-sectional view illustrating an exemplary method of the present invention for fabricating a printable semiconductor component comprising a printable single crystal germanium semiconductor strip from a (111) oriented bulk wafer. 1B provides a flow diagram illustrating the processing steps in the method of the present invention for producing a printable semiconductor component from a germanium wafer, including repeatable processing steps.

As shown in FIG. 1A (Screen 1) and 1B, a germanium wafer 100 having a (111) orientation is provided. The wafer 100 having the (111) orientation can be a one-by-one wafer. A plurality of channels 110 having pre-selected physical dimensions, pitches, and spatial orientations are etched into the outer surface 120 of the germanium wafer 100 using, for example, one of near field lithography, lift-off techniques, and dry etch techniques. In this embodiment, the spacing 130 between the channels defines the width of the printable semiconductor strips made using this method.

As shown in FIG. 1A (screen 2) and 1B, a thermal oxide layer 140 is grown on the trench 110 and the outer surface 120, for example, by heating the (111) germanium wafer 100, as desired. Next, a mask 150 is deposited on the side and outer surfaces 120 of the trench 110, for example, by oblique electron beam evaporation of one or more masking materials, such as a metal or metal combination, for use in the germanium wafer 100. A masked area and an unmasked area are created. The masking step creates a masked region 160 in the side surface of the channel 110 and an unmasked region 170 in the side surface. The present invention includes embodiments in which a mask is applied to the entire side surface of the channel 110 along the depth 135 (see, for example, FIG. 1D). In some embodiments, the masked area can be controlled by the evaporation angle of the mask material, the "shadow" projected by the surface features on the outer surface 120 of the wafer 100, and the degree of collimation of the mask material flux. The extent of the downward extension along the side surface. The depth 135 of the trench 110 and the extent of the masked region 160 in the side surface at least partially define the thickness of the printable semiconductor strip produced by the methods. The exposed areas of the thermal oxide layer 140 are removed, for example, using dry chemical etching techniques, prior to performing other processing, as desired.

As shown in FIG. 1A (Screen 3) and 1B, the unmasked region 170 in the side surface of the trench 110 is etched. In an exemplary embodiment, anisotropic etching is performed on the unmasked regions 170 in the side surfaces of the trenches 110 such that etching between the trenches is preferentially performed in the <110> direction of the germanium wafer 100. The undercut is performed on the region between the adjacent channels 110 in the (111) wafer 100. The etching front end <110> direction is schematically shown by a broken line arrow in the screen 3 in FIG. 1B. In one embodiment, an anisotropic etch system is selected such that etching does not substantially occur along the <111> direction of the germanium wafer 100. The selectivity of the anisotropic etch system and the (111) orientation of the germanium wafer 100 provides an intrinsic etch stop layer, which is schematically represented by dashed line 175. An anisotropic etching system suitable for use in this aspect of the invention includes a wet chemical etching system using a hot alkaline solution. In some embodiments, an etching system is selected for the processing step that produces a printable semiconductor strip having a relatively smooth bottom surface (e.g., a roughness of less than 1 nanometer).

As shown in FIG. 1A (screen 4) and 1B, the etching between the trenches produces a printable semiconductor strip 200 that is completely undercut from the germanium wafer 100. In one embodiment, the physical dimensions, shape, and spatial orientation of the channel 110 are selected such that the etch process steps produce a printable semiconductor strip 200 that is coupled to the germanium wafer 100 at one or more ends. The printable semiconductor strip 200 produced by the method of the present invention can be a flat, thin, and mechanically flexible printable semiconductor strip. The mask 150 is removed, as desired, for example by wet chemical etching techniques.

Referring to the flow chart of FIG. 1B, the method of the present invention includes the step of releasing the printable semiconductor component from the wafer by, for example, contacting an elastic stamp, as desired. In an exemplary method, contacting a printable semiconductor component with an elastic stamp causes one or more bridging elements for connecting the printable semiconductor component to the germanium wafer 100 to rupture, thereby achieving the (printable) printability. The semiconductor component is transferred from the wafer 100 to the alignment of the elastic stamp. The method of the present invention involves achieving a coordinated transfer of the self-twisting wafer 100 to an elastic stamp transfer device using a power controlled peel rate.

If desired, the present invention includes high throughput manufacturing methods that further include, for example, surface treatment steps (eg, polishing, grinding, etching, micromachining, etc.) that enable the tantalum wafer 100 to produce a flat and/or smooth outer surface. Renovate the outer surface of the wafer. As shown in FIG. 1B, refurbishing the surface of the wafer 100 enables the fabrication process to be repeated multiple times, thereby providing a high yield of printable semiconductor strips from a single wafer of starting material.

1C provides a schematic process view in a cross-sectional view illustrating a method of fabricating a partial mask on a side surface of a recessed feature rather than a full mask. 1D provides a schematic process view in a cross-sectional view illustrating a method of fabricating a full mask on a side surface of a recessed feature. As shown in FIG. 1D, a mask is also applied to some, but not all, of the bottom surface of the recessed features. In this embodiment, the method includes the step of etching a material located beneath the masked side surface of the recessed feature. Such a partially masked bottom surface configuration can provide an etchant inlet for etching between recessed features, such as adjacent recessed features. The method of the present invention which employs a full mask on the side surface of the recessed feature facilitates improved accuracy and precision in defining and selecting the thickness of the printable semiconductor component. In an embodiment, the opposite side surface is fully masked such that a passivation boundary appears on the bottom surface of the recessed feature. In such methods, the thickness of the strip is not defined by the passivation boundary, but by the height of the bottom surface of the trench and the top surface of the wafer.

The method for fabricating the printable semiconductor component of the present invention may further comprise the step of improving the geometry, physical dimensions and morphology of the recessed features. Improvements to the recessed features can be performed at any point in the fabrication process after the formation of the recessed features, prior to formation and/or release of the printable semiconductor component. In a suitable embodiment, the improvement of the recessed features is performed prior to the processing steps involving partial or complete masking of the side surfaces of the recessed features. Figure 1E provides an image of a recessed feature in Si (111) with a trench configuration resulting from no side surface improvement. The recessed features shown in FIG. 1E are defined by phase shift lithography, metal lift-off and reactive ion etching, and then removal of the metal etch mask. Figure 1F provides an image of the recessed features in Si (111) with a trench configuration resulting from side surface improvement. The recessed features shown in FIG. 1F are defined by phase shift lithography, metal lift-off and reactive ion etching, anisotropic etching in a hot KOH solution, and subsequent removal of a metal etch mask. . The sample was also treated by oblique metal evaporation. As shown by comparison of the three figures, the bottom and side surfaces of the trenches in FIG. 1F are more smoothly defined than the bottom and side surfaces of the trenches in FIG. 1E.

In this context, "improvement" refers to the material removal process on the surface of the recessed features, such as the side and bottom surfaces of the recessed features. Improvements include treatments that form smoother concave feature surfaces and/or processes that can form recessed features with more uniform physical dimensions and surface morphology. In one embodiment, the geometry, physical dimensions, and/or morphology are improved by an anisotropic etch technique, such as by etching using a hot KOH solution. The anisotropic wet etch improvement of the trenches is particularly useful for creating (111) ruthenium strips that enable alignment transfer. Advantages of such improved processing steps include: (i) providing an improved definition of the bottom surface of the trench defined by the crystal axis of the mother wafer, and (2) providing a trench defined by the crystal axis of the mother wafer Improved definition of the side surface.

2A and 2B provide schematic top plan views of a printable semiconductor structure of the present invention including a printable semiconductor component and two bridge components. In the configuration shown in Fig. 2A, the bridging elements are positioned away from each other, and in the configuration shown in Fig. 2B, the bridging elements are positioned close to each other. As shown in FIGS. 2A and 2B, the printable semiconductor structure 290 includes a printable semiconductor component 300 and a bridging component 310. The bridging element 310 is aligned with a holding element that connects the semiconductor element 300 to and is integrally connected to the mother wafer 320 as needed. In one embodiment, the printable semiconductor component 300 and the bridging component 310 are partially or completely undercut from the mother wafer 320. In one embodiment, the printable semiconductor component 300, the bridging component 310, and the mother wafer 320 are a unitary structure, such as a single continuous semiconductor structure.

The printable semiconductor component 300 extends longitudinally along the longitudinal axis 340 by a length 330 and extends a width 350. The length 330 terminates in a first end and a second end 400 that are coupled to the bridging element 310. The bridging element 310 extends a length 360 and extends a width 370. In the embodiment illustrated in Figures 1A and 1B, the bridging elements are connected to the entire width and/or cross-sectional area of the end 400 of the printable semiconductor component 300. As shown in Figures 2A and 2B, the width 370 of the bridging element 310 is less than the width 350 of the printable semiconductor component 300 to facilitate alignment transfer. In addition, the surface area of the exposed surface of the semiconductor element 300 is greater than the surface area of the exposed surface of the bridging element 310. In certain processing and transfer methods of the present invention, the sizing properties of the bridging element 310 and the printable semiconductor component 300 facilitate achieving high precision alignment transfer, assembly, and/or integration of the printable semiconductor component 300.

The structural support provided by the bridging element 310 can maintain the semiconductor component 300 in a preselected spatial orientation before and/or during transfer of the semiconductor component 300 from the wafer 320, for example, using an elastic stamp transfer device. In many manufacturing applications where the relative position, spacing and spatial orientation of one or more of the printable semiconductor components corresponds to a desired functional device and/or circuit design, it is desirable to have the anchoring functionality of the bridging component 310. The physical dimensions, spatial orientation and geometry of the bridging elements are selected such that the semiconductor component 300 can be released upon contact with a transfer device. In some embodiments, release is achieved by, for example, rupturing along the dashed line shown in Figures 2B and 2B. In some applications, the force required to break the bridging element 310 is sufficiently low to make the position and spatial orientation of the semiconductor component 300 substantially undisturbed during transfer.

In the present invention, the spatial arrangement, geometry, composition, and physical dimensions of the bridging elements, or any combination thereof, are selected to achieve high precision alignment transfer. 2C and 2D provide images of a bridging element for connecting a printable semiconductor component to a mother wafer. A printable germanium component and a (narrow) bridging component for connecting the printable component to a mother (SOI) wafer are shown in FIG. 2C. The geometry of the printable semiconductor component and the bridging component is defined by SF6 etching. As shown in Figure 2C, the printable semiconductor component and the bridging component have rounded corners. The equiangular fillet nature and the overall geometry of the elements reduce the ability to release the printable semiconductor component with a PDMS transfer device. Also shown in Figure 2D is a printable germanium component and a (narrow) bridging component for connecting the printable component to a mother (SOI) wafer. The geometry is defined by thermal KOH anisotropic etching. As shown in Figure 2D, the printable semiconductor component and the bridging component have sharp corners. The equiangular sharp corner properties concentrate the stress at the well-defined breakpoint and thus enhance the ability to release the components with a PDMS transfer device.

Example 1: Printed Array of Aligned GaAs Conductors for Flexible Transistors, Diodes, and Circuitry on Plastic Substrates

Aligned GaAs wire arrays with integrated ohmic contacts from high quality, single crystal wafers by photolithography and anisotropic chemical etching are transistors, Schottky diodes on flexible plastic substrates, Logic gates and even more complex circuits provide a promising class of materials. These devices exhibit excellent electrical and mechanical properties that are important in the emerging low cost, large area flexible electronic devices (commonly referred to as giant electronic devices).

Microcrystalline and nanoscale wires, strips, small plates, etc. of single crystal inorganic semiconductors are attractive functional devices (eg optical devices, optoelectronic devices, electronic devices, sensing devices, etc.) that can be used in many applications. Piece. For example, Si nanowires synthesized by the "bottom up" method can be combined into an aligned array using Langmuir/Blodgett technology (or microfluidic technology) and used as a flexible thin film transistor (TFT) on a plastic substrate. The transport channel. In a different approach, a "top-down" approach can be used to produce a thickness of ~100 nm from a high-quality single-crystal bulk material (such as a silicon-on-insulator (SOI) wafer or a bulk wafer). Micro/nano scale Si (microstructured germanium; μs-Si) elements in the form of strips ranging from a few micrometers to hundreds of micrometers. This type of material can be used to make devices with a mobility of up to 300 cm ² on plastics. V ¹ . S ^{- 1} flexible TFT. The high quality of wafer-based source materials (in terms of well-defined doping levels, doping uniformity, low surface roughness, and surface defect density) results in germanium-based semiconductor materials with equally good properties. Conducive to the realization of reliable, high-performance device operations. The "top-down" manufacturing process is also attractive because it provides a high degree of ordering that is defined on the wafer layer during "dry transfer printing" to final (eg plastic or other) device substrates. The possibility of organizing nanostructures/microstructures. Although high performance can be achieved with germanium, even better properties (e.g., operating speed) can be achieved with GaAs (for example) because GaAs has ~8500 cm ² . V ¹ . The high intrinsic electron mobility of s ^{- 1} . Previous studies have demonstrated techniques for producing nanowire/micron wires with triangular cross-sections from GaAs wafers using an anisotropic chemical etching step in a "top-down" fabrication step. By forming ohmic contacts on the GaAs wires while the GaAs wires are still bonded to the wafer, and then transferring them onto the plastic substrate, mechanically flexible properties with excellent properties are formed. Metal semiconductor field effect transistor (MESFET). The transistors exhibit a unit small signal gain in the gigahertz range. This example demonstrates the use of these types of MESFETs and GaAs-based diodes as active components, and transfer printing as a combination/integration strategy to build functional circuit components on plastic substrates (eg, inverters and logic gates). ) ability. These types are important in large-area electronic circuits for steerable antennas, organ health monitors, and other devices that have high requirements for high-speed, high-performance flexible devices on lightweight plastic substrates. .

FIG. 3A illustrates the main steps for fabricating a GaAs transistor, a diode, and a logic gate on a plastic. The basic method relies on "top-down" manufacturing techniques to produce micro/nano wires with high purity and well-known doping profiles from bulk single crystal GaAs wafers. The ohmic contacts formed on the wafer prior to fabrication of the wires are deposited and annealed on a 150 nm n-GaAs epitaxial layer on a (100) semi-insulating GaAs (SI-GaAs) substrate ( Composition of 120 nm AuGe/20 nm Ni/120 nm Au in a first-class N ₂ quartz tube at 450 ° C for 1 minute). Contact strip edge (0 The crystals are oriented and have a width of 2 μm. In the case of a transistor, the gap between the ohmic strips defines the channel length. Photolithography and anisotropic chemical etching produce a GaAs wire array having a triangular cross section (inset of Figure 3B) and a width of ~2 μm with an end connected to the wafer (Fig. 3B). These connections act as "anchors" to maintain the well-defined orientation and spatial position of the wires - defined by the design of the etch mask (ie, the photoresist pattern). The surface of the wire for transfer printing was prepared by removing the etch mask and depositing a double layer of Ti(2 nm)/SiO ₂ (50 nm) by electron beam evaporation. Triangular cross-section ensures that the upper surface of the conductor Ti / SiO ₂ film is not connected to the mother wafer Ti / SiO ₂ film, thus contributing to improve the yield of the transfer printing. Lamination of a slightly oxidized poly(dimethyl methoxide) (PDMS) stamp onto the surface of the ruthenium wafer results in a chemical bond between the surface of the PDMS stamp and the fresh SiO ₂ film due to the condensation reaction. See the top frame in Figure 3A. Stripping the PDMS stamp pulls the wire away from the wafer and bonds it to the stamp. The "coated" stamp is brought into contact with a sheet of poly(ethylene terephthalate) (PET) coated with a thin layer of liquid polyurethane (PU), the PU is cured, and the stamp is peeled off. Subsequent removal of the Ti/SiO ₂ layer in the 1:10 HF solution leaves an ordered array of GaAs wires on the PU/PET substrate, as shown in the middle of Figure 3A. The Ti/SiO ₂ film not only serves as an adhesive layer for bonding GaAs wires to PDMS, but also prevents the surface of the GaAs wires from being contaminated during processing (for example, by solvents and PU).

Exposing the clean exposed surfaces of the wires and ohmic strips in such a manner as to further perform lithography and metallization to define source and drain electrodes for connecting the ohmic contacts integrated on the wires ( Au at 250 nm. For a transistor, the electrodes define a source and a drain; and for a diode, it corresponds to a resistive electrode. The contact formed on the bare portion of the wire by photolithography and lift-off (150 nm Ti/150 nm Au) defines the Schottky junction of the diode and the MESFET when it is integrated with the plastic substrate Gate electrode. All treatments for the plastic substrate were carried out at temperatures below 110 °C. We have not observed any detachment of GaAs wires from the substrate due to inconsistent thermal expansion coefficients or other possible effects. In a transistor, the width of the gate electrode represents the critical dimension used to control the operating speed. In this work, the position of the electrode between the source and the drain is relatively unimportant. This poor alignment tolerance, which is not present in non-self-aligned high speed MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices, is critical to the reliable high speed operation on plastic substrates. In plastic substrates, it is often difficult or impossible to achieve precise alignment due to slight uncontrolled deformations in the plastic during processing. A functional logic circuit is created by connecting a plurality of transistors and diodes together in an appropriate geometry. The scheme shown in Figure 3A shows a NOR gate.

A scanning electron microscope (SEM) image (Fig. 3C) shows ten parallel wires that form a semiconductor component in a transistor. The channel length and gate length of the device are 50 μm and 5 μm, respectively. These geometries are used to construct a simple integrated circuit, a logic gate. The Ti/Au strip in the gap between the source electrode and the germanium electrode forms a Schottky junction with an n-GaAs surface. The electrode acts as a gate for modulating the current between the source and the drain. The diode (Fig. 3D) uses a wire with an ohmic strip on one end and a Schottky junction on the other end. 3E and 3F show images of a set of GaAs transistors, diodes, and simple circuits on a PET substrate. In Figure 3F, the PET sheets with circuitry are bent around a white marking axis to indicate that the electronic units are flexible.

The DC characteristics of the wire-based MESFET (Fig. 3C) on the plastic exhibit qualitatively the same behavior as the MESFET formed on the wafer. The current ( I _DS ) between the source and the drain is sufficiently modulated by the bias voltage (V _{G S} ) applied to the gate, i.e., I _DS decreases as V _{G S} decreases. In this case, the negative V _{G S} depletes the effective carrier (i.e., electrons for n - GaAs) in the channel region and reduces the channel thickness. Once V _{G S} becomes a sufficiently large negative value, the depletion layer is equal to the thickness of the n - GaAs layer and the current between the source and the drain is broken (ie, I _DS becomes substantially zero). As shown in Figure 4A, when V _{G S is} less than -2.5 V, I _DS drops to almost zero. The turn-off voltage (ie, the gate voltage V _{G S} ) is 2.7 V when the drain-source voltage (V _{D S} ) is 0.1 V (ie, a linear region). Figure 4B shows the transfer curve of the transistor in the saturation region (V _{D S} = 4 V). According to Fig. 4B, the ON/OFF current ratio and the maximum transconductance are determined to be ~10 ⁶ and ~880 μS, respectively. The total source-drain current varies with the number of wires (ie, the effective channel width) and the distance between the source and the drain (ie, the channel length). A transistor with a short channel can provide a relatively high current with a constant channel width. For example, at V _{G S} =0.5 V and V _{D S} =4 V, the saturated I _{D S} increases from 1.75 mA in the case of a transistor with a channel length of 50 μm to a channel length of 25 μm. 3.8 mA in the case of a transistor (Fig. 4C). Although in some applications, a transistor with a short channel can provide a high current, the ON/OFF current ratio tends to decrease due to the difficulty in completely breaking the current. As shown in Fig. 4C, even when V _{G S} is -5 V, the I _DS of the transistor having a channel length of 25 μm is still at a few microamperes.

The GaAs wire Schottky diode on plastic exhibits typical rectifier behavior (Fig. 4D), ie the forward current ( I ) increases rapidly as the forward bias voltage ( V ) increases, while the reverse The current remains small even at a reverse bias of up to 5 V. The I - V characteristics of the Schottky diodes can be described by a thermal electron emission model. At V >> 3 kT / q , the thermal electron emission model can be expressed as: among them (2) where J represents the forward diode current density at the applied bias voltage ( V ), the k- system Boltzmann constant, and the T- system absolute temperature (ie, 298 K in the experiment), φ _B-based Schottky barrier height and A ^{* *} Richardson effective ^system (Richardson) constant (i.e., for the GaAs is ^{8.64 A.cm - 2 .K - 2)} . By plotting the relationship between InJ and the bias voltage ( V ) (inset), the saturation current J ₀ and the ideality factor n can be determined from the intercept and slope of the linear relationship (the straight line in the illustration). The magnitude of φ _B is estimated by equation (2). φ _B and _n are usually used as evaluation criteria for the properties of the Schottky interface. Both are highly dependent on the cross-sectional state of charge between the metal and GaAs, ie an increase in the state of charge will cause φ _{B to} decrease and increase the value of n . For the diodes fabricated in this work, it is determined according to Fig. 4D that φ _B and n are 512 meV and 1.21. These devices have a slightly reduced Schottky barrier (512 meV versus ~800 meV) and an increased ideal factor (1.21 vs. ~1.10) compared to diodes built on the wafer.

The GaAs wiring devices (ie, MESFETs and diodes) can be integrated into the logic gates of complex circuits. For example, connecting two MESFETs to different channel lengths with different saturation currents results in an inverter (logic NOT gate) (Figures 5A and 5B). The load transistor (top) and the switching transistor (bottom) have a channel length of 100 μm and 50 μm, a channel width of 150 μm, and a gate length of 5 μm. This design allows the saturation current of the load cell to be ~50% of the saturation current of the switching transistor, which ensures that at a small turn-on voltage, the load line intersects the V _{G S} =0 curve of the switching transistor in the linear region. . The inverter was measured in a saturated region (i.e., a bias of 5 V was applied to V _{d d} ). When applied to a large negative voltage (logic 0) to turn itself off for the gate switch transistor of the pole (V _{i n),} since the load transistor is always turned on, and thus the output node (V _{o u t)} of a voltage equal to V _{d d} (logic 1, high positive voltage). Raising V _{i n} turns the switching transistor on and provides a large current for both the primary switching transistor and the load transistor. When the switching transistor is fully turned on, that is, V _{i n} is a large positive voltage (logic 1), V _{o u t} falls to a low positive voltage (logic 0). Figure 5C shows the transfer curve. The inverter exhibits a maximum voltage gain greater than one (ie, (dV _{o u t} /dV _{i n} ) _{m a x} = 1.52) by adding a potential level conversion branch composed of a Schottky diode ( as shown in FIG. 3D), so that V _{o u t is} converted to a logic state suitable for further integration of the circuit voltage.

Combining several devices of this type in parallel or in series results in more complex logic functions such as NOR and NAND gates. For the NOA gates shown in Figures 6A and 6B, two identical parallel MESFETs are used as the switching transistors. One of the two switching transistors (V _A or V _B ) is turned on by applying a high positive voltage (logic 1) to provide a drain (V _{d d} ) to the ground (GND) via the load transistor. The large current flows to form a low level (logic 0) output voltage (V _o ). A high positive output voltage (logic 1) is obtained only when both inputs are at a high negative voltage (logic 0). The dependence of the output of the NOR gate on the input is shown in Figure 6C. In the configuration of the NAND gate (Figs. 6D and 6E), the current in all transistors is sufficiently large only when both switching transistors are turned on by applying a high positive voltage (logic 1). In this configuration, the output voltage exhibits a relatively low value (logic 0). For other input combinations, there is almost no current flowing through the transistor, resulting in a high positive output voltage (logic 1) comparable to V _{d d} (Figure 6F). The further integration of this type of logic gate and/or other passive components (such as resistors, capacitors, inductors, etc.) makes high-speed, large-area electronic systems located on plastics promising.

In summary, GaAs wires with integrated ohmic contacts made from high-quality, monolithic single-crystal wafers using a "top-down" program provide a high-performance "printable" semiconductor material and a flexible plastic. A relatively easy way to fabricate transistors, diodes, and integrated logic gates on a substrate. Separating high temperature processing steps (e.g., forming ohmic contacts) from plastic substrates and using PDMS stamps to transfer printed very ordered GaAs wire arrays is an important feature of the methods described herein. The use of GaAs wires as semiconductors is attractive for large-area printed electronic devices that require extremely high operating speeds because (i) GaAs has a high intrinsic electron mobility (~8500 cm ² V ^{- 1} s ^{- 1} It has been applied in traditional high-frequency circuits. (ii) MESFETs constructed with GaAs are easier to handle than MOSFETs because MESFETs do not require gate dielectrics, and (iii) GaAs MESFETs do not suffer from non-self Aligning the parasitic overlap capacitance present in the MOSFET, (iv) even at moderate levels of pattern alignment and resolution (which can be easily achieved on large-area plastic substrates), can also be achieved in GaAs MESFETs High speed operation. The disadvantage is that the cost of GaAs is relatively high (compared to Si) and it is difficult to create complementary circuits with GaAs wire arrangements. However, the relative ease with which high-performance transistors and diodes can be built onto plastic substrates and the ability to integrate such components into functional circuits suggests that such approaches require mechanical flexibility, lightweight construction, and There is a certain prospect for electronic systems with large area and print processing compatibility.

Experimental Part: The GaAs wafer (IQE, Bethlehem, PA) has epitaxial Si grown on a (100) semi-insulating GaAs wafer by molecular beam epitaxy (MBE) deposition in a high vacuum chamber. doped n-type GaAs layer (carrier concentration of ^{4.0 × 10 1 7 cm - 3} ). The lithography process uses AZ photoresist (AZ 5214 and AZ nLOF 2020 for positive and negative imaging, respectively), which is attached to a plastic substrate - that is, covered with a thin layer of cured polyurethane (PU, NEA 121, Norland Products Inc., Cranbury, NJ) Polyethylene terephthalate (PET of ~175 μm thick, polyester film, Southwall Technologies, Palo Alto, CA) Sheet-compatible temperature (< Implemented at 110 ° C). An anisotropic manner in an etchant (4 mL H ₃ PO ₄ (85 wt%), 52 mL H ₂ O ₂ (30 wt%), and 48 mL deionized water) that had been cooled in an ice-water bath A GaAs wafer with a photoresist mask pattern is etched. All metals are made up of an electron beam evaporator (Temescal) ~4 The speed of /s is evaporated. After depositing 50 nm thick metal, the evaporation of os was stopped to cool the sample (5 minutes) to prevent the plastic substrate from melting. This evaporation/cooling cycle is repeated to deposit more metal after the sample has cooled.

Example 2: Gehitz operation in a mechanically flexible transistor on a flexible plastic substrate

The combination of GaAs wires with ohmic contacts, soft micro-transfer transfer printing technology, and optimal device design made of bulk wafers can be mechanically flexible on low-cost plastic substrates. A transistor in which the speed of each device is in the gigahertz range and has a high degree of mechanical bendability. The methods disclosed herein include materials in a simple layout format that is patterned with moderate lithography and resolution. This example will illustrate the electrical and mechanical properties of a high performance transistor. Such structures are of great importance in certain applications, including but not limited to high speed communications and computing, and emerging areas of large area electronic systems ("giant electronics").

The large-area flexible electronic systems (ie, giant electronic devices) formed by high mobility semiconductors are of interest because of the high speed communication and/or computing power required for such types of circuits. Flexible thin film transistors (TFTs), polycrystalline germanium, and single crystal germanium wires and microstructured strips made from various inorganic materials (eg, amorphous oxide/polycrystalline oxides and chalcogenides) exhibit ratios The polycrystalline organic film (generally <1 cm ² .V ^{- 1} .s ^{- 1} ) has a much higher mobility (10-300 cm ² .V ^{- 1} .s ^{- 1} ). Previous work has demonstrated that single crystal GaAs wire arrays with extremely high intrinsic electron mobility (~8500 cm ² .V ^{- 1} .s ^{- 1} ) can be used in the geometry of metal-semiconductor field effect transistors (MESFETs). The transport channel of the TFT. This example shows that by using the best design, similar devices can operate at frequencies in the GHz range and have better bendability even at moderate lithographic resolution. Specifically, the experimental results show that for a transistor with a gate length of 2 μm, the GaAs-based MESFET on the plastic substrate exhibits a cutoff frequency higher than 1.5 GHz and when a substrate of ~200 mm thickness is used, Moderate electrical properties change at bend radii as low as ~1 cm. The simple simulation of the device behavior is in good agreement with the experimental observations and the operating frequency in the S-band (5 GHz) is available.

The basic manufacturing strategy is similar to that described elsewhere in this article, but with the best device geometry and processing to achieve high speed operation. Fabrication of an integrated ohmic strip from a (100) semi-insulating GaAs (SI-GaAs) wafer having a 150-nm n-GaAs epitaxial layer by photolithography and anisotropic chemical etching (by A GaAs wire (width > 2 μm) formed by annealing 120 nm AuGe/20 nm Ni/120 nm Au at 450 ° C for 1 minute in an N ₂ atmosphere. A thin layer of Ti(2 nm)/SiO ₂ (50 nm) is deposited on the undercut GaAs wire to serve as an adhesion layer to facilitate the transfer printing process and protect the flat surface of the wire and the ohmic contact. Contaminated by the organic matter involved in the process (mainly from the organic matter transferred from the surface of the stamp). The layer was removed by immersing the sample in a 1:10 HF solution to expose the clean surface of the GaAs wire for device fabrication in a subsequent step. In addition, the Ti/siO ₂ layer has a thinner thickness (compared to the thickness of the photoresist layer used as a transfer printing adhesive layer in the previous work) to make plastic polyethylene terephthalate (PET). The surface of the sheet is relatively flat - on which a GaAs wire array is printed by means of a spin-coated thin layer of polyurethane (PU). The enhanced surface flatness enables the deposition of narrow gate electrodes without cracks in their longitudinal direction, providing an effective way to increase the speed of operation of the device.

The MESFET formed on the PET substrate (see the SEM image of a typical transistor having a gate length of 2 μm as shown in Fig. 7A) exhibits a DC transport characteristic similar to that of the transistor built on the mother wafer. Figure 7B shows the current ( I _DS ) between the source and the drain of a device with a gate length of 2 μm at different V _{G S as a function} of the gate voltage (V _{G S} ) (inset) and with the source /Change in the voltage of the drain. The turn-off voltage is -2.7 V at 0.1 VV _{D S} (ie linear region). The ON/OFF current ratio is determined to be ~10 ⁶ based on the average measured values of many devices. These devices exhibit negligible hysteresis (inset), which is especially important for achieving high speed response. These devices exhibit better inter-device uniformity; Table 1 lists the statistical results (number of devices > 50) for MESFETs with channel lengths of 50 μm and different gate lengths. The DC characteristics are almost independent of the gate length, except that devices with larger gate lengths exhibit slightly lower ON/OFF ratios. However, the gate length plays a key role in determining the operating frequency as described below.

The inset in Figure 8A shows the layout of a device designed for microwave testing. Each cell in the test structure contains two identical MESFETs with a gate length of 2 μm, a channel length of 50 μm and a common gate, and several probes configured to conform to the layout of the RF probe. pad. During measurement, the drain (D) terminal is held at 4 V (relative to the source (S)) and the gate (G) is driven with a bias of 0.5 V coupled to RF power of 0 dBm. The equivalent voltage amplitude of the RF power at 50 Ω is 224 mV. The measurement was performed using an HP8510C Network Analyzer on a Cascade Microtech 101-190B ISS substrate (a piece of ceramic wafer covered with a laser-trimmed gold pattern) using WinCal 3.2, using a standard SOLT ( The short-open-load-through-through technique performs calibration from 50 MHz to 1 GHz for error correction. In other words, short circuit calibration is considered an ideal short circuit and open circuit calibration is considered an ideal open circuit. Since no further de-embedding is performed during calibration, the measurement reference plane is set between the input probe and the output probe. In other words, the parasitic components of the contact pads are included in the measurement. However, considering the fact that the RF signal with a frequency of 1 GHz has a wavelength of 300 mm and the length of the contact pad is 200 μm, the influence of these parasitic components on the contact pads is negligible. Since the contact pads are only 1/1500 of the wavelength, the impedance conversion effect is negligible.

The small signal current gain ( h _{2 1} ) can be derived from the measured S-parameters of the device. This magnitude shows a logarithmic dependence on the frequency of the input RF signal (Fig. 9A). The unit current gain frequency (f _T ) is defined as the frequency at which the short-circuit current gain becomes 1. This magnitude can be determined by extrapolating the curve shown in Figure 9A and determining its x-intercept based on a least squares fit of a -20 dB/decimal line. The value determined in this way is f _T = 1.55 GHz. To the best of our knowledge, the device is the fastest mechanically flexible transistor on the plastic and is the first transistor with a f _T in the gigahertz range. We also used the measured DC parameters and the calculated capacitance between the electrodes to estimate the RF response of the GaAs MESFET based on the small signal equivalent circuit model. The curve drawn from the simulation results is in agreement with the experimental results (f _T = 1.68 GHz). The model is also applicable to transistors with different gate lengths. For example, the experimental f _T (730 MHz) of a MESFET with a gate length of 5 μm is close to the simulated magnitude (795 MHz) (Figure 9B). In this model, only the essential parameters of the MESFET are considered, because the heterogeneous parameters (ie, the inductance and resistance associated with the probe pads) are considered negligible. The self-DC measurement deserves a transconductance (g _m ), an output resistance (R _{D S} ), and a charging resistor (R _i , which takes into account the fact that the charge on the channel cannot respond to changes in V _{D S} instantaneously) . The intrinsic capacitance associated with the MESFET includes components from the depletion layer capacitance, the edge ripple effect capacitance, and the geometry ripple effect capacitance. Each of these factors is calculated using a standard equation of a conventional device to equal the channel width of the sum of the widths of the individual GaAs wires. The depletion layer capacitance is characterized by gate length (L _G ), effective device width (W), and depletion height:

In the equation: It is assumed that the depletion layer is used as a parallel plate capacitor. The edge ripple effect capacitor and the geometry ripple effect capacitor are determined by the following equations: The width and length of the 150 μm and 200 μm source or drain pads.

K(k) is the first type of elliptic integral and C _{G S} (capacitance between gate and source) includes all three capacitors; while C _{D S} and C _{D G} contain only edge ripple effect capacitors and geometry ripple effect capacitors. In most cases, C _{e d g e} and C _geometric are negligible without significantly affecting the simulation results, because they are much smaller than the C _depletion commensurate with the gate length. The model takes into account the behavior of the wire array device on the plastic, including f _{T as a function of} gate length. Figure 8C compares f _{T of} a GaAs wire MESFET measured (symbol) and calculated (dashed line) with different gate lengths and a channel length of 50 μm. This model shows that f _{T can be} significantly increased by reducing the gate length or by further optimizing the design of the individual layers in the GaAs mother wafer.

We have reported initial measurements of the effect of tensile strain on wire-based MESFETs with a gate length of 15 μm. In this example, we examined the performance of high speed devices below the break point under compression and tension. The measurements are composed of full DC electrical characterizations that vary when the substrate (see Figure 9A) is bent into a concave and convex shape with different radii of curvature. The bend radius is derived by performing a geometric fit on the side view of the bent sample. The convex and concave curved surfaces cause tensile strain (given a positive value) and compressive strain (given a negative value) on the device. A device similar to that shown in the inset of Figure 8A was used to evaluate the effect of strain caused by bending on performance. When the tensile strain is increased to 0.71% (corresponding to a bending radius of 14 mm for a 200 μm thick substrate used in this work), the saturation current (ie V _{D S} = 4 V, V _{G S} = 0 V) increases by ~10%, and when the compressive strain is increased to 0.71%, the saturation current is reduced by ~20% (Fig. 9B). When the substrate is released after the substrate is bent in one of the directions, the current returns to its original value, indicating that the deformation of the plastic substrate and other components of the devices is elastically deformed within the range. (Plastic deformation of PET and PU under strain is expected to be >2%.) Study surface of strained Ga _x In _{1 - x} As or Ga _x In _{1 - x} As epitaxial layer on (100) GaAs wafer Biaxial stress and uniaxial stress applied externally (similar to this example) can cause significant shifts in bandgap energy and valence band splitting in the epitaxial layer. The tensile strain reduces the band gap energy and thereby increases the total carrier concentration (electrons and holes) and increases the current. Conversely, compressive strain increases the band gap energy and reduces the current. These phenomena are consistent with the observations made on the device. Field imaging of the bending process with an SEM microscope confirmed that there was no break in the GaAs wire at <+/-0.71% strain. When the tensile strain is higher than ~1%, the device performance is degraded due to the breakage of some wires (or cracks in the gate electrode). For conductors that are wider than the conductors used here (for example, 10 μm wide), because of their high flexural rigidity, the conductors are separated from the plastic to release bending tensile stress rather than cracking.

Since the bending strain causes the saturation current to vary by less than 20%, the change in the ON/OFF ratio mainly depends on the change in the OFF current. The change in hole concentration and the number of dislocations and surface defects in the valence band caused by the strain in the n- GaAs layer may act on the change in the OFF current of the transistor. Both tensile strain and compressive strain increase the number of dislocations and surface defects, thereby increasing the OFF current of the device. Pulling strain creates additional holes and electrons, which also increases the OFF current. Conversely, compressive strain will reduce the hole concentration. Therefore, it is expected that the OFF current of the tension-bearing MESFET will be higher than the OFF current of the device without strain. The effect of compressive strain on the OFF current of the device is minimal. Therefore, the corresponding ON/OFF ratio should decrease with tension and remain substantially the same with compression. Figure 9C shows the dependence of the measured ON/OFF current ratio corresponding variation in the saturation region, which appears to be qualitatively consistent with the above.

In summary, the results of this example show that the surface strain (both tensile strain and compressive strain, up to 0.71%) due to bending does not significantly degrade the performance of the MESFET fabricated from the modified procedure. More importantly, releasing the sample in its bent state returns the device's performance to its original state. These observations indicate that the mechanical properties of GaAs-based MESFETs on PU/PET substrates meet the requirements of many of the contemplated giant electronic device applications. In addition, these types of TFTs exhibit high speeds, which are close to the high speeds applicable to RF communication devices and other applications that require mechanical flexibility, lightweight construction, and compatibility with large area, print processing. . Some of the disadvantages of GaAs compared to Si used in conventional integrated circuits (ie, high wafer cost, inability to form reliable complementary circuits, mechanically brittle, etc.) have been reduced for the focus of this work. The importance of devices that use wires and strips in thin, flexible, moderately dense, and large-area circuit categories.

Example 3: Mechanically flexible thin film transistor using an ultra-thin strip obtained from a self-forming wafer

This example introduces a thin film transistor type using aligned single crystal thin (submicron) strip arrays by lithographic patterning and anisotropic etching of bulk germanium (111) wafers. form. Devices that print these strips onto a thin plastic substrate exhibit good electrical properties and mechanical flexibility. The effective device mobility found in the linear range is as high as 360 cm ² V ^{- 1} s ^{- 1} and the on/off ratio is >10 ³ . These results represent an important step toward the low cost method of manufacturing large area, high performance and mechanically flexible electronic systems for organ health monitors, sensors, displays and other applications.

The nature of non-penetration and the widely available feature factors make low-dimensional materials important for new applications in electronics, photonics, MEMS, and other fields. For example, high performance flexible electronic devices (eg, transistors, simple circuit components, etc.) can be constructed using micro/nano wires, strips, or tubes that are stamped, painted, or printed onto a plastic substrate. The thin high feature ratio material structure achieves bendability in a single crystal semiconductor formed from a material that is inherently fragile and brittle, and achieves stretchability in certain structural forms. Thus, these types of semiconductors provide an attractive alternative to polycrystalline/amorphous organic materials that can be treated by vacuum and solution, which typically exhibit significantly lower performance in terms of carrier mobility. The top-down method described recently can produce semiconductor wires, strips, and sheets from a wafer-based material source. This approach achieves a high degree of control over the geometry, spatial organization, doping levels, and material purity of the resulting structure. However, this method is economically attractive (especially for applications requiring large area coverage) but is subject to the cost per unit area of the wafer (on-insulator overlay, epitaxial layer on the grown substrate, etc.). limit.

In this example, we report a different approach. In particular, a thin film transistor (TFT) type using an array of aligned strips of sub-micron thickness obtained from a low cost bulk Si (111) wafer is provided. First, a procedure for manufacturing the structures and transferring them onto a plastic substrate by an elastic stamp will be described. We provide structural characterization of the strip shape, its thickness and surface morphology. Measurements of the Schottky barrier TFTs made with the printed strips indicate an n-type field effect mobility of 360 cm ² V ^{- 1} s ^{- 1} and an on/off ratio of 4000.

Figure 10 illustrates a top down method for producing thin (&lt;1 μm) strips from the surface of a Si (111) wafer (Montco Corporation, n-type, 0.8-1.8 Ω.cm). This process is first carried out near-field phase shift lithography ^13, and then peeling embodiment SF ₆ plasma metal etching (Plasmatherm RIE _{system, 40 sccm SF 6, 30 mTorr} , 200 W RF power, 45 seconds), to the surface of the Si An array of trenches of ~1 μm wide and 1 μm wide is formed (Fig. 1(a)). The spacing between the grooves defines the width of the strip (typically 10 μm). Next, a 100 nm thermal oxide was grown on the wafer at 1100 °C. Partial coverage of the trench side surface is provided by performing two metal deposition steps by oblique electron beam evaporation of Ti/Au (3/30 nm) (Fig. 10B). The "shadow" projected during these oblique evaporations defines the thickness of the strip. The trench etch conditions, the evaporation angle, and the collimation of the metal flux control the extent of the shadow and thus the strip thickness. The exposed oxide was removed by CF ₄ plasma etching (40 sccm CF ₄ , 2 sccm O ₂ , 50 mTorr base pressure, 150 W RF power, 5 minutes). Finally, the strips were undercut with a hot KOH solution (3:1:1 H ₂ O:KOH:IPA (mass ratio), 100 ° C). The etch front advances in the <110> direction while retaining the (111) plane (Fig. 10C) and forms a free-standing strip that covers a large portion (75-90%) of the original wafer. The etch mask is designed such that each strip is anchored to the wafer at the end of the trench. The fabrication is accomplished by dissolving the KI/I ₂ in water (2.67/0.67 wt% and subsequent removal of the mask with HF. The strip produced in this way is thin, flat and mechanically flexible ( Figure 10E), which is similar to the strip formed by coating the wafer with an expensive insulator using the aforementioned method. ^{5 - 7 , 1 1} Atomic Force Microscopy Method (Figure 11A) shows a typical strip thickness of ~115 Between ~130 nm. These changes appear as slight color changes in the optical micrograph (Fig. 12E). Roughness measured by AFM on a 5x5 μm area located on the underside of one of the strips (shown in Figure 12B) is 0.5 nm. This value is greater than the value of the top polished surface (0.12 nm) measured by the same method or the bottom surface (0.18 nm) of the strip produced from an SOI wafer. Other anisotropic etchants are used to reduce this roughness. The reason for the thickness variation and, to a lesser extent, the change in roughness is due in part to the edge roughness of the trench, which in turn is during the oblique evaporation process. Roughness is induced in side surface passivation. Improved side surface quality reduces strip thickness variation However, as shown hereinafter, using the procedures described herein can be made using the article to bring transistor having good performance of the apparatus is configured.

The strip can be transferred to another (flexible) substrate by a high (>95%) yield printing process, as shown schematically in FIG. To perform the printing process, a PDMS stamp is laminated to the wafer and then quickly peeled off to pick up the strips. This type of process relies on dynamic control of the adhesion of the stamp. Thus, the stamps of "coated" (Figs. 12B and 12E) can be printed by contacting another substrate. High performance flexible bottom gate TFTs can be fabricated on plastics using ITO as the gate electrode by strips printed onto a 0.2 mm thick PET substrate coated with ITO. A layer of SU-8 deposited on the ITO gate prior to printing is used as a gate dielectric and glue to facilitate strip transfer. During the printing process, the strips were sunk into the uncured SU-8 with the tops flush with the surface of the glue leaving a dielectric of about 2 μm between the bottom surface of the strips and the ITO. The source electrode and the 汲 electrode are formed by photolithography (100 μm length × 100 μm width) and thick (~0.2 μm) Ti source and drain contact defined by wet etching with HF/H ₂ O ₂ Special base barrier joints. These bottom gate devices show a unique n-type enhancement MOSFET gate modulation. The on/off ratio of the transistor reaches ~103 and the device-level mobility determined using the standard equation for the operation of the metal oxide semiconductor field effect transistor is as high as ~360 cm ² V ^{- 1} s ^{- 1} (linear region) and 100 Cm ² V ^{- 1} s ^{- 1} (saturated area, evaluated at Vd = 5 V). The mobility of the strip itself should be higher than about 20% of the device-level mobility (440 cm ² V ^{- 1} s ^{- 1} (linear) and 120 cm ² V ^{- 1} s ^{- 1} (saturated)) due to the There is a spacing between the strips so that it only fills about 83% of the channel. For substrates of 0.2 mm thickness, these strip devices can survive when the substrate is moderately bent (15 mm) but can be severely degraded when the curvature is greater (5 mm).

In summary, this example demonstrates a high yield manufacturing strategy for fabricating printable single crystal strips from bulk iridium (111) wafers. The refurbishment of the surface of the wafer after fabrication can be repeated multiple times to make tens or even hundreds of square feet of strip from 1 square foot of starting material. TFTs made from these strips on plastic show that they can be used as high performance flexible semiconductors. Such devices and their manufacturing strategies are not only applicable to large area flexible electronic devices, but are also suitable for applications requiring three dimensional or heterogeneous integration or other features that are difficult to obtain using conventional microfabrication methods.

Example 4: Flexible GaN High Electron Mobility Transistor (HEMT) on a Plastic Substrate

Flexible, large-area electronic devices – technologies that are included in the emerging giant electronics sector – have seen tremendous advances in the past few years, and several leading-edge consumer applications and military applications are expected to be commercialized in the near future. . Microelectronic circuits with novel feature factors are key components in such systems and will likely require the use of new manufacturing methods - especially printing - to fabricate such microelectronic circuits. Therefore, great attention has been given to semiconductors in printable form, and both organic materials (such as pentacene, polythiophene, etc.) and inorganic materials (such as polycrystalline germanium, inorganic nanowires) have been examined. For devices integrated on plastic substrates, this work has shown some promising results. However, its current range of applications is largely limited by the inherently poor performance of devices made from such semiconductors, such as low effective device mobility and operating frequency. We have examined a new form of printable inorganic semiconductor called microstructured semiconductor (μs-Sc) that can be fabricated on conventional and organic polymer substrates with exceptionally high performance. It has also been demonstrated that by using μs-Sc as a basis, a fully formed device can be fabricated on a semiconductor wafer and subsequently transferred to a flexible substrate without compromising its performance. This approach utilizes high quality wafer scale semiconductors while making them suitable for print-based manufacturing methods. In such materials, the single-crystal silicon μs-GaN very interesting, because it is the material having the excellent properties, including high breakdown field has a (3 MV cm ^- 0.4 MV ¹ and the GaAs cm ^{- 1} phase Band gap (3.4 eV compared to 1.4 eV for GaAs), high saturated carrier speed (2.5*10 ⁷ cm s ^{- 1} compared to GaAs 10 ⁷ s ^{- 1} ), and good thermal conductivity rate (1.3 W cm ^{- 1} and the GaAs of 0.5 W cm ^{- 1} as compared). In addition, AlGaN / GaN heterostructure heterogeneous forms of integration with a high energy will be compensated difference responsive means and the piezoelectric material of the conductive band stage and a sheet carrier density is 1.0 x 10 ^{1 3} cm ^{- 2} in the range of. These attractive properties make GaN suitable for high frequency and high power performance requirements, such as for wireless communication electronics, full color illumination, and optoelectronic subsystem UV photodetectors.

Since the first demonstration of AlGaN/GaN high electron mobility transistors (HEMT), a large number of research activities have been concentrated in this field. These efforts have enabled the device to be integrated on a wide variety of substrates, including sapphire, SiC, Si, and AlN substrates. In this example, we describe the fabrication of a flexible AlGaN/GaN heterostructure high electron mobility transistor (HEMT, as shown in the process outlined in Figure 14), which is a flexible AlGaN/GaN heterostructure high electron. The mobility transistor is processed and subsequently transferred onto the plastic sheet from its Si (111) growth substrate by a contact printing based protocol. This work demonstrates the procedure for integrating a high performance HEMT device based on a heterogeneous III-V semiconductor material onto a plastic substrate.

Figure 15 schematically shows the steps used in the manufacture of a HEMT device. The process first uses a standard sequential lithography and lift-off step to form a resistive contact (Ti/Al/Mo/Au) on the bulk GaN hetero-wafer (Fig. 15A). Then, a PECVD oxide layer and Cr metal are deposited to serve as a mask in the subsequent dry etching. Photolithography and etching are performed on the Cr and PECVD oxides to define the desired geometry of the GaN strips that are used as solid ink for subsequent printing. After stripping the top photoresist, ICP dry etching was used to remove the exposed GaN (Fig. 15C). The ICP etch step removes the Cr layer, but the thicker PECVD oxide layer remains substantially intact on top of the GaN. An anisotropic wet etch (Fig. 15D) was performed with tetramethylammonium hydroxide (TMAH) to remove underlying Si and separate the GaN strip from the mother substrate. In this strong alkaline etching process, a PECVD oxide layer is used to prevent ohmic junction degradation. A BOE (Buffered Oxide Etchant) process step is then used to remove residual PECVD oxide that has become very rough due to the plasma and wet etch steps. A new layer of smooth sacrificial yttrium oxide layer is then deposited on top of the GaN strip by electron beam evaporation. When printing on the GaN strip, the wafer is brought into contact with a dimethyl methoxide (PDMS) slab (Fig. 15E), and the complete transfer of μs-GaN to PDMS is achieved by rapidly moving away from the mother substrate. . Then, the "coated" slab is laminated with a polyethylene terephthalate (PET) coated with polyurethane (PU) (Fig. 15F), and topped The PU was cured using UV light on the side (Fig. 15H). Peeling the PDMS causes the μs-GaN element to be transferred onto the plastic substrate. This transfer leaves a PU residue on top of the GaN strip. When the electron beam-deposited SiO ₂ layer evaporated in the step shown in Fig. 15E is stripped by BOE, the residue is removed. The final step in the process involves forming source/drain interconnects and Schottky gate metal contacts (Ni/Au), depositing multiple layers by electron beam evaporation and using a standard stripping process. It is patterned (Fig. 15F).

To maintain the original position of the free-standing μs-GaN after removing the underlying Si (Fig. 1d), a novel microstructured semiconductor (μs-Sc) geometry as shown in the process outlined in Figure 14C is employed. . The μs-GaN strip has two narrow bridging portions at the ends of the GaN strip (ie, two breakpoints as indicated by the arrows in Figure 14C) to facilitate its transfer transfer to the PDMS printing tool. (Fig. 15E). This architecture is a significant improvement over the previously reported "peanut" design. It has been found that the rupture used to achieve the transfer process is very effective for this design. Previous "peanut-like" designs required strict optimization of the etching time and required a very uniform etch rate over a large area to produce a μs-Sc strip suitable for printing. The current "narrow bridge" design is much less sensitive to differences in etch rates. To illustrate this latter point, Figures 16A and 16B show optical images of GaN wafers taken before and after the TMAH anisotropic etch step, respectively. In these images, it is easy to distinguish between different colors of self-standing and supported GaN microstructures. Figures 16C and 16D show scanning electron micrograph (SEM) images taken during the intermediate stages of the TMAH etching step for etching underlying Si. The enlarged image in Fig. 16D and the dashed line region in Fig. 16B strongly illustrate its highly anisotropic nature, indicating that the Si etch process is a process that propagates substantially only in a direction perpendicular to the orientation of the GaN strip. In this particular system, etching is preferentially performed in the (110) direction; as shown in Figure 14C, the Si (111) surface serves as an inherent etch stop mask. Figure 16E shows an image of a coated PDMS slab in which the μs-GaN is transferred with all of the tension when aligned on the wafer. The image in Figure 16F shows an SEM micrograph of the printed structure in which the μs-GaN heterogeneous device was transferred to a PU coated PET substrate in a final step. These images show that the transfer based on the "narrow bridge portion" of the μs-GaN pattern does not destroy the heterogeneous strip.

17A and 17B show representative optical images of a μs-GaN based HEMT after transfer to a PET substrate. The various contrasts corresponding to the various layers in the schematic cross-sectional views of the devices are shown in Figure 14B. In this geometry, an active electron channel is formed between the two ohmic contacts (Ti/Al/Mo/Au) and the electron flow rate (or current is controlled by a Schottky (Ni/Au) gate contact. ). The channel length, channel width and gate width of the device shown in Fig. 17B are 20, 170 and 5 μm, respectively. Unlike previous μs-GaAs processes - which have a small fill factor limitation due to wet etching of the side surfaces, the fill factor of these devices is comparable to previously reported for the printed III-V structure. High (67% compared to 13% of μs-GaAs). Figure 17C shows a typical drain current-voltage (I-V) characteristic of a plastic-supported GaN HEMT device; biasing the gate from -3 V to 1 V in steps of 1 V. The device exhibits a maximum drain current of ~5 mA at a gate bias of 1 V and a buck bias of 5 V. FIG. 17D show the transfer characteristics of a constant drain voltage (V _d = 2 V) is measured under the. The device exhibits a threshold voltage (V _{t h} ) of -2.7 V, an on/off ratio of 10 ³ , and a transconductance of 1.5 mS. The transconductance of a GaN HEMT having the same device geometry but before transfer is 2.6 mS. The transfer process appears to reduce this value by about 38%.

A bending step was used to study the mechanical flexibility of the GaN HEMT as shown in Figure 18A. Figure 18B shows a series of transfer curves measured from the bend radius (and its corresponding strain). When the bend radius was reduced to 1.1 cm (corresponding to a strain of about 0.46%), a very stable response was observed for the measured transconductance, threshold voltage, and on/off ratio. Figure 18C shows a series of current-voltage (I-V) curves measured at maximum strain and at two locations after its release. As noted above, the effect found was relatively small and the small difference seen between the three I-V curves in Figures 17B and 18B indicates that the μs-GaN HEMT device was not damaged by the severe bending cycle.

In summary, this example illustrates a process suitable for printing high performance GaN HEMTs in flexible form on plastic substrates. We further demonstrate an effective μs-Sc geometry that facilitates transfer printing protocols, and a smart material strategy for removing sacrificial layers by anisotropic wet etching. The results show that μs-GaN technology can provide important opportunities for the development of next-generation giant electronic devices such as high-performance mobile computing systems and high-speed communication systems.

Method: A GaN microstructure was fabricated on a heterostructure GaN on a GaN (100) wafer (Nitronex) consisting of three layers of III-V semiconductor: an AlGaN layer (18 nm, undoped); a GaN buffer layer ( 0.6 μm, undoped); and AlN transition layer (0.6 μm). An ohmic contact area was opened using AZ 5214 photoresist and the exposed area was cleaned using O ₂ plasma (Plasmatherm, 50 mTorr, 20 sccm, 300 W, 30 sec). To achieve low contact resistance, the ohmic contact region was pretreated using SiCl ₄ plasma in an RIE system prior to the metallization step. Then, a Ti/Al/Mo/Au (15/60/35/50 nm from bottom to top) metal layer was deposited. Electron beam evaporation is used to deposit Ti, Al, and Mo, while Au is deposited by thermal evaporation. A stripping process is used to define the joints. The joints were annealed at 850 ° C for 30 seconds using a N ₂ atmosphere in a rapid thermal annealing system. Depositing PECVD oxide (Plasmatherm, 400 nm, 900 mTorr, 350 sccm 2% SiH ₄ /He, 795 sccm NO ₂ , 250 ° C) and Cr metal (E-beam evaporator, 150 nm) layer for subsequent ICP Etched mask material. By photolithography, wet etching (Cyantek Cr etchant) and RIE process _{(50 mTorr, 40 sccm CF 4} , 100 W, 14 min) to define GaN stripe geometry. After removing the photoresist with acetone, ICP dry etching (3.2 mTorr, 15 sccm Cl ₂ , 5 sccm Ar, -100 V bias, 14 min) was used to remove the exposed GaN, and then the TMAH wet etching solution was used. (Aldrich, 160 ° C, 5 min) to etch away the underlying Si. The sample was immersed in BOE (6:1, NH ₄ F:HF) for 90 seconds to remove the PECVD oxide and deposit a new layer of 50 nm SiO ₂ evaporated by electron beam on top of the GaN strip. Then, the GaN wafer in contact with a slab PDMS (Sylgard 184, Dow corning), and then> 0.01 ms ^{- 1} peel rate of release of the PDMS slab to dip from μs-GaN elements. Then, the PDMS slab coated with μs-GaN was laminated to a polyethylene terephthalate sheet coated with polyurethane (PU, Norland optical adhesive, No. 73) (PET, thick 100 μm, Glafix Plastics). The sample is exposed to UV light from the top (active household ozone mercury lamp, 173 μW cm ^{- 2),} so that the PU curing. The PDMS was peeled off and the electron beam oxide was removed by immersing in the BOE for 30 seconds, which transferred the μs-GaN element onto the plastic substrate. The Schottky junction region was patterned using a negative photoresist (AZ nLOF 2020) and then a Ni/Au (80/100 nm) layer was deposited by electron beam evaporation. A stripping process was used in conjunction with an AZ stripper (KWIK, 5 hours) to remove the PR.

Example 5: Printable Semiconductor Components Derived from Bulked GaAs Wafers with Multiple Epitaxial Layers

The invention includes a method of making a printable semiconductor strip using a bulk GaAs wafer as a starting material. In one embodiment, the strips are produced from a high quality agglomerated GaAs wafer having a plurality of epitaxial layers. The wafer is fabricated by growing a 200 nm thick AlAs layer on a (100) semi-insulating GaAs (SI-GaAs) wafer, followed by sequential deposition of a 150 nm thick SI-GaAs layer. and a thickness of 120 nm and a carrier concentration of 4 × 10 ^{1 7} cm ^- doping of Si ³ via the n-type GaAs layer. One defined as parallel to (0 A pattern of crystal oriented photoresist lines is used as a mask for chemical etching of the epitaxial layer (including both GaAs and AlAs). The top layer is separated into individual strips by anisotropic etching with an aqueous etchant of H ₃ PO ₄ and H ₂ O ₂ , the strips having a length and orientation defined by the photoresist and relative to The wafer surface forms an acute angle side surface. The AlAs layer is removed and removed by removing the photoresist after anisotropic etching and then immersing the wafer in an ethanol solution of HF (2:1 by volume of ethanol and 49% HF aqueous solution). GaAs (n-GaAs/sI-GaAs) strips. The use of ethanol in this step without the use of water reduces cracks that may occur in the brittle strip due to capillary forces during the drying process. The lower surface tension of ethanol compared to water also minimizes the disorder caused by the spatial layout of the GaAs strip due to drying.

GaAs wafers with epitaxial layers designed according to customer requirements are available from IQE Corporation of Bethlehem, PA. The lithography process uses AZ photoresists - AZ 5214 and AZ nLOF 2020 - for positive and negative imaging, respectively. a photoresist mask pattern in an ice-water bath etchant (4 mL H ₃ PO ₄ (85 wt%), 52 mL H ₂ O ₂ (30 wt%) and 48 mL deionized water) The GaAs wafer is anisotropically etched. HF solution (Fisher) diluted in ethanol (1:2 by volume) Chemicals) to dissolve the AlAs layer. Samples with stripped strips on the mother wafer were dried in a tin cabinet at 2-nm Ti and 28-nm SiO ₂ .

Example 6: Multilayer Printable Semiconductor Component Array Obtained from Si(111) Wafer

The present invention also includes methods and configurations for providing a multilayer printed semiconductor device array obtained from a Si (111) wafer precursor material. Figure 19 provides a schematic flow diagram illustrating a method of the invention for fabricating a multilayer printed semiconductor device array. As shown in the screen 1 of Fig. 19, a germanium wafer having a (111) orientation is provided. The outer surface of the wafer is patterned with an anti-etch mask to create a masked area that is sized to define the length and width of the printable semiconductor strip in the multi-layer array. In the example shown in FIG. 19, the etch-resistant mask is a thermally grown SiO ₂ layer.

As shown in Figure 2, the germanium wafer is etched primarily along a direction orthogonal to the patterned outer surface. The etching system used produces a recessed feature with a shaped side surface. In a preferred embodiment, the side surfaces of the recessed features have a selected spatially varying styling profile having a plurality of styling features, such as a side surface having a periodic scalloped contour and / or on the side surface of the recessed features there is a contoured profile with deep ridges. Exemplary components for creating recessed features having selected contours include STS-ICPRIE and BOE etching systems that cyclically expose the tantalum wafer to reactive ion etching gases and etching resistant materials. As shown in Figure 3 of Figure 19, the processing step produces a plurality of 矽 structures having selectively shaped side surfaces positioned adjacent the recess features.

As shown in Figure 3 of Figure 19, the processed tantalum wafer having the recessed features is deposited through the anti-etch mask material such that the shaped side surfaces of the recessed features are only partially coated with the deposited material. In such an aspect of the invention, the selected contour of the side surfaces of the recessed features at least partially determines the spatial distribution of the masking material on the side surfaces. Thus, this processing step defines the thickness of the printable semiconductor component in the multilayer stack. For example, the wafer can be subjected to oblique vapor deposition of a combination of metals or metals such that the material is primarily deposited on the ridges present in the forming surface of the recessed features without substantially depositing in the forming surface. The regions of the "shadows" of the ridges (eg, present in the recessed regions of the sidewalls). Thus, the "shadow" projected by features in the selected contour (e.g., ridges, corrugations, and scallops) at least partially defines the thickness of the printable semiconductor component in the multilayer array. The use of gold deposit materials is advantageous because gold is preferably adhered to the exposed surface.

As shown in the screen 4 of Fig. 19, the wafer is then subjected to anisotropic etching, for example, by being subjected to an alkali solution (e.g., KOH). Etching is performed between the recessed features to cause etching in the <110> direction of the germanium wafer, thereby forming a germanium structure in which each of the printable semiconductor components includes a partial or complete undercut. Multilayer printable semiconductor device array. The present invention includes a method in which etching is continued between the adjacent recess features in the <110> direction of the germanium wafer to completely undercut the (printable) semiconductor device. As explained in detail above, the etching system selected in conjunction with the (111) orientation of the germanium wafer results in an etch rate in the <110> direction of the wafer that is faster than the <111> direction in the wafer. . The position, shape, and spatial orientation of the recessed features are selected as needed to form alignment retention elements, such as bridging elements for connecting the printable semiconductor components to the wafer. In the multilayer structure shown in Figure 4, a bridging element for connecting the ends of the semiconductor strips in the multilayer array to the germanium wafer is provided.

Picture 5 of Figure 19 shows an optional processing step in which the bridging elements are released from the wafer, for example by rinsing, etching or other material removal processes, thereby producing a multilayer printed semiconductor component stack. . Alternatively, the printable semiconductor component in the array can be released by a contact printing process. In one embodiment, for example, the printable semiconductor component is sequentially released from a transfer device (eg, an elastic stamp) and sequentially released from the wafer to be printable in the multilayer array. Semiconductor component.

Figure 20 provides an SEM image of the Si (111) angled view (A, C, E, G) and a cross-sectional view (B, D, F, H): (A and B) in STS-ICPRIE and BOE etching Thereafter, (C and D) were subjected to metal protection on the opposite side surface, and (E to H) was performed after KOH etching for 2 minutes (E and F) and 5 minutes (G and H) and then metal cleaning was performed.

Figure 21 provides (A) a photograph of a large scale aligned array of four layer Si (111) strips. (B) and (D and E) oblique view of the four-layer Si (111) shown in (a).

Figure 22 provides (A) photographs and (B and C) OM images of the released flexible Si (111) strips. (D to F) SEM image of the strip shown in (A).

Figure 23 provides (A) an optical image of an aligned Si (111) strip transferred onto a PDMS substrate. (B) AFM images from the four strips of the array shown in (A). A photograph of a flexible polyester film used to accommodate four Si (111) array patterns obtained by performing four transfer cycles from a single Si wafer.

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Statement on the inclusion of references and amendments by reference

The following references relate to self-assembling techniques that can be used in the methods of the present invention for transferring, combining, and interconnecting printable semiconductor components by contact printing and/or solution printing techniques, and are incorporated herein by reference in their entirety. (1) "Guided molecular self-assembly: a review of recent efforts", Jiyun C Huie Smart Mater . Struct . (2003) 12, 264-271; (2) "Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems", Whang, D.; Jin, S.; Wu, Y.; Lieber, CM Nano Lett . (2003) 3(9), 1255-1259; (3) "Directed Assembly of One-Dimensional Nanostructures into Functional Networks", Yu Huang, Xiangfeng Duan, Qingqiao Wei, and Charles M. Lieber, Science (2001) 291, 630-633; and (4) "Electric-field assisted assembly and alignment of metallic nanowires", Peter A. Smith et al., Appl. Phys. Lett. (2000) 77(9), 1399-1401.

References cited throughout this application, including, for example, patents or equivalents granted, granted patent applications, patent applications, unpublished patent applications, and non-patent documents or other sources of material are The disclosure is hereby incorporated by reference in its entirety in its entirety in its entirety in its entirety in the extent of the extent of the extent of the disclosure of the disclosure of Portions of the references other than the partially inconsistent portions described in this reference are incorporated by reference.

Any of the appendices herein are hereby incorporated by reference in their entirety in their entirety herein in their entirety herein.

When the term "comprise,comprises,comprised" or "comprising" is used herein, it is intended to be understood to mean the existence of the recited features, integers, steps or components, but does not exclude the presence or addition of one or more Other features, integers, steps, components, or a combination thereof. It is also intended to include a separate copy of the term "comprising" or "comprise(s)" or "comprised" with the following terms as needed in a similar grammar. Embodiments of the invention: for example, "consisting/consist(s)" or "consisting essentially of/consist(s) essentially of", to illustrate other implementations that are not necessarily extended example.

The invention has been described above with reference to various specific and preferred embodiments and techniques. However, it will be appreciated that many variations and modifications can be made while still remaining within the spirit and scope of the invention. It will be readily apparent to those skilled in the art that the present invention may be practiced without departing from the scope of the invention, and other embodiments, methods, devices, apparatus, materials, procedures, and techniques described herein. . The present invention is intended to encompass all such forms as are known in the art that are functionally equivalent to the structures, methods, devices, device components, materials, procedures and techniques described herein. Whenever a range is revealed, it is intended to encompass all sub-ranges and individual values as if they were individually recited herein. The present invention is not limited to the embodiments disclosed herein, and is to be construed as being limited by the accompanying drawings. The scope of the invention is only limited by the scope of the following claims.

100. . . Silicon wafer

110. . . Channel

120. . . The outer surface

130. . . spacing

135. . . depth

140. . . Thermal oxide layer

150. . . Mask

160. . . Masked area

170. . . Unmasked area

175. . . dotted line

200. . . Printable semiconductor strip

290. . . Printable semiconductor structure

300. . . Printable semiconductor component

310. . . Bridging element

320. . . Master wafer

330. . . length

340. . . Vertical axis

350. . . width

360. . . length

370. . . width

400. . . Ends

1A provides a schematic cross-sectional view illustrating an exemplary method of the present invention for fabricating a printable semiconductor component comprising a single crystal iridium strip from a wafer having a (111) orientation. FIG. 1B provides a flow diagram illustrating the various processing steps in the method of the present invention for producing a printable semiconductor component from a germanium wafer.

1C provides a schematic cross-sectional view of a process illustrating a method of fabricating a partial but not a complete mask on a side surface of a recessed feature. FIG. 1D provides a schematic cross-sectional view of a process illustrating a method of fabricating a full mask on a side surface of a recessed feature.

Figure 1E provides an image of a recessed feature in Si (111) with a trench configuration resulting from no side surface improvement; the recessed features shown in Figure 1E are by phase shift lithography, metal stripping, and Reactive ion etching, and subsequent removal of the metal etch mask, is defined. Figure 1F provides an image of the recessed features in Si (111) with a trench configuration resulting from side surface improvement.

2A and 2B provide schematic top plan views of a printable semiconductor structure of the present invention comprising a printable semiconductor component and two bridge components. In the configuration shown in Figure 2A, the bridging elements are positioned away from each other, and in the configuration of Figure 2B, the bridging elements are positioned adjacent each other.

2C and 2D provide images of a bridging element for connecting a printable semiconductor component to a mother wafer.

3(A) schematically illustrates a process for fabricating a transistor, a diode, and a logic circuit on a plastic using a transfer printed GaAs wire integrated with an ohmic strip, the GaAs wire being from a single crystal germanium. GaAs wafers are prepared. (B) An SEM image of an array of GaAs wires (with ohmic strips) whose ends are connected to the mother wafer. The partial wires shown by the arrows are located under the wires arranged in an array, which indicates that the GaAs wires are separated from the bulk wafer. The inset shows a separate individual wire that clearly shows its triangular cross section. (C) SEM image of a single MESFET having a channel length of 50 μm and a gate length of 5 μm, which is transferred onto a PET substrate by transferring the GaAs wire array shown in (B) form. (D) Optical micrograph of a Ti/n-GaAs Schottky diode on a PET sheet. The inset shows one of the electrode pads connecting the ohmic strips on one end of the wires, while the other electrode (150 nm Ti/150 nm Au) pads are directly connected to the GaAs wires to form a Schottky junction. (E, F) Optical images of PET substrates of various logic gates and individual MESFETs mounted on a flat surface (E) or on a white marking bending axis (F).

Figure 4 is a GaAs wire MESFET with a gate length of 5 μm and a different channel length on a PU/PET substrate: (A, B) 50 μm and (C) 25 μm. (A) Current-voltage (i.e., I _{D S} - V _{D S} ) curve for the transistor shown in Figure 3C at different gate voltages (V _{G S} ). From top to bottom, V _{G S} is reduced from 0.5 V to -3.0 V in steps of 0.5 V. (B) Transfer curve of the same transistor in a saturated region of V _{D S} = 4V. The inset shows the derivative of the transfer curve, which indicates the dependence of the transconductance on the gate voltage. (C) Source-drain current of a transistor with a channel length of 25 μm at different V _{G S.} From top to bottom, V _{G S} is reduced from 0.5 to -5.0 V in steps of 0.5 V. (D) I-V characteristics of the fabricated Au/Ti-GaAs Schottky diode, which exhibits good rectifying power.

Fig. 5 is a circuit diagram (A), an optical image (B), and an output-input characteristic (C) of the inverter. All MESFETs have a gate length of 5 μm. V _{d d} is biased to 5 V with respect to ground.

Figure 6 below shows the circuit diagram, optical image and output-input characteristics of different logic gates: (A, B, C) NOR gate; (D, E, F) NAND gate. All MESFETs have a gate length of 5 μm. The scale bar represents 100 μm. V _{d d} is biased with respect to ground to 5 V. The logic "0" and "1" input signals of the NOR and NAND gates are driven by -5 and 2 V, respectively. The logic "0" and "1" outputs of the NOR gate are 1.58-1.67 V and 4.1 V, respectively. The logic "0" and "1" outputs of the NAND gate are 2.90 V and 4.83-4.98 V, respectively.

Fig. 7(A) is an SEM image of a single GaAs wire MESFET having a channel length of 50 μm and a gate length of 2 μm on the PU/PET substrate, which shows that each transistor is formed of ten aligned GaAs wires. (B) A current-voltage (i.e., I _DS - V _DS ) curve of the transistor shown in (A). From top to bottom, V _GS is reduced from 0.5 V to -3.0 V in 0.5 V steps. The inset shows the transfer curve of the transistor in the V _DS = 4 V saturation region.

Figure 8 (A, B) shows the experimental results (blue) and simulation results (red) of the RF response of GaAs wire MESFETs with different gate lengths: 2 μm (A) and 5 μm (B). These measurements are carried out in the probe configuration shown in illustration (A). (C) The dependence of f _T on the gate length. The different symbols represent measurements of different devices, with the dashed lines corresponding to the simulation results.

Figure 9 is a feature of the mechanical flexibility of a high speed GaAs wire MESFET (gate length 2 μm) on a PU/PET substrate. (A) Optical image of the measuring mechanism. The surface strain (positive and negative values correspond to tensile strain and compressive strain, respectively) versus (B) the saturation current flowing from the source to the drain at V _DS = 4V and V _{G S} =0 V; C) V _{D S} = 4 V The effect of the ON/OFF current ratio in the saturation region.

Figure 10 is a schematic flow chart showing the manufacture of a single crystal crepe strip. (A) The trench is etched in a (111) Si surface with SF ₆ plasma. (B) The side surfaces are passivated by thermal oxidation and oblique evaporation of the Ti/Au layer. (C) Finally, the Si strips were undercut with a hot KOH/IPA/H ₂ O solution. (D) A cross-sectional SEM image of a strip under partial undercut. (E) Flexible strip that has been released.

Figure 11 is an atomic force micrograph of a microstructured crucible produced by an anisotropic wet etching undercut. (A) AFM height image of the strip exposed on the bottom of a PDMS stamp. Each strip is measured at its edge by about 115 to 130 nm thick and bent downwards in the middle. (B) AFM image of the bottom surface of a 550 nm thick strip showing the roughness of the nanoscale introduced by KOH/IPA/H ₂ O undercut.

Figure 12 is a schematic flow diagram for transferring microstructured crucibles from a "donor" wafer to a plastic substrate. (A) Laminating a PDMS stamp onto a wafer that is anchored to the undercut strip on the wafer. (B) Bonding the strip to the stamp and removing the strip from the wafer by stripping the stamp. (C) The strip is then printed from the stamp onto a plastic substrate. (D) SEM image anchored to the donor wafer near the strip completely undercut. (E) Optical photomicrograph of the strip removed from the donor wafer and adhered to the stamp. (F) A photograph of a flexible plastic "wafer" containing a TFT made of a transferred ribbon.

Figure 13 is a single crystal on a PET/ITO substrate with L = 100 μm, W = 100 μm, linear mobility of 360 cm ² V ^{- 1} s ^{- 1} , and saturation mobility of 100 cm ² V ^{- 1} s ^{- 1} The electrical characteristics of the bottom gate transistor, (A) transfer characteristics (VD = 0.1 V), which show the on/off ratio of ~4000 with a top view of a device. (B) Current-voltage (I-V) characteristics.

Figure 14 (A) is a schematic diagram of a heterostructure GaN wafer for fabricating a high electron mobility transistor (HEMT, a two-dimensional electron gas (2 DEG) formed between an AlGaN and a GaN interface); (B) is located on a plastic substrate A schematic diagram of the HEMT geometry above; (C) a Ws-GaN design supported by two "narrow bridges" at the ends of the Ws-GaN strip. Self-standing Ws-GaN components were fabricated using a smart anisotropic etch orientation.

Figure 15 is a schematic illustration of the steps for fabricating a Ws-GaN HEMT on a plastic substrate.

Figure 16 shows GaN prior to TMAH wet etching of underlying Si. (B) Self-standing GaN strips after TMAH etching. Attention should be paid to the color difference between the etched region and the unetched region in the Si sacrificial layer. (C-D) An SEM image of an intermediate step of TMAH anisotropic etching of underlying Si. (E) An SEM image of a PDMS slab with a μs-GaN object by van der Waals force. (F) SEM image of μs-GaN transferred onto PET coated with PU. For easy viewing, artificially add color to the metal and polymer areas.

Figure 17 shows a high performance HEMT formed from Ws-GaN on a plastic substrate. (A-B) Optical micrograph of an actual flexible Ws-GaN device. A schematic cross-sectional view of the device geometry is shown in Figure 14B. (C) I-V curve of the Ws-GaN based HEMT in the (Vg = -4 V to 1 V) gate voltage range. The channel length, channel width and gate width of the device are 20 Wm, 170 Wm and 5 Wm, respectively. (D) Transfer characteristics measured at a constant source-drain voltage (V _{d s} = 2 V, which shows a transconductance of 1.5 mS.

Figure 18 (A) Optical image of the actual curved platform and plastic device. (B) Transfer curves obtained at different bending radii (and their corresponding strains). (C) I-V curve when bent at the maximum bending radius (orange) and flattened (blue) after the bending cycle.

Figure 19 provides a schematic flow diagram illustrating a method of the invention for fabricating a multilayer printed semiconductor device array.

Figure 20 provides an SEM image of the Si (111) angled view (A, C, E, G) and a cross-sectional view (B, D, F, H): (A and B) in STS-ICPRIE and BOE etching Thereafter, (C and D) were subjected to metal protection on the opposite side surface, and (E to H) was performed after KOH etching for 2 minutes (E and F) and 5 minutes (G and H) and then metal cleaning was performed.

Figure 21 provides (A) a photograph of a large scale aligned array of four layer Si (111) strips. (B and C) top view and (D and E) oblique view of the four-layer Si (111) shown in (A).

Figure 22 provides (A) photographs and (B and C) OM images of the released flexible Si (111) strips. (D to F) SEM image of the strip shown in (A).

Figure 23 provides (A) an optical image of an aligned Si (111) strip transferred onto a PDMS substrate. (B) AFM images from the four strips of the array shown in (A). A photograph of a flexible polyester film used to accommodate four Si (111) array patterns obtained by performing four transfer cycles from a single Si wafer.

100. . . Silicon wafer

110. . . Channel

120. . . The outer surface

130. . . spacing

135. . . depth

140. . . Thermal oxide layer

150. . . Mask

160. . . Masked area

170. . . Unmasked area

175. . . dotted line

200. . . Printable semiconductor strip

Claims (20)

A method for fabricating a printable semiconductor component, the method comprising the steps of: providing a germanium wafer having a (111) orientation and having an outer surface; generating a plurality of depressions on the outer surface of the germanium wafer a feature, wherein each of the recessed features comprises a bottom surface and a plurality of side surfaces of the exposed wafer; at least a portion of the side surfaces of the recessed features; and between the recessed features Etching is performed wherein etching is performed in the <110> direction of the germanium wafer to form the printable semiconductor component. The method of claim 1, wherein the etching is performed in the <110> direction of the germanium wafer at a rate faster than the <111> direction of the germanium wafer, or wherein the etching is not along the germanium wafer In the <111> direction. The method of claim 1, wherein the step of performing etching between the recessed features continues between adjacent adjoining features along the <110> direction of the tantalum wafer, whereby at least a portion of the undercut is located The printable semiconductor component between adjacent recessed features. The method of claim 1, wherein the recessed features comprise first and second trenches separated from each other, wherein the step of etching between the recessed features along the germanium wafer is <110> The direction proceeds from the first channel to the second channel, whereby at least a portion of the printable semiconductor component between the first channel and the second channel is undercut from the germanium wafer. The method of claim 1, further comprising the step of: After the step of creating one or more recessed features on the face, a layer of thermal oxide is grown on the outer surface of the germanium wafer. The method of claim 1, further comprising the step of releasing the printable semiconductor component from the wafer. The method of claim 1, wherein the germanium wafer is a one-by-one wafer. A printable semiconductor structure comprising a printable semiconductor component; and a first bridge component coupled to the printable semiconductor component and to a mother wafer, wherein the printable at least partially undercut from the mother wafer a semiconductor component and the first bridging component; wherein the first bridging component is connected to the entire width or cross-sectional area of the printable semiconductor component that is less than a first end; wherein contacting the printable semiconductor component with a transfer device enables The first bridging element is broken to release the printable semiconductor component from the mother wafer. The printable semiconductor structure of claim 8 wherein the transfer device is an elastic stamp. The printable semiconductor structure of claim 8, wherein the printable semiconductor component and the first bridging component are completely undercut from the mother wafer. The printable semiconductor structure of claim 8, wherein the first bridging element, the printable semiconductor component, and the mother wafer form a single semiconductor structure. The printable semiconductor structure of claim 8, wherein the printable semiconductor component has a first average width, and the first bridge component has a second average width, the second average width being at least less than the first average width 1.5 times. The printable semiconductor structure of claim 8, further comprising a second bridging element at least partially undercut from the mother wafer, the second bridging element being coupled to the solderable semiconductor component and to the mother wafer, and The contacting of the printable semiconductor element with a transfer device can cause the second bridging element to rupture. The printable semiconductor structure of claim 13 wherein the printable semiconductor component comprises a length of semiconductor strip extending along a major longitudinal axis, the length terminating at a first end and a second end, wherein the first A bridging element is coupled to the first end and the second bridging element is coupled to the second end. The printable semiconductor structure of claim 14, wherein the first bridging element, the second bridging element, the printable semiconductor strip, and the mother wafer are a monolithic semiconductor structure. The printable semiconductor structure of claim 14, wherein the first end has a first cross-sectional area and the second end has a second cross-sectional area, wherein the first bridging element is coupled to the first end Less than 50% of the first cross-sectional area and wherein the second bridging element is connected to less than 50% of the second cross-sectional area of the second end. The printable semiconductor structure of claim 13, wherein the first and second bridging elements have an average width selected from the range of from about 100 nanometers to about 1000 micrometers, selected from the range of from about 1 nanometer to about 1000 micrometers. The average thickness and the average length selected from the range of from about 100 nanometers to about 1000 micrometers. A method for transferring a printable semiconductor component to a transfer device The method includes the steps of: providing a printable semiconductor structure including a printable semiconductor component; and connecting at least one bridge component to the printable semiconductor component and to a mother wafer, wherein at least one of the master wafers Partially undercutting the printable semiconductor component and the bridging component; wherein the first bridging component is connected to the entire width or cross-sectional area of the printable semiconductor component that is less than a first end; a transfer device for contacting a surface, wherein contact between the contact surface and the printable semiconductor component causes the printable semiconductor component to bond to the contact surface; and moving the transfer device in a manner that causes the bridging component to rupture Thereby, the printable semiconductor component is transferred from the mother wafer to the transfer device. The method of claim 18, wherein the transfer device is a conformal transfer device, wherein a conformal contact is formed between a contact surface of the conformal transfer device and an outer surface of the printable semiconductor component. A method for combining a printable semiconductor component on a receiving surface of a substrate, the method comprising the steps of: providing a printable semiconductor component; and connecting to the printable semiconductor component and to a mother wafer a first bridging element, wherein the printable semiconductor component and the first bridging component are at least partially undercut from the mother wafer; wherein the first bridging component is connected to the entire width of the printable semiconductor component that is less than a first end Or cross-sectional area; contacting the printable semiconductor component with a conformal having a contact surface a transfer device, wherein contact between the contact surface and the printable semiconductor component causes the printable semiconductor component to bond to the contact surface; moving the conformal transfer device in a manner that causes the first bridging component to rupture, The transferable semiconductor component is transferred from the mother wafer to the conformal transfer device to form the contact surface with the printable semiconductor component thereon; the printable semiconductor disposed on the contact surface Contacting the receiving surface of the substrate; and separating the contact surface of the conformal transfer device from the printable semiconductor component, wherein the printable semiconductor component is transferred onto the receiving surface, whereby the printable semiconductor is The component is assembled on the receiving surface of the substrate.