TWI420824B - Analog-to-digital conversion device - Google Patents

Description

Analog digital converter

The present invention relates to a conversion device, and more particularly to an analog digital conversion device.

Analog-to-Digital Converter (ADC) converts the analog signal into a digital message and saves it with a capacitor, which is then processed by the microcomputer controller. Analog digital converters are mainly: successive-approximation, dual-slope, parallel compare or flash, and delta-sigma. Types. Analog-to-digital converters are often used in communications, instrumentation, and measurement, as well as in computer systems to facilitate digital signal processing and information storage.

For the difference and analog analog converter, the over sampling method is used together with the digital filter to generate the digital signal output. This converter does not require high-precision parts, ie has a high resolution. . The prior art difference and analog-to-digital converters are mainly composed of a feedback circuit composed of a loop filter 10, a quantizer 12, and a synchronous digital analog converter 14, as shown in FIG. The synchronous digital analog converter 14 is located on the feedback path and receives the clock signal generated by the non-ideal clock generating component 16 for the quantizer 12 to perform signal sampling and conversion operations. However, because the clock generating component 16, such as a quartz oscillator or a phase-locked loop clock generator, is inherently non-ideal (especially in an integrated circuit) will cause clock waveform jitter. Therefore, the analog-to-digital conversion by the clock generating element 16 is necessarily subject to jitter of the clock waveform to generate noise.

Accordingly, the present invention has been made in view of the above problems, and an analog-to-digital conversion apparatus has been proposed to solve the problems caused by the prior art.

The main object of the present invention is to provide an analog-to-digital conversion device that uses a non-synchronous digital analog converter to provide a fixed pulse signal without clock jitter to avoid the influence of noise on the digital output. It is further applied to high-speed analog digital conversion technology.

To achieve the above object, the present invention provides an analog-to-digital conversion device that connects an input terminal and an output terminal, and the input terminal receives an original analog signal. The analog digital conversion device receives a conversion analog signal by using a primary loop filter, and filters it to output a filtered analog signal. The loop filter and the output are connected to a quantizer, and the quantizer receives the filter analog signal for digital sampling, and outputs a digital signal from the output. The loop filter, the input end and the output end are connected to a non-synchronous digital analog converter, and thereby receive the digital signal and an original clock signal, and the asynchronous digital analog converter first adjusts the original clock signal to a fixed pulse signal to The clock jitter of the original clock signal is eliminated, and the digital signal is converted into a analog analog signal according to the fixed pulse signal to form a conversion analog signal with the original analog signal for the loop filter to receive.

For a better understanding and understanding of the structural features and the achievable effects of the present invention, please refer to the preferred embodiment and the detailed description.

As shown in FIG. 2, the analog-to-digital conversion device of the present invention is connected to an input terminal 18 and an output terminal 20, and the input terminal 18 receives an original analog signal. The present invention includes a loop filter 22, such as a continuous-time loop filter or a hybrid continuous discrete-time loop filter, which is coupled to an adder 24 An amplitude quantizer as a quantizer 26 is connected, and an adder 24 is connected to the input terminal 18, and a quantizer 26 is connected to the output terminal 20. The loop filter 22 receives a conversion analog signal from the adder 24 and filters it to output a filtered analog signal. The quantizer 26 receives the filtered analog signal for digital sampling and outputs a digital signal from the output 20. The adder 24, the quantizer 26 and the output terminal 20 are all connected to a non-synchronous digital analog converter 28, which receives the digital signal and an original clock signal, and the asynchronous digital analog converter 28 first adjusts the original clock signal to a fixed pulse signal to eliminate the clock jitter of the original clock signal, and then convert the digital signal according to the fixed pulse signal into a feedback analog signal, and add the original analog signal in the adder 24 to form a conversion. The analog signal is received by loop filter 22.

The asynchronous digital analog converter 28 further includes a bias source 30, a fixed pulse width generator 32 and a digital analog conversion unit 34. The fixed pulse width generator 32 receives the original clock signal and adjusts it to a fixed pulse signal. To eliminate the clock jitter of the original clock signal. The bias source 30, the fixed pulse width generator 32, the adder 24, the output terminal 20 and the quantizer 26 are all connected to the digital analog conversion unit 34, which receives the fixed pulse signal to provide the electrical signal and the fixed signal according to the bias source 30. The pulse signal converts the digital signal into a feedback analog signal. When the bias source 30 is a current source, the feedback analog signal is a current analog signal, and when the bias source 30 is a voltage source, the analog signal is a voltage analog signal. .

The fixed pulse width generator 32 further includes a first and second delay unit 36, 38 and a logic combining unit 40. The first delay unit 36 receives the original clock signal to delay the first period of time and output a first delay. The second delay unit 38 also receives the original clock signal to output a second delayed clock signal after the second period of time longer than the first period. The first and second delay units 36 and 38 and the digital analog conversion unit 34 are connected to the logical combination unit 40, which receives the first and second delayed clock signals, and performs an operation to output a fixed pulse signal. The logic gate combination unit 40 is composed of a mutually exclusive (XOR) gate 42 and an AND gate 44. The mutual exclusion gate 42 is connected to the first and second delay units 36 and 38 to receive the first and second Delay the clock signal and perform a calculation to output a balanced clock signal. The gate 44 is connected to the first delay unit 36, the mutex 42 and the digital analog conversion unit 34, and receives the first delayed clock signal and the balanced clock signal to add them, and then outputs a fixed pulse without clock jitter. Signal, this signal can eliminate the noise effect of the digital output, and the whole conversion device is applied to the high-speed analog digital conversion technology.

Please refer to FIG. 3 at the same time. First, the operation of the fixed pulse width generator 32 will be described. The first and second delay units 36, 38 first receive the original clock signal to delay the first period Δt ₁ and the first period Δt ₂ , respectively, and output the first and second delayed clock signals, wherein the first period △ t _{2 is} longer than the first period Δt ₁ . Since the original clock signal has a pulse jitter phenomenon in both the rising and falling waveform segments, that is, the oblique line region in the figure, the first and second delayed clock signals have the same phenomenon. Then, the mutex gate 42 receives the first and second delayed clock signals, and after performing the operation, outputs the balanced clock signal to the AND gate 44, and the gate 44 receives the first delayed clock signal and balances it with the balance. The clock signals are added to output a fixed pulse signal to the digital analog conversion unit 34. Since the phenomenon that the mutual sluice gate 42 and the sluice gate 44 shake the clock during the signal addition process, the fixed pulse signal will form a stable waveform in the rising and falling sections of the signal, and the pulse width is Δt ₂ - Δt ₁ .

When the output terminal 20 has a digital signal output, the digital analog conversion unit 34 can receive the digital signal and the fixed pulse signal, and convert the digital signal into a feedback analog signal according to the electrical signal and the fixed pulse signal provided by the bias source 30. To be transmitted to the adder 24, the adder 24 receives the original analog signal to add the analog analog signal to form a conversion analog signal for reception by the loop filter 22. The loop filter 22 filters the conversion analog signal to output a filtered analog signal to the quantizer 26. Finally, the quantizer 26 digitally samples the filtered analog signal and outputs a stable and high resolution digital signal from the output terminal 20.

In summary, the present invention provides a fixed-pulse signal without clock jitter to replace the conventional clock signal, so as to avoid the influence of the noise of the digital output and achieve the high-resolution digital output.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally varied and modified. All should be included in the scope of the patent application of the present invention.

10‧‧‧ Loop Filter

12‧‧‧Quantifier

14‧‧‧Synchronous digital analog converter

16‧‧‧ Clock generation components

18‧‧‧ input

20‧‧‧ Output

22‧‧‧ Loop Filter

24‧‧‧Adder

26‧‧‧Quantifier

28‧‧‧Synchronous digital analog converter

30‧‧‧ bias source

32‧‧‧Fixed pulse width generator

34‧‧‧Digital Analog Conversion Unit

36‧‧‧First delay unit

38‧‧‧second delay unit

40‧‧‧Logical combination unit

42‧‧‧mutation

44‧‧‧ and gate

1 is a circuit block diagram of an analog digital conversion device of the prior art.

Figure 2 is a block diagram of the device of the present invention.

Figure 3 is a waveform diagram of the original clock signal, delayed clock signal and fixed pulse signal of the present invention.

18. . . Input

20. . . Output

twenty two. . . Loop filter

twenty four. . . Adder

26. . . Quantizer

28. . . Asynchronous digital analog converter

30. . . Bias source

32. . . Fixed pulse width generator

34. . . Digital analog conversion unit

36. . . First delay unit

38. . . Second delay unit

40. . . Logical combination unit

42. . . Mutually exclusive gate

44. . . Gate

Claims (7)

An analog-to-digital conversion device is connected between an input end and an output end, the input end receiving an original analog signal, the analog-to-digital conversion device comprising: a loop filter, which receives a conversion analog signal and filters the same a filter analog signal is output; a quantizer is connected to the loop filter and the output terminal, and receives the filter analog signal for digital sampling, and outputs a digital signal from the output terminal; a bias source; The delay unit and the second delay unit receive an original clock signal, and the first delay unit delays the first period of the original clock signal to output a first delayed clock signal, and the second delay unit delays After the second time period of the first time period, the original clock signal outputs a second delayed clock signal; a logic combination unit is connected to the first and second delay units, and receives the first and second delays a clock signal, and after performing an operation, outputting a fixed pulse signal to eliminate clock jitter of the original clock signal; and a digital analog conversion unit connecting the bias source, Combining the unit, the loop filter, the input end, the output end and the quantizer, and receiving the digital signal and the fixed pulse signal, according to the electrical signal provided by the bias source and the fixed pulse signal, The digital signal is converted into a feedback analog signal to form the conversion analog signal with the original analog signal for reception by the loop filter. The analog-to-digital conversion device of claim 1, wherein the loop filter is a continuous-time loop filter or a hybrid continuous-distribution Hybrid continuous discrete-time loop filter. The analog-to-digital conversion device of claim 1, wherein the quantizer is an amplitude quantizer. The analog digital conversion device of claim 1, wherein the feedback analog signal is a current analog signal when the bias source is a current source. The analog digital conversion device of claim 1, wherein the feedback analog signal is a voltage analog signal when the bias source is a voltage source. The analog digital conversion device of claim 1, wherein the logic gate combination unit further comprises: a mutual exclusion (XOR) gate connected to the first and second delay units to receive the first and second Delaying the clock signal, and performing an operation, outputting a balanced clock signal; and an AND gate connecting the first delay unit, the mutual repulsion and the digital analog conversion unit, and receiving the first delay The pulse signal and the balanced clock signal are added to output the fixed pulse signal. The analog-to-digital conversion device of claim 1, further comprising an adder connecting the input end, the loop filter and the asynchronous digital analog converter to receive the feedback analog signal and the original Analog signals are added and added to output the analog analog signal for reception by the loop filter.