TWI420311B - Set-based modular cache partitioning method - Google Patents

Description

Segmentation method of cache memory based on set sub-module

The invention relates to a method for segmenting a cache memory, in particular to a method for segmenting a cache memory based on a set sub-module based on a set sub-module.

At present, single-core processors are obviously unable to meet the operational requirements and applications of today's computer systems due to power and frequency limitations. Therefore, the development of multi-core processor technology with higher operational performance has gradually replaced the application of single-core processors. . However, because the multi-core processor of the computer system has the characteristics of cache memory sharing, how to properly and effectively segment the cache memory, so that the programs executed on each core can get the right amount of fast Taking memory and accommodating the contents of the program to improve access efficiency and reduce power consumption has clearly become the goal of the industry.

The existing dynamic memory segmentation methods mainly include three types: segmentation method based on combination degree, segmentation method based on set, and sharing mode. Many documents and patents have revealed a way of dividing memory based on the degree of integration, such as:

1. "Utility-based cache partitioning: a low-overhead, high-performance runtime mechanism to partition shared caches", published in the 39th IEEE/ACM Int'l Symp. On Microarchitecture seminar paper, pp. 423-432.

2. An adaptive shared/private NUCA cache partitioning scheme for chip multiprocessors, published on page 2 to 12 of the 13th Int’l Symp. on High Performance computer Architecture.

3. Published in the Journal of J. of Supercomputing, pages 2 to 12, "Dynamic partitioning of shared cache memory";

4. "An adaptive bloom filter cache partitioning scheme for multicore architectures" on pages 25 to 32 of Int’l Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008; and

5. The Republic of China Announcement No. I285810, "Distribution Method, Device, System, and Computer-Readable Recording Media Storing Cache Memory for Chip Multiprocessors".

The foregoing disclosure discloses a conventional dynamic cache memory segmentation based on the degree of integration. The structure thereof is shown in FIG. 1 , which divides a cache memory structure into a plurality of cache memory modules, and each module includes a number. Each cache memory set (set), and each cache memory set further contains a plurality of fixed number of cache line (way). When multiple programs are executed, the cache line of each cache module is divided into different programs according to the requirements of each program. Therefore, more cache lines need to be set, and the cache memory segmentation method is fast. It takes a lot of power to access all or more cache lines when accessing memory, and multiple programs of multi-core processors are easy to compete with the same cache memory module, resulting in additional access latency. , thereby reducing system performance.

In view of this, the segmentation-based dynamic cache memory segmentation method is proposed, because in the segmentation mode of the cache memory, the cache memory module has a lower degree of integration, and for multiple fast The access operation only needs to access the corresponding cache memory modules, so that the disadvantages of the above-described degree-based dynamic cache memory segmentation can be solved. About the collection-based dynamic cache memory segmentation method, such as the 2008 seminar published in 14th Int'l Symp. on High Performance computer Architecture, pp. 367-378 "Gaining insights into multicore cache partitioning: bridging the gap Between the simulation and real systems, which reveals that the cache block is evenly arranged in the allocated cache memory module, and each cache access operation is performed separately when the cache memory is re-segmented, thereby reducing the waiting time However, in the cache memory reconfiguration, the overall cache memory content movement is required, so that the power and time consumed during the movement are relatively generated, and when the cache memory access is performed, the division operation is required, that is, the division circuit is required. Setting, in contrast, will result in increased logic and computational complexity, and therefore more power and time.

In addition, the segmentation of cache memory for shared mode, as published in the 39th IEEE/ACM Int'l Symp. on Microarchitecture, pp. 433-442, "Molecular caches: a caching structure for dynamic creation of application -specific heterogeneous cache regions, which reveals that the memory blocks stored by the cache module are selected in a random distribution manner. When accessing, the average needs to search for a plurality of memory blocks that may be distributed, so more Search time and power consumption.

Also, as published in the 10th Int'l Symp. on High Performance computer Architecture, pp. 176-185, "Organizing the last line of defense before hitting the memory wall for CMPs", which reveals that the memory model will be cached. The group is assigned to one or more programs, and it is necessary to search for a cache memory module that may exist when performing a cache memory access, so that more search time and power consumption are also required.

Furthermore, as disclosed in the Republic of China Announcement No. I297832, "System Method for Non-Uniform Cache Memory in Multi-Core Processors", it discloses a method of distributing memory blocks in a cache mode in a far-to-near manner. The group can dynamically move the memory block according to the usage condition and adjust the distance between the memory block and the processor used. Therefore, the cache memory needs to search for multiple cache memory modules from near to far during access, so it is necessary to compare More time and power consumption.

In addition, the Republic of China Announcement No. I317065 "Method for Accessing Memory Data Accessed by Parallel Processors" invention patent also discloses that the memory access is performed by searching for the memory module from near to far. Therefore, it also requires more time and power consumption.

The main object of the present invention is to provide a method for segmenting cache memory based on a collection sub-module to reduce access latency, search time, and power consumption.

The second object of the present invention is to provide a method for segmenting cache memory based on a collection sub-module, which can reduce the reconfiguration action and further reduce the power and time required for reallocation.

Another object of the present invention is to provide a method for segmenting a cache memory based on a collection sub-module, which eliminates the waiting time for the program to perform cache memory access when reconfiguring the cache memory.

The method for segmenting the cache memory based on the set sub-module according to the present invention comprises the steps of: a program entity address corresponding step, corresponding to at least one program entity address corresponding to at least one of the plurality of virtual cache memory modules a virtual cache memory module corresponding step, using a virtual to physical cache memory module area number corresponding calculation and an area to global entity cache memory module correspondence table query for the plurality of virtual cache memory modules The content corresponds to a plurality of physical cache memory modules, wherein the selection of the number of allocations of the physical cache memory module and the setting of the correspondence table of the area to the global entity cache module are performed by a software algorithm in an operating system or A hardware algorithm is determined according to the hit rate of the program currently accessed by the cache access, and wherein the virtual to physical cache memory module area number corresponding to the calculation system includes steps: according to the number of selected physical cache memory modules P, to The formula calculates a k value; the plurality of virtual cache memory modules are sequentially numbered s _1N , N is 0 to u-1, where u is the number of virtual cache memory modules corresponding to a program, and the virtual The number of cached memory modules is 2, and the number of physical cache modules is sequentially numbered s _PN , N is 0 to v-1, where v is a program dynamically configured entity fast Taking the number of memory modules, each virtual cache memory module performs the remainder of the following equation with its number s _1N for 2 ^k : s _1N '= s _1N mod2 ^k ; the remainder of the determination is s _1N ' Whether it is less than P; performing the step of the area number s _{PN of the} physical cache memory module according to the judgment result, wherein if the remainder s _1N ' is smaller than P, the remainder s _1N ' is the corresponding cache mode of the entity The global number s _PN ' of the group, if the remainder s _1N ' is not less than P, the virtual cache memory module is further subjected to the operation of the remainder of the following equation: s _1N '= s _1N mod2 ^k-1 , remainder s _1N 'is the number corresponding to the region s _PN modules of the physical cache memory; and respond to the desired virtual cache memory module Taken from area number s _PN entity of the cache module; and a step of accessing the physical cache memory module, each line of the cache memory module virtual cache access, according to the speed corresponding to the entity The memory module is used to perform a cache access of a physical cache memory.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Referring to FIG. 2, a method for segmenting a cache memory based on a set sub-module according to a preferred embodiment of the present invention is disclosed. The method includes the steps of: a program entity address corresponding to step S1, and at least one program entity bit. The address corresponds to one of the plurality of virtual cache memory modules; a virtual cache memory module corresponding to step S2, using a virtual to physical cache memory module area number corresponding to calculate and an area to global entity cache memory module Corresponding table query corresponds to the content of the plurality of virtual cache memory modules to a plurality of physical cache memory modules, wherein the selection of the number of the physical cache memory module allocations and the setting of the correspondence table are performed by an operating system The software algorithm or a hardware algorithm is determined according to the hit rate of the program currently performing the cache access; and the access step of the entity cache memory module is to cache the virtual cache memory modules. Accessing, performing a cache access of a physical cache memory according to the corresponding physical cache memory module.

The so-called entity cache memory module area number is defined as: a program is assigned to a number of physical cache modules (the number is P), and 0~P-1 is performed for the entity cache modules. If they are numbered, they represent the physical cache memory module area number.

Referring to FIG. 3A, FIG. 3B and FIG. 3C, in the program entity address corresponding to step S1, each program segment has a program entity address, and multiple program segments can share the same virtual cache memory space. Each of the program entity addresses includes three address contents D1, D2, and D3, and the program segment can correspond to the virtual cache memory according to the two address contents D1 and D2 by using the process of FIG. 3B. When the physical address of the program needs to be shifted, the process of the virtual cache memory module address corresponding to the process of the 3C is used to map the individual or the whole block of one or more programs to the virtual fast. The same or different virtual cache memory modules in the memory are used to match the low usage rate and the complementary used blocks to the same virtual cache memory space, and the highly competitive program segments correspond to different virtual memories. Cache memory space to eliminate the effect of cache pollution caused by cache memory access competition.

Regarding the address correspondence in the same virtual cache memory space, the memory interleaving arrangement may be used for correspondence, or as shown in FIGS. 3A and 3C of the present invention, the plurality of blocks correspond to a virtual cache. The technique of shifting in the memory space to stagger other blocks corresponding to the same virtual cache space to avoid competing with each other when the memory access is cached.

Referring to FIG. 4, the program content D1 is used to provide an index data, and the virtual correspondence corresponds to the entity to obtain the global number of the corresponding physical cache memory module, and then the program contents D2 and D3 are used to The physical cache memory module performs cache access.

The main purpose is to allocate a certain number of physical cache memory modules according to dynamic needs in each virtual cache memory space, and provide a corresponding manner from virtual to physical cache memory modules. In this way, the software algorithm or the hardware algorithm in the operating system needs to adjust the physical cache memory capacity used by each program according to the dynamics of each program to obtain an improvement in the cache hit rate. Furthermore, a virtual cache memory space forms an address space integration unit, and then allocates the entity cache memory to each virtual cache memory space, which can be adjusted according to the fast hit rate and the total number of errors. The physical cache memory capacity, and programs that may compete with each other in the same address space can correspond to different entity cache memory modules without causing cache pollution.

The so-called physical cache memory module global number is defined as: an operating system or a hardware algorithm queries the actual location of the actual physical cache memory module by using the area to global entity cache memory module correspondence table. The real location is the global number of the actual physical cache memory module.

The method for segmenting the cache memory based on the set sub-module of the present invention will be described in detail as follows: Please refer to FIG. 5, which discloses that a physical address space is mapped to a virtual cache. The virtual cache then corresponds to a corresponding flow chart between physical caches.

The virtual address memory space corresponds to the virtual cache memory in a manner corresponding to a virtual cache memory, wherein the virtual cache memory has a plurality of virtual cache memory modules, and the virtual cache memory module a power of 2, the at least one program entity address of the program entity address space is allocated to a corresponding virtual cache memory module; and the area to the global entity cache memory module correspondence table As a result of the query, the data in the corresponding virtual cache memory module is correspondingly stored in a corresponding physical cache memory module in a physical cache memory, wherein the software calculation in the operating system The method or hardware algorithm determines the allocation quantity of the physical cache memory module according to the current program requirement, so the number of the allocated entity cache memory modules may be any power of 2 or any positive integer other than 2. The number of the physical cache memory modules is not greater than the number of the virtual cache memory modules. Under normal circumstances, due to the local adjustment calculation relationship, the number of allocations of the entity cache memory module is often not the power of 2.

The present invention records the dynamic cache segmentation performed by each entity cache module by using the correspondence table, so that each program can obtain an appropriate number of physical memory to promote the individual and overall cache hit ratio.

In order to clearly describe how to obtain the index value of the corresponding table by the operation of the memory address, and how to use the index value of the corresponding table to determine the corresponding implementation between each virtual cache memory module and each entity cache memory module For the manner, please refer to the sixth and seventh drawings of the present invention.

Figure 6 of the present invention discloses a method for calculating a virtual cache memory space in a module-based unit corresponding to an entity cache memory space, which requires only a fast low-power calculation. The method comprises the steps of: a power level value calculation step S21, based on the number P of the selected physical cache memory modules, The formula calculates the power level value k value; a step S22 of performing a remainder operation on each virtual cache memory module for 2 ^k , sequentially numbers the plurality of virtual cache memory modules to be cache accessed. s _1N is 0 to u-1 (ie, s ₁₀ , s ₁₁ , ..., s _1u-1 ), and the number of physical cache memory modules is sequentially numbered s _PN is 0 to v-1 (ie, s _P0 , s _P1 , ..., s _Pv-1 ), and each of the virtual cache memory modules performs the remainder of the following equation with its number s _1N for 2 ^k : s _1N '=s _1N mod2 ^k ; a determining step S23, determining whether the obtained remainder s _1N ' is less than P; performing an entity cache memory module area number s _PN according to the determination result corresponding to step S24, wherein if the remainder s _1N ' If it is less than P, a corresponding step is performed, that is, the remainder s _1N ' is the area code s _PN corresponding to the physical cache memory module, and if the remainder s _1N ' is not less than P, each virtual cache memory module is re- The operation step of taking the remainder of 2 ^k-1 power: s _1N '= s _1N mod2 ^k-1 , and then performing a corresponding step, that is, the remainder s _1N ' is the corresponding area number of the physical cache memory module s _PN ; and one In step S25, the area number s _PN of the physical cache memory module to be accessed by the virtual cache memory module is returned.

As described in the above step, by inputting the number of physical cache memory modules P allocated to the virtual cache memory space and the virtual cache memory module number s _{1N to be} queried, it can be replied through a simple and fast hardware calculation. The area code s _PN of the allocated physical cache memory module to be accessed. In the access step of the physical cache memory module, each of the virtual cache memory modules can perform cache access according to the area code s _{PN of} the corresponding physical cache memory module. Moreover, in the circuit implementation of FIG. 6, since the divider is not required, the corresponding operation between the virtual cache memory module and the physical cache memory module can be performed by a simple calculation circuit architecture.

Please refer to FIG. 7 , which can be used to illustrate the correspondence between the virtual cache memory space and the physical cache memory space by using the virtual to physical cache memory module area number corresponding calculation method in FIG. 6 . Assume that the virtual cache memory space has eight virtual cache memory modules, the number of which is the power of 2, and is sequentially numbered from 0 to 7. In addition, it is assumed that the software algorithm or a hardware in the operating system The number of the physical cache memory modules to be allocated by the algorithm is P, and the area number is 0~P-1, where P is any positive integer. Here, the memory module is cached by the entity. The number of groups P is 1 to 8 as an example, and the corresponding conditions of selecting eight different numbers of P items are listed.

Regarding how the virtual cache memory module in FIG. 7 corresponds to the corresponding manner of the physical cache memory module by using the calculation flow of FIG. 6, the following is an example: assume that the fifth entry in FIG. 7 is used for explanation. The number of physical cache modules in the entry is 5, which is between Therefore, the virtual cache memory module number s _1N is calculated for 2 ³ = 8 respectively, if the obtained remainder s _1N ' is less than 5 (in this example, the virtual cache memory module number If the remainder of s _1N =0~4 is less than 5), the remainder s _1N ' is the corresponding area number s _PN of the physical cache memory module, that is, the virtual cache memory module number s _1N =0~ 4 The corresponding physical cache memory module area number s _PN is 0~4.

However, if the obtained remainder s _1N ' is not less than P (in this example, the virtual cache module number s _1N = 5 to 7 respectively is 2 ³ = 8 and the remainder is not less than the remainder. 5), the virtual cache memory modules are further calculated by using the number and 2 ² = 4, and the remainder s _1N ' is obtained corresponding to the physical cache memory module. The area number s _PN , that is, the virtual cache memory module number s _1N = 5~7, the corresponding physical cache memory module area number s _PN is 1~3.

In summary, please refer to the 6th and 7th diagrams. When the physical cache memory module is allocated to the virtual cache memory space according to the dynamic requirements of the program, the virtual cache calculated by the program entity address can be calculated. The memory module number and the number of the cached memory modules of the allocated entity are used as reference values for calculating the virtual to physical cache memory module area number, and the allocated physical cache memory module area is obtained by the foregoing corresponding calculation method. The number is used, and the area number is used as the index value to perform the query of the area to the global entity cache module correspondence table shown in FIG. 8 , and the cache access of the corresponding entity cache memory module is performed.

Please refer to FIG. 8 again, which discloses a corresponding flow chart between the program entity address and the virtual to physical cache memory. The program entity address translates the virtual cache memory module number s _1N and then calculates The physical cache memory module area number s _{p is} used as the index value to query the global number of the physical cache memory module to be accessed on the area-to-global entity cache memory module correspondence table (c _i ,m _i ), and the area-to-global correspondence table is pre-stored by the software algorithm or the hardware algorithm in the operating system with the global number of the physical cache memory module sequentially allocated. This method can achieve two important characteristics. One is that the virtual cache memory module number s _1N can be mapped to the physical cache memory module area number s _PN , so that the partial use of each executable program can be reconfigured. Entity cache memory size. The second is that when the physical cache memory module is reconfigured, the reconfiguration of the memory module can be performed with a minimum amount of physical cache memory, and the movement of the cache line set involved is performed, so the time and power consumption required for reconfiguration can be Control to a minimum extent.

Please refer to FIG. 8 again, wherein the conversion from the program entity address to the virtual cache memory module can refer to the corresponding manners of the 3A, 3B, and 3C diagrams. In addition, the corresponding manner of the virtual cache memory module to the physical cache memory module and the corresponding hardware structure of the corresponding table are as follows:

Referring to FIG. 9, the virtual cache memory has a plurality of virtual cache modules, which are numbered 0-7, and the virtual cache module is used to correspond to a translation program entity address; The memory has a plurality of physical cache memory clusters c0~c3, and each of the entity cache memory clusters c0~c3 includes four entity cache memory modules m0~m3.

Please refer to FIG. 9 again, wherein the virtual cache memory and the physical cache memory are matched with the virtual to physical cache memory module area number corresponding calculation and the area to global entity cache memory module. Correspondence table corresponds. The corresponding calculation is performed as shown in Figures 6 and 7; and the region-to-global entity cache memory module correspondence table is pre-stored in the hardware, and the software algorithm or hardware algorithm in the operating system is based on the current program. The hit rate and the number of misses of the cache access determine the number of physical cache modules that need to be allocated. As shown in FIG. 9, the entity cache memory shares a non-second power number of the physical cache memory module. Performing the allocation operation (here, the number of the allocated entity cache memory modules is 5, and is sequentially indexed to 0 to 4); wherein the entity cache memory module with the index value of 0 in the corresponding table is The physical cache memory module m0 is configured to the entity cache memory cluster c0. Thus, the data of the virtual cache memory module number 0 can be accessed by the path cache to the entity cache of the entity cache memory cluster c0. The memory module m0; since the number of the physical cache memory modules allocated is 5, referring to the fifth entry in FIG. 7, the data in the two virtual cache memory modules numbered 1 and 5 can be Path cache access to the entity cache memory cluster c0 entity fast Memory module M1; remaining virtual cache module can refer to the fifth entry of FIG 7 correspond to the configuration.

Furthermore, the software algorithm or the hardware algorithm in the operating system is based on whether the cache access currently processed by each of the programs P1, P2, etc. has a predetermined requirement that meets its hit rate, and if so, the entity is maintained fast. The allocated quantity of the memory module is taken; if not, the allocated quantity of the physical cache memory module is reconfigured. As shown in FIG. 10, it is assumed that the cache access currently processed by the program P1 cannot meet the predetermined requirement of the hit rate, and the program P2 is determined that the cache hit rate is too high, and one entity that can be allocated by P2 can be assigned. The cache memory module is reconfigured to the cache reconfiguration process used by P1.

Please refer to FIG. 11 , which discloses that the address scanning, reconfiguration, and the reconfiguration operation between the physical cache memory modules are performed by using the physical cache memory module to achieve, for example, Figure 10 shows how the target of the cache reconfiguration is operated. By using the method of moving the cache line, the reconfiguration operation of the re-configured physical cache memory module is gradually cleared and moved into the cache line, and the control of the scan can be achieved by a hardware counter. In the process of scanning the mobile cache line set, for the reconfigured physical cache memory module, the scanned cache line set belongs to the virtual cache memory space after the reconfiguration is completed, and the entity in this case The cache access of the cache memory module should use the new address corresponding setting; and the cache line set that has not been scanned belongs to the original virtual cache memory space, therefore, the physical cache memory module of this case The cache access should use the original address corresponding settings.

Referring to FIG. 12, it is disclosed in FIG. 8 that a second judging step is added. One judging step is to add a reconfiguration flag, which is a software algorithm or hardware in the operating system. The algorithm controls to determine whether the physical cache memory module is being reconfigured, that is, the cache access of the program P1 that obtains the physical cache memory module is to be a physical memory module that is being reconfigured. Group, or to access the unreconfigured physical cache module, and decide to release the cache access of the entity cache module P2 to the entity being reconfigured Taking a memory module or moving to another physical cache memory module for accessing operations; another determining step is to compare whether the aggregate address accessed in the physical cache memory module is not greater than the cache line set The scan address is determined to determine whether the entity cache memory module should currently access the new corresponding entity cache memory address or the original corresponding entity cache memory address.

Referring to FIG. 12 again, when the software algorithm or the hardware algorithm in the operating system sets the reconfiguration flag to 1, it means that the physical cache memory module needs to be reconfigured, if a virtual The cache memory module can increase the allocation of n (or decrease n) physical cache memory modules at one time, and can simultaneously calculate the physical cache memory module area number on the corresponding table by using P and P+n (or Pn). s _PN and s _PN ', and then use the physical address of the physical cache memory module to compare with the scan address of the cache line set, if the access address of the entity cache module is not greater than the cache address The scan address of the line set, the s _PN 'select corresponds to the reconfigured physical cache memory module; otherwise, the s _PN selects the unreconfigured physical cache memory module for cache memory access.

With the above reconfiguration and cache memory address mapping method, the cache memory access performed on the virtual cache memory module being reconfigured can correctly correspond to the relevant entity cache memory module. Access. There are two characteristics: one is that after the setting of the relevant cache memory reconfiguration, the processor can perform the step-by-step reconfiguration work in the background when the processor does not use the cache memory, and involves reconfiguring the entity cache mode. The execution program of the group can continue to execute without waiting for its reconfiguration to complete, which helps the speed of execution of each program. Another feature is that the cache access at any time requires only one physical cache access, which is beneficial to reduce power and reduce competition of the cache module, which can also lead to improved performance.

In summary, the present invention overcomes the problem of the efficiency of the conventional method of segmenting the cache memory based on the cluster module by the operation of the above steps. Therefore, the present invention can further reduce the memory compared with the above-mentioned conventional techniques. Take the time of waiting and searching, and reduce the power consumption of the circuit when accessing.

While the invention has been described in connection with the preferred embodiments described above, it is not intended to limit the scope of the invention. The technical scope of the invention is protected, and therefore the scope of the invention is defined by the scope of the appended claims.

Figure 1: Schematic diagram of a conventional dynamic cache memory partitioning structure based on the degree of integration.

2 is a flow chart of a method for segmenting a cache memory based on a set sub-module according to a preferred embodiment of the present invention.

Figure 3A: Schematic diagram of a multi-program segment corresponding to a virtual cache memory space.

Figure 3B: Schematic diagram of a program entity address corresponding to a virtual cache memory space.

Figure 3C: Schematic diagram of displacement of a program's program entity address to another virtual cache memory space.

Figure 4 is a schematic diagram of a program entity address corresponding to a physical cache memory module by a virtual correspondence and entity correspondence processing.

Figure 5 is a diagram showing the correspondence between a program entity address space, a virtual cache memory and an entity cache memory in a preferred embodiment of the present invention.

Figure 6 is a flow chart showing the operation of the virtual cache memory space to the allocated entity cache memory space in the preferred embodiment of the present invention.

Figure 7: When the virtual cache memory space has eight virtual cache memory modules, the operation flow of Figure 6 corresponds to the number of eight different physical cache memory modules.

Figure 8: The program entity address of the preferred embodiment of the present invention corresponds to the virtual cache memory module according to the operation flow of Figure 3, and then the area number of the physical cache memory module is calculated according to the sixth figure, and then The area number query area to the global entity cache memory module correspondence table corresponds to the entity cache memory module global number, and the flow is shown in this diagram.

Figure 9: Correspondence calculation between a virtual cache memory module and a physical cache memory module according to a preferred embodiment of the present invention by a virtual to physical cache memory module area number and a software algorithm in an operating system Or a corresponding diagram of a region-to-global entity cache memory module correspondence table governed by the hardware algorithm.

Figure 10: Schematic diagram of reconfiguration between two programs.

Figure 11: Schematic diagram of re-configuration of the physical cache memory modules for scanning, reconfiguring, and retrieving the addresses of the memory modules via the physical cache.

Figure 12 is a schematic diagram of a complete entity cache memory address conversion process for adding a reconfiguration flag and a scan address of a cache line set in Fig. 8.

Claims (10)

A method for segmenting a cache memory based on a set of modules, comprising the steps of: a program entity address corresponding step, corresponding to at least one program entity address corresponding to at least one of the plurality of virtual cache memory modules; Corresponding to the memory module corresponding step, using a virtual to physical cache memory module area number corresponding calculation and an area to global entity cache memory module correspondence table query to correspond to the contents of the plurality of virtual cache memory modules a plurality of physical cache memory modules, wherein the selection of the number of allocations of the physical cache memory module and the setting of the correspondence table of the area to the global entity cache module are performed by a software algorithm or a hardware in an operating system. The algorithm is determined according to the hit rate of the program currently accessed by the cache access, and wherein the virtual to physical cache memory module area number corresponding to the calculation system includes the steps of: according to the number P of the selected physical cache memory modules, The formula calculates a k value; the plurality of virtual cache memory modules are sequentially numbered s _1N , N is 0 to u-1, where u is the number of virtual cache memory modules corresponding to a program, and the virtual The number of cached memory modules is 2, and the number of physical cache modules is sequentially numbered s _PN , N is 0 to v-1, where v is a program dynamically configured entity fast Taking the number of memory modules, each virtual cache memory module performs the remainder of the following equation with its number s _1N for 2 ^k : s _1N '= s _1N mod2 ^k ; the remainder of the determination is s _1N ' Whether it is less than P; performing the step of the area number s _{PN of the} physical cache memory module according to the judgment result, wherein if the remainder s _1N ' is smaller than P, the remainder s _1N ' is the corresponding cache mode of the entity The global number s _{PN of the group} , if the remainder s _1N 'is not less than P, the virtual cache memory module is further subjected to the operation of the remainder of the following equation: s _1N '=s _1N mod2 ^k-1 , The remainder s _1N ' is the area number s _PN corresponding to the physical cache memory module; and replies to the virtual cache memory module Accessing the physical cache memory module area number s _PN ; and accessing the physical cache memory module, the cache access of each virtual cache memory module, according to the corresponding entity The memory module is cached for quick access of a physical cache memory. The method for segmenting the cache memory based on the aggregate module according to the first aspect of the patent application, wherein the number of the physical cache memory module is not greater than the number of the virtual cache memory module, and the entity cache memory The number of modules is any integer. According to the segmentation method of the cache module based on the aggregate module according to Item 1 of the patent application scope, in the step corresponding to the physical address of the program segment, the low usage rate and the complementary used program segments are corresponding to the same one. The virtual cache memory space has highly competitive blocks corresponding to different virtual cache memories. According to the method for segmenting the cache memory based on the aggregate module according to Item 3 of the patent application scope, wherein the addresses in the same virtual cache memory space correspond to each other, the memory interleave arrangement may be used for correspondence, or A technique in which a plurality of blocks correspond to displacements in a virtual cache memory space to stagger other blocks corresponding to the same virtual cache space. According to the method for segmenting the cache memory based on the aggregate module according to the first aspect of the patent application, in the corresponding step of the virtual cache memory space, the physical cache memory space may be corresponding to the use sharing non-two times. A square number of physical cache memory modules for cache access operations. According to the method for segmenting the cache memory based on the aggregate module according to Item 1 of the patent application scope, wherein the software algorithm in the operating system conforms to the hit rate and the number of errors according to the currently processed cache access. The relative requirement, if any, maintains the allocated number of the physical cache memory module, and if not, reconfigures the allocation of the physical cache memory module by the software algorithm or the hardware algorithm in the operating system Quantity. The method for segmenting cache memory based on the aggregate module according to item 6 of the patent application scope, wherein in the reconfiguration process, the reconfiguration of the physical cache memory module is performed by using the moving cache line set operation. According to the method for segmenting the cache memory based on the aggregate module according to Item 7 of the patent application scope, the method for moving the cache line to gradually clear and reconfigure the physical cache memory module The operation is controlled by a hardware counter to achieve scanning. According to the method for segmenting the cache memory based on the aggregate module according to Item 7 of the patent application scope, in the process of scanning the moving cache line set, for the reconfigured physical cache memory module, The scanned cache line collection, the cache access of the physical cache memory module uses the corresponding corresponding physical cache memory address corresponding setting, and the cache line set that has not been scanned, the entity cache memory The cache access of the module uses the corresponding corresponding physical cache memory address corresponding setting. According to the sixth aspect of the patent application, the method for segmenting the cache memory based on the aggregate module, wherein the reconfiguration process includes a second determining step, and a determining step is to add a reconfiguration flag, The reconfiguration flag is controlled by the software algorithm or the hardware algorithm in the operating system to determine whether the physical cache module is being reconfigured; another determining step is to compare the entity cache mode. Whether the set address of the intra-group access is not greater than the scan address of the cache line set, so as to determine that the entity cache memory module should currently access the new corresponding entity cache memory address or the original corresponding entity cache memory. Address.