TWI418018B - Electronic device and fabrication method thereof and memory device - Google Patents

Description

Electronic device, manufacturing method thereof, and memory device

The present invention relates to an electronic device and a method of fabricating the same, and more particularly to a bit line of a dynamic random access memory cell and a method of fabricating the same.

Dynamic Random Access Memory (DRAM) belongs to a kind of volatile memory. The main principle of operation is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0 to store data. To achieve high density requirements, the most effective method at present is to reduce the size of the wafer by reducing the manufacturing process and using cell design techniques. Another way to reduce the size of the wafer is to implement a more efficient array architecture. After several generations of development, storage techniques often become a limitation of a certain cell layout. Every improvement in cell size requires a lot of work to reduce etching. The smallest size.

Therefore, there is a need for a dynamic random access memory having a novel structure and a method of fabricating the same.

In view of the above, an embodiment of the present invention provides an electronic device including a substrate; a trench formed in the substrate; a diffusion region formed in a portion of the substrate adjacent to the sidewall of the trench; a conductive structure Provided in the trench, comprising a conductive layer covering the bottom surface of the trench, the conductive layer having a recess to expose the diffusion region from the recess; a conductive plug filling the recess and covering a sidewall of the diffusion region, wherein a barrier layer is disposed between the conductive plug and the conductive layer.

Another embodiment of the present invention provides a memory device including a substrate; at least one vertical transistor formed in the substrate and having a vertical sidewall; at least one word line formed along the first direction In the substrate, the word line is disposed on the vertical sidewall of the pair of vertical transistors; at least one bit line is formed in at least one of the substrates in a second direction different from the first direction, And being located below the pair of vertical transistors, and electrically contacting a drain region of the vertical transistor by a diffusion region formed in a portion of the substrate adjacent to the sidewall of the trench, wherein the bit line comprises a conductive a layer covering the bottom surface of the trench, the conductive layer having a recess to expose the diffusion region from the recess; a conductive plug filling the recess and covering a sidewall of the diffusion region, wherein the conductive plug A barrier layer is disposed between the conductive layer and the conductive layer.

Still another embodiment of the present invention provides a method of fabricating an electronic device, including providing a substrate; forming a trench in the substrate; forming a conductive layer in the trench to cover a bottom surface and a portion of a side surface of the trench The conductive layer has a recess adjacent to the sidewall of the trench; a diffusion region is formed in the portion of the substrate adjacent to the recess; a barrier layer is formed in the trench to cover the conductive layer; A conductive plug is formed in the recess to fill the sidewall of the diffusion region.

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

1 is a perspective view showing an electronic device 600 according to an embodiment of the present invention. In an embodiment of the invention, the electronic device 600 can be, for example, a memory device, particularly a dynamic random access memory having a cell size of 4F ² (where F is the minimum lithography process size, or cell size). DRAM cell 600. As shown in FIG. 1, a vertical transistor 300 of the above-described dynamic random access memory cell 600, for example, a conductive structure 500 of a bit line (BL) 500, and a word line (word line, WL) 308 are all disposed in a substrate 200. As shown in FIG. 1, the electronic device 600 includes a substrate 200. A vertical transistor 300 is formed in the substrate 200. The vertical transistor 300 has a vertically stacked lower layer drain region 314, an intermediate layer channel region 316, and an upper layer source region 318. Additionally, vertical transistor 300 has at least one vertical sidewall 302. A word line 308 is formed in the substrate 200 along a first direction 322, wherein the word line 308 is disposed on the vertical sidewall 302 of the vertical transistor 300 and serves as a gate of the vertical transistor 300. An insulating layer 306 is disposed between the word line 308 and the vertical transistor 300 to serve as a gate insulating layer of the vertical transistor 300. As shown in FIG. 1 , the electronic device 600 further includes a bit line 500 formed in a trench 202 in the substrate 200 along a second direction 320 different from the first direction 322 and located in the vertical transistor 300 . Bottom, and electrically contacting the drain region 314 of the pair of vertical transistors 300 by a diffusion region 230 formed in a portion of the substrate 200 adjacent to the sidewall of the trench 202. In addition, the electronic device 600 further includes a capacitor 312 electrically contacting the source region 318 of the vertical transistor 300.

2a-2e are cross-sectional views taken along line A-A' of FIG. 1 and show conductive structures 500a-500e of, for example, bit lines of an electronic device according to various embodiments of the present invention (also referred to as bit lines 500a~). Sectional view of 500e). Further, the 2a to 2e maps further show the diffusion regions 230 adjacent to the bit lines 500a to 500e. As shown in FIG. 2a, the bit line 500a according to an embodiment of the present invention includes a conductive layer 214 covering the bottom surface of the trench 202. The conductive layer 214 has a recess 247 to expose the diffusion region 230 from the recess 247. The conductive plug 220a is filled with the recess 247 and covers the sidewall of the diffusion region 230. A barrier layer 218 is disposed between the conductive plug 220a and the conductive layer 214. The conductive plug 220a is made of tungsten. As shown in FIG. 2b, the bit line 500b of another embodiment of the present invention differs from the bit line 500a in that the bit line 500b further includes a germanide layer 232 formed in the trench 202. The sidewalls covered by the insulating blanket 208 are adjacent to the diffusion region 230. As shown in FIG. 2c, in another embodiment of the present invention, the bit line 500c is different from the bit line 500a. The bit line 500c further includes a diffusion source layer 228 and a sidewall formed on the diffusion source layer 228. A germanide layer 232 is formed, wherein the diffusion source layer 228 is formed on sidewalls of the trench 202 that are not covered by the insulating pad layer 208 and between the germanide layer 232 and the diffusion region 230. As shown in FIG. 2d, the bit line 500d of still another embodiment of the present invention differs from the bit line 500a in that the material of the conductive plug 220a of the bit line 500d is polysilicon. As shown in FIG. 2e, in another embodiment of the present invention, the bit line 500e is different from the bit line 500a. The conductive plug 220a of the bit line 500d is made of polysilicon, and the bit line 500b. A germanide layer 232 is further formed on the sidewall of trench 202 that is not covered by insulating spacer 208 and is adjacent to diffusion region 230.

3 to 10 are schematic cross-sectional views showing a method of manufacturing the conductive structure 500a of the electronic device 600 according to an embodiment of the present invention as shown in FIG. 2a, particularly showing the bit line 500a of the dynamic random access memory cell. Manufacturing method. As shown in FIG. 3, first, a substrate 200 is provided. In an embodiment of the invention, the substrate 200 can be a germanium substrate. In other embodiments, silicon germanium (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI), Or other commonly used semiconductor substrates are used as the substrate 200. The substrate 200 can be implanted with a p-type or n-type dopant to change its conductivity type for design needs. In an embodiment of the invention, the substrate 200 can be implanted with a p-type dopant.

Then, a patterned hard mask layer 201 is formed on the substrate 200 by a deposition and patterning process, and the formation position of the trenches 202 is defined. In an embodiment of the invention, the patterned hard mask layer 201 may include a stacked structure formed of a lower layer of a hafnium oxide pad layer 201a and an upper layer of a tantalum nitride layer 201b. Then, the patterned hard mask layer 201 can be used as an etch hard mask layer to perform an anisotropic etching process to remove a portion of the substrate 200 that is not covered by the patterned hard mask layer 201. A trench 202 is formed in the substrate 200.

Thereafter, a deposition method such as a chemical vapor deposition (CVD) method, a low pressure chemical vapor deposition (LPCVD) method, or a high temperature oxidation deposition (HTP) method may be used to form a conformance on the sidewall 206 and the bottom surface 204 of the trench 202. Insulating mat 208. In an embodiment of the invention, the insulating pad layer 208 may include an oxide layer, a nitride layer, or a combination thereof. In this embodiment, the insulating underlayer 208 can be a tetraethyl orthosilicate layer of TEOS oxide.

Next, referring to FIG. 4, a barrier layer 212 may be formed in the trench 202 by the deposition method of atomic layer deposition (ALD), and the insulating pad layer 208 may be covered. In an embodiment of the invention, the barrier layer 212 may comprise titanium, titanium nitride, or a combination thereof. In this embodiment, the barrier layer 212 may be a stacked structure composed of titanium and titanium nitride. Then, a conductive material 211 is formed in a comprehensive manner by a chemical vapor deposition (CVD) deposition method, and the trench 202 is filled. In an embodiment of the invention, the electrically conductive material 211 may comprise a metal such as tungsten.

Thereafter, referring to FIG. 5, the conductive material 211 above the substrate 200 and partially located in the trench 202 may be removed by an etching back process, wherein the top surface of the conductive material 211 is lower than the surface of the substrate 200.

Next, referring to FIG. 6, a first dielectric layer 240 may be formed in the trench 202 by a deposition method using atomic layer deposition (ALD), and the conductive material 211 may be covered. In an embodiment of the invention, the first dielectric layer 240 may include an oxide layer or a nitride layer. In this embodiment, the first dielectric layer 240 lining the sidewalls of the trench 202 may be a high-k dielectric layer such as aluminum oxide (Al ₂ O ₃ ) (high dielectric constant refers to The electrical constant is greater than the dielectric constant of the germanium dioxide (referred to as 4.2), which has a better density. Therefore, when a doped region is formed in the substrate 200 adjacent to the sidewall of the trench 202 by subsequent vapor phase doping, The dopant gas is prevented from diffusing into other undesired regions, and the subsequent etching process can be facilitated as etching the hard mask without damaging the conductive material 211 located thereunder. In an embodiment of the invention, after the first dielectric layer 240 is formed, an annealing process may be performed to make the structure of the first dielectric layer 240 more dense. Then, a second dielectric layer 242 is formed in the trench 202 by the deposition method of the chemical vapor deposition (CVD) method, and covers the first dielectric layer 240. In an embodiment of the invention, the second dielectric layer 242 and the first dielectric layer 240 are made of different materials, and the second dielectric layer 242 is, for example, undoped amorphous silicon.

Then, referring to FIG. 7, the second dielectric layer 242 can be subjected to an ion implantation step 262 in one direction (ie, the direction of the arrow of the symbol 262). As shown in Fig. 7, since the direction of the ion implantation step 262 (i.e., the direction of the arrow of the symbol 262) has an angle a with the surface of the substrate 200, the value may be determined by the position or size of the subsequent diffusion region, for example, It is between 10° and 80°, and the formation position or size of the above diffusion region can be determined by means of device simulation. Therefore, the ion implantation step 262 can form a doped region 242a and an undoped region 242b in the second dielectric layer 242. In an embodiment of the invention, the dopant of ion implantation step 262 can be boron difluoride (BF ₂ ).

Next, referring to FIG. 8, a second wet etching process may be performed on the second dielectric layer 242 to remove portions of the doped region 242a and the undoped region 242b until a portion of the first dielectric layer 240 is exposed. During the wet etching process, the doping region 242a having the dopant as shown in FIG. 7 may have an etching rate lower than that of the non-doping region 242b having no dopant, and the two have an etching selectivity ratio with each other, so when non-doped When the impurity region 242b is completely removed, a portion of the doped region 242a remains.

Then, the residual doping region 242a can be used as an etch hard mask layer, and one of the non-isotropic etching processes such as dry etching can be performed to remove the first dielectric layer 240 covered by the undoped region 242a to form a hard mask. Cover structure 243. In an embodiment of the invention, since the doped region 242a formed by the second dielectric layer 242 and the first dielectric layer 240 are made of different materials, for example, the first dielectric layer 240 is aluminum oxide (Al ₂ O _{3 ).} The doped region 242a is polysilicon, and therefore, an appropriate etchant may be selected to provide the first dielectric layer 240 with a higher etch rate (with a good etch selectivity) than the doped region 242a. After the non-isotropic etching process, a hard mask structure 243 is formed which has an opening 246 and exposes a portion of the conductive material 211. In one embodiment of the invention, the location and size of the opening 246 of the hard mask structure 243 may determine the location or size of the subsequent formation of the diffusion region.

Thereafter, the hard mask structure 243 is used as an etch hard mask layer, and an anisotropic etching process such as dry etching is performed to remove a portion of the conductive material 211 and the barrier layer 212 exposed from the opening 246 to form Conductive layer 214 of recess 247. The conductive layer 214 having the recess 247 described above can define the formation location of the diffusion region 230 in a subsequent process.

Then, using the hard mask structure 243 and the conductive layer 214 as an etch hard mask layer, an isotropic etching process such as wet etching is performed to remove a portion of the insulating underlayer 208 exposed from the recess 247 to expose the trench. A portion of the side wall 226 of the slot 202. In an embodiment of the present invention, since the hard mask structure 243, the conductive layer 214 and the insulating pad layer 208 are respectively made of different materials, for example, the hard mask structure 243 is a stack of aluminum oxide (Al ₂ O ₃ ) and polycrystalline germanium. The layer structure, the conductive layer 214 is a metal such as tungsten, and the insulating pad layer 208 is an oxide. Therefore, a suitable etchant may be selected to make the insulating pad layer 208 have a higher hardness of the hard mask structure 243 and the conductive layer 214. Etch rate (with good etch selectivity ratio). After the isotropic etch process, portions of sidewalls 226 of trench 210 are exposed.

Then, a diffusion region 230 is formed in a portion of the substrate 200 adjacent to the recess 247. The dopant gas can be injected into the adjacent portion of the substrate 200 from the exposed sidewalls 226 of the trench 202 by gas phase doping to form the diffusion region 230. In an embodiment of the invention, the gas phase doping method may include high temperature rapid gas phase doping (RVD), room temperature gas phase doping, gas immersion laser doping (GILD), and the like. In an embodiment of the invention, the diffusion region 230 can serve as a diffusion junction of the bit line and the drain of the vertical transistor. In an embodiment in which the conductivity type of the substrate 200 is a p-type, the conductivity type of the diffusion region 230 may be an n-type. The conductivity type of the diffusion region 230 depends on the conductivity type of the gas dopant, but is not limited to the embodiment. In an embodiment of the present invention, the first dielectric layer 240, such as aluminum oxide (Al ₂ O ₃ ), and the conductive layer 214 in the hard mask structure 243 can be used as a barrier layer for performing a gas phase doping process, avoiding The dopant gas diffuses from the sidewalls of the trenches 202 covered by the first dielectric layer 240 and the conductive layer 214 into unwanted regions of the substrate 200 to affect the performance of the bit lines.

Then, referring to Fig. 9, the hard mask structure 243 as shown in Fig. 8 can be removed by wet etching. Next, a pre-cleaning step can be performed to remove, for example, native oxide on sidewall 226 of trench 202. Thereafter, a barrier layer 218 can be formed in the trench 202 by a deposition method using atomic layer deposition (ALD), and cover the sidewalls of the insulating pad layer 208, the conductive layer 214, and the diffusion region 230. In an embodiment of the invention, the barrier layer 218 can comprise titanium, titanium nitride, or a combination thereof. In the present embodiment, the barrier layer 218 may be a stacked structure composed of titanium and titanium nitride. Then, a conductive material 220 can be formed in a comprehensive manner by a chemical vapor deposition (CVD) deposition method and filled in the trenches 202. In the present embodiment, the conductive material 220 may include a metal such as tungsten. As shown in FIG. 9, the conductive material 220 fills the recess 247 and covers the sidewall of the diffusion region 230.

Thereafter, referring to FIG. 10, the conductive material 220 above the substrate 200 and partially located in the trench 202 may be removed by an etching back process to form a conductive plug 220a, wherein the top surface of the conductive plug 220a It is lower than the surface of the substrate 200. Thereafter, a capping layer 258 can be formed in trench 202 and covered by conductive plug 220a using, for example, chemical vapor deposition (CVD) followed by, for example, an etching back process. In an embodiment of the invention, the material of the cover layer 258 may be, for example, an insulating material of cerium oxide. Further, through a subsequent planarization process such as chemical mechanical polishing (CMP), a conductive structure 500a according to an embodiment of the present invention as shown in Fig. 2a is formed.

The conductive structure 500a of an embodiment of the present invention, as shown in FIG. 2a, is formed in a self-aligned manner by forming a plurality of layers of hard mask structures having different etching options than each other in a self-aligned manner to form Conductive layer 214 of recess 247. The formation position of the diffusion region 230 is defined by a subsequent etching process. Moreover, the diffusion region 230 is directly electrically contacted to the conductive plug by a barrier layer such as a metal material, and the interface factor can be prevented from affecting the conductive property of the bit line. In addition, the hard mask structure may include a high dielectric constant first dielectric layer 240, such as aluminum oxide (Al ₂ O ₃ ), which has a preferred density and thus can be used as a vapor phase dopant for forming a diffusion region. The barrier layer of the miscellaneous process prevents the dopant gas from diffusing from the sidewalls of the trench 202 covered by the first dielectric layer 240 into the undesired regions of the substrate 200 to affect the performance of the bit line.

11 is a cross-sectional view showing a method of fabricating the conductive structure 500b of the electronic device 600 according to another embodiment of the present invention as shown in FIG. 2b, which differs from the conductive structure 500a in that the conductive structure 500b further includes a covered diffusion region. For the vaporization layer 232 of the side wall of the 230, if the components in the above-mentioned drawings have the same or similar parts as those shown in the first to the tenth drawings, reference may be made to the above related description, and the description thereof will not be repeated. Referring to FIG. 11 , after the diffusion region 230 is formed and the hard mask structure 243 as shown in FIG. 8 is removed, a deuteration process is performed to form a germanide layer 232 on the sidewall 226 of the trench 202 and covered. The sidewall of the diffusion region 230. In an embodiment of the invention, the germanide layer 232 can include a titanium germanide or cobalt germanide to reduce the electrical resistance between the diffusion region 230 and the subsequently formed conductive plug 220a. Further, through a subsequent planarization process such as chemical mechanical polishing (CMP), a conductive structure 500b according to an embodiment of the present invention as shown in Fig. 2b is formed.

12 to 13 are schematic cross-sectional views showing a method of manufacturing the conductive structure 500c of the electronic device 600 according to still another embodiment of the present invention as shown in Fig. 2c, the difference from the conductive structure 500a being the diffusion of the conductive structure 500c. The region 230 is formed by diffusion diffusion of the diffusion source layer 228 formed on the exposed sidewall 226 of the trench 202. If each element in the above figure has the same or similar portion as shown in FIGS. 1-11, Please refer to the previous related description, and no repeated explanation is given here.

Referring to FIG. 12, a portion of the insulating underlayer 208 exposed from the recess 247 may be removed after the step of exposing a portion of the sidewall 226 of the trench 202 as illustrated in FIG. A diffusion source layer 228 is formed on the exposed sidewalls 226 of the trench 202 by a thin film deposition method such as chemical vapor deposition (CVD) and a subsequent etch back step, and the addition formed by the second dielectric layer 242 is removed. Miscellaneous area 242a. In an embodiment of the invention, the diffusion source layer 228 may be a conductive layer doped with a polysilicon layer, such as an arsenic doped poly layer (As-doped poly). Then, the dopant of the diffusion source layer 228 can be diffused into the adjacent substrate 200 by, for example, an annealing process to form a diffusion region 230 in a portion of the substrate 200 adjacent to the diffusion source layer 228.

Then, referring to FIG. 13, the first dielectric layer 240 as shown in FIG. 12 can be removed by wet etching. Thereafter, a deuteration process can be performed to form a germanide layer 232 in the trench 202 and to cover the sidewalls of the diffusion source layer 228. In an embodiment of the invention, the germanide layer 232 can include a titanium germanide or cobalt germanide to reduce the electrical resistance between the diffusion source layer 228 and the subsequently formed conductive plug 220a. Further, through a subsequent planarization process such as chemical mechanical polishing (CMP), a conductive structure 500c according to an embodiment of the present invention as shown in Fig. 2c is formed.

Figure 14 is a cross-sectional view showing a method of fabricating the conductive structure 500d of the electronic device 600 according to still another embodiment of the present invention as shown in Fig. 2d, which is different from the conductive structure 500a as a conductive plug of the conductive structure 500d. The material is a doped poly. If the components in the above figures have the same or similar parts as those shown in FIGS. 1 to 13, reference may be made to the above related description, and the description thereof will not be repeated. Referring to FIG. 14, after the diffusion region 230 is formed and the barrier layer 218 is formed by a vapor phase diffusion method, a thin film deposition method such as chemical vapor deposition (CVD) and a subsequent etch back step are used to form a material doped. Conductive plug 220b of the heteropolysilicon. In this embodiment, the conductive plug 220b may be, for example, an arsenic doped poly-layer (As-doped poly). Further, through a subsequent planarization process such as chemical mechanical polishing (CMP), a conductive structure 500d according to an embodiment of the present invention as shown in Fig. 2d is formed.

Figure 15 is a cross-sectional view showing a method of fabricating the conductive structure 500e of the electronic device 600 according to still another embodiment of the present invention, as shown in Fig. 2e, which differs from the conductive structure 500a in that the conductive structure 500e further includes a cover diffusion. The germanide layer 232 of the sidewall of the region 230, and the material of the conductive plug is doped poly, and the components in the above figures may have the same or similar parts as those shown in FIGS. Referring to the previous related description, no repeated explanation is given here. Referring to FIG. 15, after the diffusion region 230 is formed and the hard mask structure 243 as shown in FIG. 8 is removed, a deuteration process is performed to form a germanide layer 232 on the sidewall 226 of the trench 202 and covered. The sidewall of the diffusion region 230. In an embodiment of the invention, the germanide layer 232 can include a titanium germanide or cobalt germanide to reduce the electrical resistance between the diffusion region 230 and the subsequently formed conductive plug 220a. Thereafter, after the barrier layer 218 is formed, a conductive plug 220b made of doped polysilicon is formed by a thin film deposition method such as chemical vapor deposition (CVD) and a subsequent etch back step. In this embodiment, the conductive plug 220b may be, for example, an arsenic doped poly-layer (As-doped poly). Further, through a subsequent planarization process such as chemical mechanical polishing (CMP), a conductive structure 500e according to an embodiment of the present invention as shown in Fig. 2e is formed.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application.

200. . . Substrate

201. . . Patterned hard mask layer

201a. . . Cerium oxide cushion

201b. . . Tantalum nitride layer

202. . . Trench

204, 212. . . Bottom

206. . . Side wall

208. . . Insulating mat

211, 220. . . Conductive material

212, 218. . . Barrier layer

214. . . Conductive layer

228. . . Diffusion source layer

230. . . Diffusion zone

232. . . Telluride layer

240. . . First dielectric layer

242. . . Second dielectric layer

242a. . . Doped region

242b. . . Undoped area

243. . . Hard mask structure

246. . . Opening

247. . . Depression

262. . . Ion implantation step

220a, 220b. . . Conductive plug

258. . . Cover layer

300. . . Vertical transistor

302. . . Vertical side wall

306. . . Insulation

308. . . Word line

312. . . capacitance

314. . . Bungee area

316. . . Channel area

318. . . Source area

320. . . First direction

322. . . Second direction

500, 500a, 500b, 500c, 500d, 500e. . . Conductive structure

600. . . Electronic device

a. . . angle

Fig. 1 is a perspective view showing an electronic device according to an embodiment of the present invention.

2a-2e are cross-sectional views taken along line A-A' of Fig. 1 showing conductive structures such as bit lines of an electronic device of various embodiments of the present invention.

3 to 10 are schematic cross-sectional views showing a method of manufacturing a conductive structure of an electronic device according to an embodiment of the present invention as shown in Fig. 2a.

Figure 11 is a cross-sectional view showing a method of manufacturing a conductive structure of an electronic device according to another embodiment of the present invention as shown in Figure 2b.

12 to 13 are schematic cross-sectional views showing a method of manufacturing a conductive structure of an electronic device according to still another embodiment of the present invention as shown in Fig. 2c.

Figure 14 is a cross-sectional view showing a method of manufacturing a conductive structure of an electronic device according to still another embodiment of the present invention as shown in Figure 2d.

Figure 15 is a cross-sectional view showing a method of manufacturing a conductive structure of an electronic device according to still another embodiment of the present invention as shown in Figure 2e.

200. . . Substrate

202. . . Trench

208. . . Insulating mat

212, 218. . . Barrier layer

230. . . Diffusion zone

214. . . Conductive layer

220a. . . Conductive plug

258. . . Cover layer

500a. . . Conductive structure

Claims (42)

An electronic device comprising: a substrate; a trench formed in the substrate; a diffusion region formed in a portion of the substrate adjacent to the sidewall of the trench; and a conductive structure disposed in the trench, comprising: a conductive layer covering a bottom surface of the trench, the conductive layer having a recess to expose the diffusion region from the recess; and a conductive plug filling the recess and covering a sidewall of the diffusion region, wherein the conductive layer A barrier layer is disposed between the conductive plug and the conductive layer. The electronic device of claim 1, further comprising an insulating pad covering a sidewall and a bottom surface of the trench, wherein the diffusion region abuts a sidewall of the trench not covered by the insulating pad. The electronic device of claim 2, wherein the barrier layer covers a sidewall of the diffusion region. The electronic device of claim 1, wherein the conductive structure further comprises a germanide layer formed on a sidewall of the trench not covered by the insulating pad and adjacent to the diffusion region. The electronic device of claim 4, wherein the conductive structure further comprises a diffusion source layer formed on a sidewall of the trench not covered by the insulating pad, and interposed between the germanide layer and the diffusion Between the districts. The electronic device of claim 1, wherein the conductive plug comprises a metal or polysilicon. The electronic device of claim 1, wherein the conductive layer is a metal. The electronic device of claim 1, wherein the barrier layer comprises titanium, titanium nitride or a combination thereof. The electronic device of claim 1, further comprising a cover layer formed in the trench and covering the conductive plug. The electronic device of claim 3, wherein the insulating layer comprises an oxide layer, a nitride layer or a combination thereof. The electronic device of claim 5, wherein the diffusion source layer comprises doped polysilicon. The electronic device of claim 1, wherein another conductive layer is disposed between the conductive layer and the trench. The electronic device of claim 1, wherein the conductive structure is a one-dimensional line. The electronic device according to claim 1 is a dynamic random access memory device. A memory device includes: a substrate; at least one vertical transistor formed in the substrate, having a vertical sidewall; at least one word line formed in the substrate along a first direction, the word line is set And on the vertical sidewall of the pair of vertical transistors; and at least one bit line formed in at least one of the trenches in a second direction different from the first direction, and located in the pair of vertical transistors Bottom, and electrically contacting a drain region of the vertical transistor by a diffusion region formed in a portion of the substrate adjacent to the sidewall of the trench, wherein the bit line includes: a conductive layer covering the trench a bottom surface, the conductive layer has a recess to expose the diffusion region from the recess; and a conductive plug fills the recess and covers a sidewall of the diffusion region, wherein the conductive plug and the conductive layer There is a barrier layer between them. The memory device of claim 15 further comprising at least one capacitor electrically contacting a source region of the vertical transistor. The memory device of claim 15, wherein the bit line further comprises an insulating pad covering a sidewall and a bottom surface of the trench, wherein the diffusion region is adjacent to the trench without an insulating pad The side walls covered by the layer. The memory device of claim 17, wherein the barrier layer covers a sidewall of the diffusion region. The memory device of claim 15, wherein the bit line further comprises a germanide layer formed on a sidewall of the trench not covered by the insulating pad and adjacent to the diffusion region. The memory device of claim 19, wherein the bit line further comprises a diffusion source layer formed on a sidewall of the trench not covered by the insulating pad and interposed between the germanide layer Between this diffusion zone. The memory device of claim 15, wherein the conductive plug comprises a metal or polysilicon. The memory device of claim 15, wherein the conductive layer is a metal. The memory device of claim 15, wherein the barrier layer comprises titanium, titanium nitride or a combination thereof. The memory device of claim 15 further comprising a cover layer formed in the trench and covering the conductive plug. The memory device of claim 17, wherein the insulating underlayer comprises an oxide layer, a nitride layer or a combination thereof. The memory device of claim 20, wherein the diffusion source layer comprises doped polysilicon. The memory device of claim 15, wherein another barrier layer is disposed between the conductive layer and the trench. A method of manufacturing an electronic device, comprising the steps of: providing a substrate; forming a trench in the substrate; forming a conductive layer in the trench covering a bottom surface and a portion of a side surface of the trench, the conductive layer having the adjacent layer a recess of the sidewall of the trench; a diffusion region is formed in the substrate adjacent to the recess; a barrier layer is formed in the trench to cover the conductive layer; and a conductive plug is formed in the trench Filling the recess and covering the sidewall of the diffusion region. The method of manufacturing an electronic device according to claim 28, wherein the step of forming the conductive layer further comprises forming an insulating underlayer on the sidewalls and the bottom surface of the trench. The method of manufacturing the electronic device of claim 29, wherein the step of forming the conductive layer further comprises: forming a conductive material in a comprehensive manner and filling the trench; and performing an etching process to remove the a conductive material over the substrate and partially located in the trench; compliance forming a hard mask structure in the trench having an opening to expose a portion of the conductive material; and removing the hard mask structure A portion of the conductive material is covered to form the conductive layer having the recess. The method of manufacturing the electronic device of claim 30, wherein the step of forming the diffusion region further comprises: removing the portion of the insulating spacer exposed from the recess to expose a portion of the sidewall of the trench ; and remove the hard mask structure. The method of manufacturing an electronic device according to claim 30, wherein the step of forming the conductive layer further comprises forming another barrier layer on the sidewalls and the bottom surface of the trench. The method of manufacturing the electronic device of claim 30, wherein the step of forming the hard mask structure further comprises: conforming to the first dielectric layer of the lower layer and the second layer of the upper layer in the trench a dielectric layer; performing an ion implantation step on the second dielectric layer in a direction to form a doped region and an undoped region in the second dielectric layer; performing a wet etching process to remove the non-doped layer Doping the region until a portion of the first dielectric layer is exposed; and performing a dry etching process to remove the first dielectric layer that is not covered by the second dielectric layer to form a hard mask structure . The method for manufacturing an electronic device according to claim 28, wherein the step of forming the diffusion region further comprises: injecting a gas containing a dopant from a sidewall of the trench exposed by a gas phase doping method; In the substrate, the diffusion region is formed. The method of manufacturing an electronic device according to claim 28, wherein the step of forming the diffusion region further comprises forming a diffusion source layer on a sidewall of the trench. The method of manufacturing an electronic device according to claim 35, wherein the diffusion region is adjacent to the diffusion source layer. The method of manufacturing an electronic device according to claim 36, wherein the step of forming the barrier layer further comprises forming a germanide layer in the trench and covering a sidewall of the diffusion source layer. The method of manufacturing an electronic device according to claim 33, wherein the first dielectric layer and the second dielectric layer are made of different materials. The method of manufacturing an electronic device according to claim 38, wherein the first dielectric layer comprises an oxide layer or a nitride layer, and the second dielectric layer is an undoped amorphous germanium. The method of manufacturing an electronic device according to claim 28, wherein the conductive plug comprises a metal or a polysilicon. The method of manufacturing an electronic device according to claim 28, wherein the conductive layer is a metal. The method of manufacturing an electronic device according to claim 28, wherein the electronic device is a one-dimensional line of a dynamic random access memory cell.