TWI416896B - Methods and apparatus for data transmission based on signal priority and channel reliability - Google Patents

Abstract

This invention provides different data transmitting methods and devices thereof based on signal priority valve and channel reliability. An demonstrating method of this invention includes: coding multiple bits into coding bits with multiple system bits and multiple parity bits corresponding to each other, for the purpose of transmitting the data, the bits are coding through multiple channels of a communication system with multiple channels, where, the communication system with multiple channels includes a high reliability channel and a lower reliability channel. Said demonstrating method of this invention also includes: assigning system bits to different bits locations corresponding to first series current in channel with high reliability, assigning system bits to different bits locations corresponding to high signal priority valve in second series current in channel with low reliability, and assigning parity bits to the bits locations in second series current. This invention also provides similar or related methods and related devices for assigning system bits and parity bits to corresponding each bits locations in channels with high and low reliability.

Description

Data transmission method and device based on signal prior weight and channel reliability

Related to a data transmission, relating to data processing of data transmission in a multi-channel communication system.

A multi-channel communication system is a wireless communication system capable of transmitting information (such as audio and data) between a transmitting end and a receiving end, wherein each of the transmitting end and the receiving end may have at least one transmitting end antenna and one receiving end antenna . For example, the multi-channel communication system may include a multiple-input multiple-output (MIMO) communication system, an Orthogonal Frequency Division Multiplexing (OFDM) system, and/or a Multiple input multiple output system with orthogonal frequency division multiplexing. A multiple input multiple output system uses a plurality of transmit antennas and a plurality of receive antennas to form a plurality of spatial subchannels using spatial diversity, wherein each subchannel is used to transmit data. An orthogonal frequency division multiplexing system divides an operating frequency band into a plurality of frequency sub-channels, and each frequency sub-channel is a sub-carrier capable of transmitting modulated data. Therefore, the multi-channel communication system can support a plurality of transmission channels, and each transmission channel can correspond to a spatial sub-channel in a multiple input multiple output system, a frequency sub-channel in an orthogonal frequency division multiplexing system, or use positive A spatial subchannel of a frequency subchannel in a multiple input multiple output system with crossover frequency multiplexing.

In the multi-channel communication system, the transmission channel will form different channel conditions due to different attenuation and multipath effects, thus forming different signal-to-interference-plus-noise ratio (signal-to-interference-plus-noise ratio, Referred to as SINR). Therefore, the transmission capacity (such as information bit rates) that the transmission channel can provide varies from channel to channel. In addition, channel conditions often change with time/frequency. Therefore, the bit rate that the transmission channel can provide also varies with varying channel conditions and reliability. In this regard, a single channel that has experienced a poor communication channel typically limits the overall transmission rate of multiple channels. For applications that manipulate communication data, the transmission rate will be slower and the user will experience slower transmission speeds.

The exemplary methods and exemplary devices described herein provide for the transmission of data based on signal pre-weights and signal/channel reliability. Some of the disclosed embodiments may indicate which of the plurality of channels has higher reliability and assign more important data bits to the bit positions in the data stream according to channel reliability. In addition, some of the disclosed embodiments may selectively allocate more important data bits to higher signal pre-weighted positions in the modulated data symbols to increase the probability of successful transmission of related information.

According to some embodiments, the transmitted message bits may first be encoded to generate system bits and parity bits. As used herein, a system bit is a coded bit that describes the data of the information bits that are input to the encoder, and its status is important in successful communications. The parity bit is the coded error correction or error acknowledgement bit and is less important in successful communication. An embodiment allocates system bits and parity bits to a data stream of a plurality of channels in a corresponding multi-channel system to increase communication throughput and overall reliability.

A number of embodiments are described herein that provide an example of a method of data transmission based on signal prior weight and channel reliability. The exemplary method includes encoding a plurality of bits into coded bits having a plurality of system bits and their respective corresponding plurality of parity bits, in order to transmit data through a plurality of channels of a multi-channel communication system. The above bit coding, wherein the multi-channel communication system comprises a higher reliability channel and a lower reliability channel. The exemplary method further includes allocating the system bit and the parity bit to a bit position corresponding to the first stream of one of the higher reliability channels, or corresponding to one of the lower reliability channels. The stream is in the meta-location. The step of configuring the system bit and the co-located bit may include allocating at least a plurality of the system bits to a bit position of the first stream, and allocating at least a plurality of remaining system bits to the second stream a bit position having a higher signal first weight, and assigning at least a plurality of the same bit to the remaining bit positions remaining in the second stream.

Another embodiment is a device for transmitting data based on signal prior weight and channel reliability. According to some embodiments, the apparatus further includes an encoder and a one-bit counterpart. The encoder is configured to encode a plurality of bits into coded bits having system bits and corresponding co-located bits. The bits are encoded by transmitting data through a plurality of channels of a multi-channel communication system. The multi-channel communication system includes a higher reliability channel and a lower reliability channel. The bit corresponding device is configured to allocate the system bit and the co-located bit to a bit position corresponding to the first stream of one of the higher reliability channels, or to one of the lower reliability channels In the position of each element of the second stream. The step of configuring the system bit and the co-located bit includes assigning at least a plurality of the system bits to a bit position of the first stream, and allocating at least a plurality of the system bits to a bit position of the first stream The method includes allocating at least a plurality of the system bits to a bit position of the first stream having a higher signal pre-weight. The bit correlator is further configured to allocate at least a plurality of the parity bits associated with the system bit located in the first stream to a bit position in the second stream.

Another embodiment is a computer program product that transmits data based on signal weights and channel reliability. The computer program product includes at least one computer readable storage medium having a plurality of memory executable readable program code instructions, wherein the computer readable storage medium readable program code instructions are used to generate a device Performing encoding a plurality of bits into coded bits having a plurality of system bits and their respective corresponding plurality of parity bits, wherein the bits are encoded in order to transmit data through a plurality of channels of a multi-channel communication system, The multi-channel communication system includes a higher reliability channel and a lower reliability channel. The computer readable program code instructions to generate a means for assigning the system bit and the co-located bit to a bit position corresponding to the first stream of one of the higher reliability channels, or corresponding to the comparison One of the low reliability channels is in the position of each of the second streams. The step of configuring the system bit and the co-located bit includes assigning at least a plurality of the system bits to a bit position of the first stream, and allocating at least a plurality of the system bits to a bit position of the first stream The method includes allocating at least a plurality of the system bits to a bit position of the first stream having a higher signal pre-weight. The computer readable code instructions further generate a means for performing allocation of at least a plurality of the parity bits associated with the system bits in the first stream to a bit position in the second stream.

The disclosed embodiments are accompanied by the illustrations, but in some cases, possible embodiments are not shown in the drawings. Where possible, the same component numbers in the drawings represent the same or similar parts. As used herein, the terms "data," "content," "information," and similar terms are used interchangeably to refer to the information that can be transmitted, received, and/or stored in accordance with the disclosed embodiments.

As mentioned above, a Multiple Input Multiple Output (MIMO) technique is applied to a plurality of antennas at the transmitting end and the receiving end to achieve simultaneous transmission of a plurality of independent data streams to increase the transmission rate. The technology according to the above principles is adopted in the fourth generation wireless communication standard combined with the multiple input multiple output mode which has been specifically formulated in the IEEE 802.16e standard. Regardless of this particular technique, the architecture of multiple input multiple output transmission is based on a single codeword (SCW) structure or a multiple codeword (MCW) structure.

For a single codeword structure, this architecture includes a single set of modulation order and a modulation rate coding and coding scheme (MCS) for use at the transmitting end. In other words, the multi-codeword structure uses the modulation and coding mechanisms of the complex array (for example, two groups). According to one of the above two techniques, some parameters applicable to the transmitting end, such as the modulation level and the encoding rate, will be used to improve the transmission performance. Since multi-codewords (MCW) have more parameters that can be effectively modified, multi-codewords provide more performance gain than single-wordword transmission architectures. However, this architecture may require additional feedback overhead, which can result in a reduction in overall bandwidth efficiency.

Figure 1 is a block diagram showing the transmission side of a spatially multiplexed multiple input multiple output (SCW) based on a single codeword transmission architecture with precoding usage. The transmitting end includes an encoder 126, a channel interleaver 128, a rate matcher 130, a symbol mapper 132, and a codeword pair stream counterpart. (codeword (CW)-to-stream mapper) 134, a precoder 136 coupled to a plurality of antenna ports, and a controller 138. Encoder 126 receives a codeword block containing information bits 124 in the bitstream. Encoder 126 then encodes the received information bits 124 according to an encoding mechanism, for example, using a 1/3 code rate turbo code with tail bit addition (1/3-rate turbo code, TC).

Turbo code (TC) or convolutional turbo code (CTC) uses a double binary circular recursive systematic convolutional code (double binary CRSC code), as shown in Figure 2. Said in the middle. Figure 2 is a diagram depicting a more specific encoder 126. First, a plurality of input information bits (A, B) are encoded into a plurality of system bits (A, B) and a plurality of parity bits (Y1, Y2, W1, W2) by a swirling turbo code. Each system bit corresponds to at least a number of co-located bits. The parity bit is used for error detection or correction of its corresponding system bit. The parity bits Y1 and W1 are generated by a constituent encoder 102, and the parity bits Y2 and W2 are generated by a convolutional turbo code interleaver 100 and a constituent encoder 104.

After encoding, the plurality of sub-blocks of the coded bits are interleaved by the channel interleaver to avoid communication errors of the cluster type on the special channel. Regarding FIG. 3, each sub-block of a plurality of bits, for example, A sub-block 108, B sub-block 110, Y1 sub-block 112, Y2 sub-block 114, W1 sub-block 116, W2 sub-area Block 118, routing the bit order through sub-block interleaver 120 to generate an interleaved code sequence 122.

After the interleaving process, the interleaved code sequence 122 including the systematic bit portion and the co-located bit portion is subjected to a puncture action to conform to the encoding rate desired by the rate matcher 130. After the culling action, the symbol counterpart 132 converts the encoded bit into a complex-valued symbol, wherein the complex symbol is a symbol having a real part and an imaginary part. The modulated symbols are converted from a single sequence to a multiple transmitted stream by a codeword pair stream counterpart 134. For example, a circulation-based CW-to-stream mapper based on a data loop placement method is used. Next, the stream is precoded in precoder 136 according to a pre-designed precoding matrix and transmitted by a plurality of antennas. Figures 4a, 4b, and 4c show graphical representations of a stream-to-stream counterpart 134 converting a single encoded, modulated symbol sequence into 2, 3, and 4 streams, respectively. The above encoding rate, modulation level, number of transmitted data streams, and precoding matrix are all adjusted by the controller 138 to correct the transmission of the combination.

Figure 5a shows an example of data processing based on single codeword spatial multiplex multiple input multiple output, where the number of information bits N _ep is 48 and 16 orthogonal amplitude modulation (16-QAM), code rate R is 2/3, and the number L of streams is 2. In this example, the information bits are first encoded using a 1/3 code rate convolutional turbo code, followed by a bit interleaving and culling procedure to conform to a 2/3 code rate. Thus, the coded bit sequence includes 48 system bits and the remaining 24 coded bits that are considered to be co-located bits after the culled action. The parity bit in the sequence of coded bits follows the system bit. After the culling procedure, the symbol bit is mapped to the symbol by the symbol counterpart 132. Since the 16-quadrature amplitude modulation mechanism is utilized, every four coded bits are divided into a group corresponding to a complex modulation symbol.

Each symbol has a connected bit position, some of which have a higher signal first bit position (eg, a sign bit), and some bit positions have a lower signal first value Bit position (for example: non-sign bit). The bit line with the bottom line in Fig. 5a represents the sign bit of a complex modulating symbol, and the sign bit of the complex modulating symbol is used to represent the real value and imaginary number of a complex modulating symbol. (image value). Due to the structure of the symbol, the sign bit has a higher signal pre-weight than the non-symbol bit. In general, a complex modulator is composed of a plurality of coded bits. For example, two bits form a quadrature phase key shift (QPSK) symbol, four bits form a 16 quadrature amplitude modulation (16-QAM) symbol, and six bits form a 64 quadrature amplitude modulation. Change (64-QAM) symbol. Two of the bits in any symbol are used to represent a real (eg, in-phase) portion of a quadrature amplitude modulation (QAM) symbol and an imaginary (eg, orthogonal) portion, ie, a sign bit. Figures 5b and 5c show a coded constellation of 16 orthogonal amplitude modulations, where the first and third bits represent the real and imaginary symbols, respectively. As shown in Figures 5b and 5c, changing the first bit and the third bit respectively represent a different half of the constellation, (ie, the symbols when the first bit is 1 occur in the constellation In the left half of the middle, the symbols when the first bit is 0 occur in the right half of the constellation; and the symbols when the third bit is 0 occur in the upper half of the constellation, Symbols with a octet of 1 occur in the lower half of the constellation. During the transmission of a symbol, the transmitted bit will typically be in the same half or quadrant of the demodulation region. It can be seen that a bit that determines half or quadrant has a relatively low error rate compared to a bit that does not define a half or a quadrant. Therefore, these bits have higher signal pre-weights and are more important bits in transmission. Based on this characteristic, due to reliability considerations, more important coding bits (such as system bits) will be assigned to the location of the sign bit in a complex modulation symbol.

Again using the same example as in Figure 5a, all 72 coded bits are mapped to 18 16 quadrature amplitude modulation (16-QAM) symbols. As shown in the example, it can be seen that some system bits are assigned to non-symbol bits of a complex modulation symbol. Finally, the codeword pair stream counterpart 134 evenly distributes the 18 orthogonal amplitude modulation symbols described above into two transport streams and transmits them via two actual channels. As in the direction of the arrow in Figure 5a, the system bits and the corresponding parity bits are assigned to the same channel. Based on the above discussion, it is assumed that one channel has better and more reliable transmission quality than the other channel. However, according to this example illustration, the channel will present the same processing for the bit configuration. In this example, some system bits will be placed in less reliable channels due to the rate R of 2/3.

Figure 6 is a block diagram showing a transmission end of a multi-codeword based spatial multiplex multiple input multiple output (MCW) based on a precoding architecture. The transmitting end includes a splitter 140, an encoder 142, a channel interleaver 144, a rate matcher 146, a modulator 148, a codeword pair stream counterpart 150, and a plurality of antennas. A precoder 152, and a controller 154. For a multi-codeword based architecture, the controller 154 adjusts a plurality of modulation and coding mechanisms depending on the channel conditions. Compared to the single codeword structure described above, more parameters have to be adjusted due to channel variations to provide improved link performance. However, an increase in the number of changeable parameters will result in an increase in the demand for feedback signals. Therefore, the data processing method of the basically multi-codeword structure is similar to the single codeword structure, and the multi-codeword structure is processed simultaneously based on a plurality of codewords. Figures 7a and 7b show a schematic diagram of how the codeword pair streamer counterpart 150 and precoder 152 operate. In this regard, Figures 7a and 7b illustrate the case where the codeword pair stream selector 150 converts each of the two coded symbol sequences into three or four streams.

Figure 8 shows a single codeword structure in accordance with an embodiment. The structure of Figure 8 shows a system block diagram of an exemplary method and/or example apparatus used for data distribution based on signal prior weighting and reliability to improve transmission quality. While FIG. 8 depicts an explanation of a single codeword, those skilled in the art can equally appreciate embodiments in which a multi-codeword structure is applied. The encoder 126, the channel interleaver 128, the rate matcher 156, the codeword pair stream counterpart 158, the symbol counterpart 160, the precoder 136, and the controller 162 can be implemented in at least one hardware device in a hardware or software manner. (Example: integrated circuit).

With respect to Figure 8, encoder 126, channel interleaver 128, and precoder 136 operate as described above. However, in accordance with some embodiments, after the interleaving procedure, the coding bits will be rate matched by the rate matcher 156 based on the desired coding rate and the signal prior weight. In this regard, according to various embodiments, the rate matcher 156 can cull some of the parity bits from the code sequence according to a puncturing ratio or a culling rule, wherein the controller 162 can be configured according to channel reliability and/or bit. To determine the rejection rate or rejection rules. The rejection ratio is the ratio of the parity bits associated with the system bits of the stream located in the higher reliability channel to the parity bits associated with the system bits of the stream located in the lower reliability channel. According to various embodiments, it is desirable that the parity bits associated with the system bits of the stream located in the lower reliability channel be related in number to the system bits of the stream in the higher reliability channel. The rejection ratio design is performed under the criterion of more homo-bits. For example, a 1:2 rejection ratio means that the parity bits associated with system bits in the higher reliability channel are compared to the parity bits associated with the system bits in the lower reliability channel. It has twice the number of parity bits.

The codeword pair stream counterpart 158 and the symbol counterpart 160, which can be regarded as a one-element counterparter, can allocate system bits and parity bits to different streams according to the reliability of the channel. In this regard, the coded bits after the interleaving procedure are first culled according to the signal reliability and corresponding to the stream, and then the symbol counterpart 160 then each according to the signal weight and reliability. The plurality of bits in the stream correspond to modulation symbols. Thus, the codeword pair stream counterpart 158 performs the stream correspondence in a bitwise manner, rather than in a symbolic manner, as compared to the codeword pair stream counterpart 134.

According to various embodiments, the symbol correspondence may be performed based on the first weight of the modulation symbol to further improve the transmission link quality. In addition, according to different embodiments, Symbol Mapping Based Priority (SMP) can be performed. According to the symbolic correspondence (SMP) of the first weight, the system bit (for example, the important part of the coding sequence) is assigned to the bit position of the high-order first weight in a complex modulation symbol (for example: sign bit) yuan). Additionally, according to various embodiments, system bits are allocated to the stream of higher reliability channels based on backhaul information from the receiving end or other network entity. Compared to the parity bit, because the system bit is the transmitted information bit, the system bit is more important in the coded bit sequence. When the signal transmission reliability in each channel is available at the transmitting end, assigning system bits to a more reliable channel provides an improved transmission link quality. Therefore, according to different embodiments, most of the system bits are configured as far as possible into the higher reliability channel. However, based on the code rate, it is also possible for system bits to be configured into lower reliability channels.

By feeding back the signal to the controller 162, the information used to indicate which channel is more reliable may result in an increase in the feedback semaphore. However, according to other embodiments, the amount of feedback semaphore can be limited to only the number of bits that specifically describe the channel with the best reliability. According to other embodiments, a feedback signal amount of 1 to 3 bits is sufficient. In some embodiments, for example, a multiple input multiple output system corresponding to two data streams of respective channels, a one-bit overhead is required to be given to an open loop (open- Loop) A transmitter in a multiple input multiple output system to indicate the quality of the channel. If N _s transmission streams are used, the number of bits required for log ₂ N _S is used in the notification of channel reliability. In some closed loop systems, channel reliability information is already available at the transmitting end, so no additional feedback signals are required. Therefore, assigning bit locations based on combined channel reliability and signal prior weights can therefore be used to develop a joint set of joint allocations to improve link reliability and increase overall spectral efficiency.

According to the above description, the 9, 9, 13, and 15 diagrams show the bit position assignment results of several embodiments. It is worth noting that while Figures 9, 11, 13 and 15 all have systems for two effective channels, the techniques and embodiments shown above can be applied to systems using any number of channels. Figure 9 shows the location of the bit by using a symbol-based correspondence rule based on the signal-based weight and a code-to-stream correspondence rule based on signal/channel reliability. As shown in Figure 9, the number of signal data is 48, using 16 orthogonal amplitude modulations with a code rate of 2/3, and two sets of data streams are generated on each transmitted channel. The degree of reliability of the two channels is determined by, for example, a feedback signal received by the controller 162.

As described in Figure 9, after encoding, interleaving, and culling procedures, sequences of encoded system bits and parity bits are generated. These generated coded bits are then configured with their bit placement by a signal-to-stream counterpart based on signal reliability. In this way, the system bits can correspond to the stream in the more reliable channel, the remaining system bits are placed in the lower reliability channel, and all the parity bits are arranged to the lower reliability channel. In the stream. Next, the symbol correspondence is performed according to the symbol correspondence (SMP) rule of the first weight. The system bits of the stream located in the lower reliability channel are assigned to the bit positions of the higher signal prior weights in the complex-valued symbols in the stream of the lower reliability channel. , that is, the position of the symbol bit. The co-located bit is configured to the bit position of the lower signal pre-weight in the stream of the lower reliability channel, that is, the position of the non-symbol bit. Therefore, such an operation results in that the first stream in the higher reliability channel is the system bit, and the higher signal precedence bit position in the second stream in the lower reliability channel It is a system bit, and any remaining higher signal first weight bit positions in the second stream in the lower reliability channel and the lower signal first weight bit positions are all parity bits.

Figure 10 is a flow chart showing an exemplary method for completing the bit configuration of Figure 9. The exemplary method of FIG. 10 includes encoding a bit to be transmitted through a plurality of channels of a multi-channel communication system, wherein the bit is encoded as a coded bit having system bits and parity bits (in step 400). The multiple channels of the multi-channel communication system include a channel with higher reliability and a channel with lower reliability. In step 410, the exemplary method includes configuring at least a number of system bits to a bit position in a first stream of higher reliability channels. According to other embodiments, all of the bit locations in the first stream are allocation system bits. In step 420, the exemplary method includes configuring at least a number of remaining system bits to a bit position in the second stream of the lower reliability channel having a higher signal prior weight. According to other embodiments, some or even all of the bit positions of the higher signal prior weights in the second stream are assigned to system bits. In step 430, the exemplary method also includes allocating at least some or all of the parity bits to the remaining bit locations remaining in the second stream. In some embodiments, allocating at least some or all of the co-located bits includes assigning some of the co-located bits associated with the system bits located in the first stream to the bit locations in the second stream.

Figure 11 is a diagram showing another method of bit configuration in accordance with an embodiment. Figure 11 is a bit configuration determined using a combined culling procedure and signal/channel reliability based codeword pair stream correspondence rules and symbol precedence rules based on signal prior weights. In the example depicted in Figure 11, the number of signal data is 48, a 16-quadrature amplitude modulation of 2/3 is used, and a set of data streams is generated on each of the transmitted channels. And to determine which of the channels has better reliability than the other channel.

As described in FIG. 11, after encoding and interleaving procedures, encoded system bits and sequences of parity bits are generated. These generated coded bits then correspond to their position based on signal reliability by the codeword pair stream counterpart. As such, system bits can correspond to streams of higher reliability channels. Any remaining system bits are placed in the lower reliability channel, and all of the parity bits are placed into the stream of lower reliability channels.

The undesired bits of the coding sequence are culled according to the culling ratio. Thus, after the system bits fill the bit locations of the higher reliability channels, it is determined which system bits are still allocated to the lower reliability channels. The rejection ratio decision is that after the culling procedure, the parity bits associated with the system bits configured in the lower reliability channel can be compared to the number of parity bits associated with the system bits in the higher reliability channel. many. As described in FIG. 11, the rejection ratio is 1:2. In some embodiments, the codeword pair stream correspondence is performed based on the reliability after the culling procedure.

The symbol correspondence is performed according to the symbol-based correspondence (SMP) rule based on the first weight. Thus, system bits located in the stream of the lower reliability channel will be assigned to the bit position of the higher signal first weight in the symbol, ie, the symbol bit position, and the parity bit is configured. The lower signal precedence bit position in the symbol in the stream of the lower reliability channel, that is, the non-symbol bit position. Therefore, such an operation results in that the first stream in the higher reliability channel is the system bit and the second stream in the lower reliability channel has the system bit in the high signal first bit position. yuan. The co-located bit is assigned to the bit position of the second stream having the lower signal first weight in the symbol of the configured system bit, and the remaining co-located bits are assigned to any of the second stream The remaining available bit locations.

Figure 12 is a flow chart showing an exemplary method for completing the bit configuration described in Figure 11. The exemplary method of Figure 12 includes encoding the bit to be transmitted as a coded bit through a plurality of channels of a multi-channel communication system, wherein the coded bit has system bits and parity bits (in step 500). The multiple channels of the multi-channel communication system include a channel with a higher reliability and a channel with lower reliability. In step 510, unwanted coding bits are culled based on the culling ratio. The above rejection ratio decision is intended to leave more of the parity bits associated with the system bits configured in the second stream. According to some embodiments, the culling procedure is performed prior to configuring the bit position. In step 520, the exemplary method includes allocating at least a number of system bits to a bit position in a first stream corresponding to a higher reliability channel. According to other embodiments, all bit locations in the first stream are configured as system bits. In step 530, the exemplary method includes allocating at least a number of remaining system bits to a bit position having a higher signal pre-weight in the second stream of the channel corresponding to the lower reliability. In step 540, the exemplary method also includes including at least a number of co-located bits remaining in the cull program associated with system bits located in the bit position of the second stream, and bits located in the first stream At least a number of co-located bits associated with the culling program associated with the system bits of the meta-location are allocated to the lower signal-first weight location remaining in the second stream.

Figures 13 and 15 show the location allocation of the bits using a combined culling procedure and a codeword-to-stream correspondence rule based on signal/channel reliability and a symbol correspondence rule based on both the signal first weight and the reliability. In the example depicted in Figures 13 and 15, the number of signal data is 48, using 16 orthogonal amplitude modulations with a rate of 2/3, and generating a set of data streams on each transmitted channel. And determine which channel has better reliability than the other channel. The location allocation of the parity bits is related to both the signal pre-weight and the signal/channel reliability.

Figure 13 shows the sequence of coded system bits and parity bits. This sequence consists of 48 systematic bits and 24 co-located bits, assuming a pre-defined rejection ratio of 1:2 and using the parameters described above. The bit configuration of Fig. 13 shows that a series of operations are performed according to the word pair correspondence and the symbol correspondence rule.

In the first operation in Figure 13, the system bit is first allocated to the bit position in the higher reliability channel, and the remaining system bits are assigned to the higher signal first weight in the lower reliability channel. Bit position. In a second operational step, the rejection ratio is used to determine the number of parity bits associated with system bits configured in the lower reliability channel, and then the corresponding parity bits are configured to be left in the lower reliability channel The lower signal is in the first weight position. In a third operational step, any remaining parity bits associated with system bits configured in the lower reliability channel are assigned to the higher reliability channel and the system bits are assigned to the higher signal. The lower signal first weight position in the symbol of the first weight position. In a fourth operational step, the parity bits associated with the system bits located in the higher reliability channel are assigned to the lower signal prior weight positions remaining in the lower reliability channel.

Figure 14 is a flow chart showing an exemplary method for completing the bit configuration described in Figure 13. The exemplary method of Figure 13 includes encoding the coded bits to be transmitted through a plurality of channels of a multi-channel communication system having system bits and parity bits (in step 600). The multiple channels of the multi-channel communication system include a higher reliability channel and a lower reliability channel. In step 610, the puncturing procedure is performed on the encoded bits based on the culling ratio. The above rejection ratio decision is intended to leave more of the parity bits associated with the system bits configured in the second stream. According to some embodiments, the culling procedure is performed prior to configuring the bit position. In step 620, the exemplary method includes allocating at least a number of system bits to a bit position in a first stream of the higher reliability channels. In step 630, the exemplary method includes allocating at least a number of remaining system bits to a bit position having a higher signal prior weight in the second stream of the lower reliability channel. In step 640, the exemplary method also includes allocating at least a plurality of cull-releasing co-located bits associated with system bits located at a bit position in the second stream to the second stream having a higher The bit position of the signal first weight. In step 650, the exemplary method includes assigning at least a number of remaining co-located bits associated with system bits located in a bit position in the second stream to a lower reliability channel in which system bits are assigned The lower signal precedence bit position in the symbol of the high signal first weight bit position. As such, the parity bits can be assigned to the lower signal prior weight locations such that at least some of the parity bits are configured into the same symbols as the system bits associated therewith. In step 660, the exemplary method includes allocating at least a number of co-located bits associated with system bits located at a bit location in the first stream to a lower signal prior weight bit remaining in the second stream Meta location.

Figure 15 shows another sequence of coding system bits and co-located bits. The difference from the embodiment described in Figures 13 and 14 is that the rejection ratio of the embodiments of Figures 15 and 16 is not predefined and is determined using the formula described below. In the example depicted in Figure 15, the rejection ratio is determined to be 1:3. The bit configuration of Fig. 15 shows that a series of operations are performed by word-to-stream correspondence and symbol correspondence rules.

In the first operation in Figure 15, the system bits are allocated to the bit locations in the higher reliability channel, and the remaining system bits are allocated to the higher signal precedence bits in the lower reliability channel. Meta location. In a second operational step, the parity bits associated with the system bits configured in the lower reliability channel are configured into the remaining higher signal prior weight bit locations in the lower reliability channel. In a third operational step, all remaining co-located bits associated with system bits configured in the lower reliability channel are assigned to the lower reliability channel. System bits are assigned to higher signal first weights. The lower signal precedence bit position within the symbol of the bit position. In a fourth operational step, the parity bits associated with the system bits located in the higher reliability channel are assigned to the lower signal prior weight positions remaining in the lower reliability channel.

As mentioned above, the rejection ratio is determined based on the calculation of the formula relating to the modulation level | A |, the coding rate R, and the number M of data streams. The relationship is defined as follows:

Where N _C represents the total number of coded bits after encoding, interleaving, and culling procedures, N _S represents the number of system bits (ie, the number of information bits), and N _P represents the number of parity bits.

The relationship of the bit configuration of the stream in the lower reliability channel is defined as follows:

among them Is the number of coded bits in the lower reliability channel, The number of system bits in the lower reliability channel and Is the number of parity bits in the lower reliability channel. The number of higher signal precedence bits (ie, sign bits) of the complex symbols in the lower reliability channel is defined as:

In addition

and

among them Is the number of parity bits associated with the system bits allocated in the lower reliability channel, and Is the number of parity bits associated with the system bits allocated in the higher reliability channel. as well as Can be calculated as follows:

as well as

From equation (6) and equation (7), the rejection ratio can be determined as:

among them

Figure 16 is a flow chart showing an exemplary method for completing the bit configuration described in Figure 15. The exemplary method of Figure 16 includes encoding a set of signals to be transmitted into a coded bit having system bits and parity bits through a plurality of channels of a multi-channel communication system (in step 700). The multiple channels of the multi-channel communication system include a higher reliability channel and a lower reliability channel. In step 710, the exemplary method includes allocating at least a number of system bits to a bit position in a first stream of a higher reliability channel. In step 720, the exemplary method includes allocating at least a number of remaining system bits to a bit location having a higher signal pre-weight in the second stream of the lower reliability channel. In step 730, the exemplary method also includes allocating at least a plurality of co-located bits associated with system bits located at a bit position in the second stream to the remaining higher-priority weights in the second stream Bit position. In step 740, the exemplary method includes assigning any remaining co-bits associated with system bits located in the bit locations in the second stream to lower reliability channels in which system bits are assigned higher The lower signal precedence bit position within the symbol of the signal first bit position. In step 750, the exemplary method also includes allocating at least a plurality of co-located bits associated with system bits located at a bit position in the first stream to a lower signal prior weight remaining in the second stream The position of the bit. In step 760, the exemplary method includes determining the rejection ratio according to equations (8) and (9), as described above.

The description provided above and the data transmission demonstration method based on signal prior weight and channel reliability, demonstration devices and exemplary computer program products. Figure 17 shows an exemplary device embodiment in the form of integrated circuit/wafer 200 or communication device 201 for performing the various functions described herein. The integrated circuit/wafer 200 or communication device 201 can include and/or be used to perform the functions described herein, particularly the functions described in Figures 8-16. For example, the integrated circuit/wafer 200 can include or be used to execute an encoder 126, a channel interleaver 128, a rate matcher 160, a codeword pair stream counterpart 158, a symbol counterpart 160, and a precoder 136. And the function of the controller 162.

With respect to Fig. 17, in some embodiments, device 201 implements or comprises the constituent elements of a communication device of wired or wireless communication functionality. For example, without a stationary terminal, the device 201 can be part of an access point (eg, a base station, a wireless router, etc.), a computer, a server, a device that supports network communication, and the like. For example, a mobile terminal, the device 201 can be a mobile computer, a mobile phone, a portable digital assistant (PDA), a portable pager, a mobile TV, a game machine, and a mobile terminal. Laptop computer, a camera, a video recorder, an audio/video player, a radio, and/or a global positioning system (GPS) device, or any combination of the above Etc., regardless of the form of the communication device, device 201 also includes computing power.

The exemplary device 201 includes other integrated circuits/chips 205 for communication, a memory device 210, a communication interface circuit 215, a receiver 271, a transmitter 272, an antenna 273, a user interface circuit 220, a display 261, and a keyboard. 262 and speaker 263. The integrated circuit/wafer 205 is embodied by a device that performs various functions, such as a microprocessor, a coprocessor, a controller, and a specific purpose integrated circuit (eg, application specific integrated Circuit (referred to as ASIC), component programmable gate array (FPGA), hardware accelerator (processing accelerator, processing circuit, etc.). In some embodiments, the integrated circuit/wafer 205 is used to execute instructions stored in the memory device 210 or instructions to enter the integrated circuit/wafer 205. Thus, the instructions stored in the memory device 210 are instructions relating to the functions performed in the description of Figures 8-16.

The integrated circuit/wafer 205 may be executed in accordance with the corresponding embodiments described above, either by hardware or by instructions stored in a computer-readable storage medium, or a combination of the two. The entity that operates. Thus, in embodiments in which the integrated circuit/wafer 205 can be implemented through a dedicated integrated circuit, an element programmable logic gate array, or the like, or a portion thereof, the integrated circuit/wafer 205 can be specifically configured to manage the operations described herein. Hardware. In other embodiments in which the integrated circuit/wafer 205 can be embodied as an executor of instructions stored in a computer readable storage medium, the instructions are specifically for assembling the integrated circuit/wafer 205 for execution herein. The algorithm or operation described. In addition, in some embodiments in which the execution instructions of the algorithms, methods, and operations described herein can be performed in accordance with the configuration of the integrated circuit/wafer 205, the integrated circuit/wafer 205 is a specific device for performing the embodiments. Processor (for example, mobile terminal).

The memory device 210 is at least one computer readable storage medium including volatile and/or non-volatile. In some embodiments, the memory device 210 includes dynamic RAM and/or static RAM, on-chip or off-chip. ) Memory access memory and/or random access memory (RAM). In addition, the memory device 210 may include embedded and/or removable non-volatile memory, and may include read only memory, flash memory, magnetic storage devices (eg, hard disk, floppy device, tape, etc.) ), optical disk drive and/or media, non-volatile random access memory (NVRAM) and/or the like. The memory device 210 can include a cache buffer for temporary storage of data. In this regard, some or all of the memory device 210 can be included within the integrated circuit/wafer 205.

The communication interface circuit 215 can be any device or tool implemented in hardware, a computer program product, or a combination of hardware and computer program products, wherein a combination of hardware and computer program products can be used for receiving and/or transmitting. Data from/to the network 225 and/or any other device or module that communicates with the example device 201 via the receiver 271, the transmitter 272, and the antenna 273. The integrated circuit/wafer 205 can also facilitate communication of data by, for example, controlling the hardware through the communication interface circuitry in the communication interface circuit 215. In addition, the integrated circuit 271, the transmitter 272, and the integrated circuit 252 of the antenna 273 and the communication interface circuit 215 are used to support any wireless communication, including the environment with multiple input multiple output (MIMO) and the implementation of positive Communication of the environment of the crossover frequency multiplex (OFDM) signal.

The user interface circuit 220 is in communication with the integrated circuit/wafer 205 to receive user input or provide user output through the display 261, the keyboard 262, and the speaker 263. According to some embodiments, such as the embodiment in which device 201 is a base station, user interface circuitry 260, display 261, keyboard 262, and speaker 263 are eliminated.

10, 12, 14 and 16 are flowcharts of systems, methods and/or computer program products according to an embodiment. With the aid of these illustrations, it is understood that each operation or block of the flowchart, and/or the operation of the flowchart or the combination of the blocks can be implemented by many means. The operation of the flowcharts or the means of the blocks, the operations of the flowcharts or the combination of the blocks or other functions of the embodiments described herein may include hardware, and/or include computer program products having computer readable storage media. And wherein the computer readable storage medium has at least one computer code command, a computer command or an executable computer readable code command stored therein. As discussed herein, the code instructions can be stored in a memory device, such as the memory device 210 of the example device (eg, the exemplary device 201), and the components described in FIG. 8 or a processor (eg, integrated circuit/wafer). 205) to execute. It is known to those skilled in the art that any program code instructions can be loaded from a computer readable storage medium into a computer or other programmed device (eg, integrated circuit/wafer 205, memory device 210, etc.) to produce a A particular device enables the device to function as a method or operation described in the flowchart. The code instructions can also be stored on a computer readable storage medium to manage a computer, a processor or other programmed device to operate in a particular method to form a particular device or particular article of manufacture. The instructions stored on the computer readable storage medium may result in the manufacture of a device that performs the functions of the method or operation illustrated by the flowchart. The code instructions are retrievable in a computer readable storage medium and loaded into a computer, processor or other programming device for performing operations via the computer, processor or other programmed device, or on the computer, processor or Other program control devices are executed. The retrieving, loading, and execution of the above code instructions can be performed in series, so that an instruction can be retrieved, loaded, and executed at a time. In some embodiments, the retrieving, loading, and execution of the code instructions can be performed in a parallel manner so that the code instructions can be retrieved, loaded, and executed together. Execution of the code instructions produces a computer-executable program, such that the instructions executed by the computer, processor or other programmed device described above provide the functionality to perform the functions of the methods or operations described in the flowchart.

Accordingly, instructions relating to blocks or operations of the flowcharts, or storage associated with blocks or operations of the flowcharts in the computer-readable storage medium, are supported by the processor to support performing a combination of these particular functional operations. It can be understood that at least one block or operation in the flowchart or a combination of the above-mentioned blocks or operations, a computer system capable of performing a specific function or a specific purpose hardware and a combination of code instructions on a hardware basis for a specific purpose and/or Or the processor implements it.

The features and advantages of the present invention, as well as the teachings of the present invention, will be apparent to those skilled in the art. Therefore, it is to be understood that the invention is not limited to the specific embodiments disclosed herein, and any modifications, variations, and embodiments thereof are within the scope of the invention. In addition, although the embodiments are described in detail in the foregoing detailed description and the claims Various combinations of the various aspects of the invention may be provided by other alternatives without departing from the scope of the invention. In this regard, for example, any combination of the various elements set forth in the basic elements and/or functional aspects, and not the above-described explicit description, may be considered as the scope of protection as set forth in the scope of the present application. Although specific terms are used herein to describe the invention, the specific terms are used in a generic or descriptive manner and are not intended to limit the invention.

124. . . Information bit

126, 142. . . Encoder

128, 144. . . Channel interleaver

130, 146, 156. . . Rate matcher

132, 160. . . Symbol counterpart

134, 150, 158. . . Codeword pair stream counterpart

136, 152. . . Precoder

138, 154, 162. . . Controller

102, 104, 106. . . Composition encoder

100. . . Cyclotron code interleaver

108. . . A sub-block

110. . . B subblock

112. . . Y1 sub-block

114. . . Y2 sub-block

116. . . W1 subblock

118. . . W2 subblock

120. . . Subblock interleaver

122. . . Interleaved code sequence

140. . . slicer

148. . . Modulator

201. . . Communication device

225. . . network

271. . . receiver

272. . . Transmitter

273. . . antenna

215. . . Communication interface circuit

205. . . Integrated circuit/wafer

210. . . Memory device

220. . . User interface circuit

261. . . monitor

262. . . keyboard

263. . . speaker

Figure 1 is a block diagram showing a transmit end of a pre-coded single codeword based spatial multiplex multiple input multiple output (SCW).

Figure 2 is an illustration of an encoder 126, which is described in more detail.

Figure 3 is a schematic block diagram showing the channel interleaving and culling procedures.

Figures 4a-4c show block diagrams of codeword pair streams having different numbers of streams based on single codeword transmission.

Figure 5a shows the data processing based on the position of a single codeword bit.

Figures 5b and 5c show the bit reliability indicated by the 16 Quadrature Amplitude Modulation (QAM) constellation.

Figure 6 is a block diagram showing a multi-codeword based transmission end in a multiple input multiple output system.

Figures 7a and 7b show block diagrams of codeword pair streams having different numbers of streams under multi-codeword transmission.

Figure 8 is a block diagram showing a single codeword based transmission end in a multiple input multiple output system in accordance with an embodiment.

Figures 9, 11, 13, and 15 show bit configuration methods based on signal pre-weight and channel reliability, according to an embodiment.

10, 12, 14 and 16 are flowcharts showing a method of performing bit configuration based on signal pre-weight and channel reliability, according to an embodiment.

Figure 17 is a diagram showing an apparatus for performing a bit allocation method based on signal pre-weight and channel reliability, according to an embodiment.

124. . . Information bit

126. . . Encoder

128. . . Channel interleaver

130. . . Rate matcher

132. . . Symbol counterpart

134. . . Codeword pair stream counterpart

136. . . Precoder

138. . . Controller

Claims (23)

A communication method includes: encoding a plurality of bits into coded bits having a plurality of system bits and respective corresponding plurality of parity bits, in order to transmit data through a plurality of channels of a multi-channel communication system Encoding the above bit, wherein the multi-channel communication system includes a higher reliability channel and a lower reliability channel; and allocating the system bit and the co-located bit to one of the higher reliability channels In the bit positions of the first stream or the bit positions corresponding to the second stream of one of the lower reliability channels, the step of configuring the system bit and the co-located bit includes: allocating at least some of the above a system bit to a bit position of the first stream; assigning at least some of the remaining system bits to a symbol bit position of the second stream having a higher signal precedence value, wherein the sign bit a meta-location is used to indicate a bit position of the second stream having a higher signal pre-weight; and assigning at least some of the co-located bits to He said two streams in the remaining bit positions are available. The communication method according to claim 1, wherein the bit position having the higher signal first weight is the position of the symbol bit corresponding to the modulation symbol. The communication method of claim 1, wherein the step of allocating the system bit and the co-located bit further comprises allocating at least some of the other co-located bits to the second stream having a lower signal first a bit position of the weight, and the at least some of the other of the other parity bits are configured to a bit position associated with a symbol having the system bit assigned to the bit position having the higher signal precedence value in. The communication method of claim 1, wherein the communication method further comprises: culling the same bit according to a culling ratio, and the culling ratio is determined to leave more than one At least some of the remaining identical alleles associated with the system bits of the bit position in the second stream. The communication method of claim 4, wherein the step of allocating the system bit and the co-located bit further comprises at least a plurality of related to the system bit located at a bit position of the second stream. The above-described parity bits of the culling procedure are allocated to the remaining bit locations of the second stream having a higher signal precedence value. The communication method of claim 5, wherein the step of allocating the system bit and the co-located bit further comprises at least a number of passes relating to the system bit located at the second stream bit position. Releasing the remaining parity bits and at least some of the culling procedures associated with the system bits located at the first stream bit location to allocate the remaining parity bits to The bit position of the lower signal prior weight remaining in the second stream. The communication method of claim 5, wherein the step of allocating the system bit and the co-located bit comprises at least some of the system bits associated with the bit position located in the bit position of the second stream. The remaining parity bits of the culling procedure are allocated to the lower signal precedence bit locations in the symbol associated with the lower reliability channel, wherein the system bits are assigned to a lower reliability The higher signal prior weight bit position in the channel; and the remaining bit allocation remaining in the culling program associated with the system bit located in the first stream bit position And to the lower signal precedence bit position remaining in the second stream. The communication method of claim 7, further comprising: the system bit corresponding to the second stream and the plurality of groups of the same bit to the symbol; wherein the content is higher Each of the system bits of the signal prior weight bit position and each of the at least one of the group of the same bit bits located at the lower signal first bit position are associated. The communication method of claim 1, further comprising a plurality of groups corresponding to the configured system bit and the same bit to a symbol; wherein the system bit and the same bit are included Each at least one of the symbols in a group of the two is corresponding. For example, the communication method described in item 1 of the patent application includes determining a rejection ratio. / ,among them The number of parity bits associated with the first stream described above and For the number of parity bits associated with the second stream described above, the above rejection ratio is determined according to the following equation: Where R is a code rate, M is the number of streams, and | A | is a modulation level; and wherein the communication method further includes culling the above-described parity bits according to the rejection ratio. The communication method of claim 1, further comprising a plurality of groups corresponding to the system bit and the same bit in the first stream; wherein the source is included in the higher signal first weight Each of the system bits of the bit position and each of the above-described symbols in the group of the same bit positions at the lower signal priority bit position are associated. A communication device comprising: an encoder for encoding a plurality of bits into coded bits having system bits and corresponding co-located bits, wherein data is transmitted through a plurality of channels of a multi-channel communication system Therefore, the above-mentioned bit element is encoded, wherein the multi-channel communication system includes a higher reliability channel and a lower reliability channel; and a one-bit counterparter for allocating the above system bit and the above-mentioned parity bit to corresponding The first stream of one of the above higher reliability channels In the bit position of the bit or the bit position corresponding to the second stream of one of the lower reliability channels, the step of configuring the system bit and the co-located bit includes: allocating at least some of the system bits to a bit position of the first stream; assigning at least a plurality of remaining bit positions of the system bit to a second bit stream having a higher signal precedence value, wherein the symbol bit position is used Representing a bit position of the second stream having a higher signal prior weight; and allocating at least a plurality of the same bit to the remaining bit positions remaining in the second stream. The communication device according to claim 12, wherein the bit position having the higher signal first weight is the position of the symbol bit corresponding to the modulation symbol. The communication device of claim 12, wherein the bit-receiving device is configured to allocate the system bit and the co-located bit, and the step of allocating the system bit and the co-located bit further comprises allocating at least some The other parity bits are in a bit position of the second stream having a lower signal precedence value, and the at least some other of the same parity bits are configured to have the right to be assigned to have the higher signal precedence The bit position of the value is in the bit position associated with the symbol of the above system bit. The communication device of claim 12, wherein the communication device further comprises a rate matcher for determining a rejection ratio The culling procedure is performed on the above-mentioned parity bits. The above rejection ratio is determined to leave at least a plurality of reticled remaining decimators that will be associated with system bits located in the location of the bits in the second stream. The communication device of claim 15, wherein the bit corresponding device is further configured to use the cull of the at least some culling programs associated with the system bit located at a bit position of the second stream. The bit is allocated to the remaining bit position of the second stream having a higher signal pre-weight. The communication device of claim 16, wherein the bit corresponding device is further configured to remove at least some of the culling programs associated with the system bit located at the second stream bit position a parity bit and at least a plurality of culling programs associated with the system bits located at the first stream bit position, wherein the remaining bits are allocated to the lower signal remaining in the second stream The weight is in the bit position. The communication device of claim 16, wherein the bit-receiving device is configured to allocate at least some of the co-located bits, and the step of allocating at least the plurality of co-located bits includes a bit to be used with the second stream. And storing at least some of the remaining parity bits of the culling procedure associated with the system bit in the meta-location are assigned to the lower signal-first weight location in the symbol associated with the lower reliability channel, wherein The system bit is allocated to the higher signal prior weight bit position in the upper lower reliability channel; and the system bit to be located in the first stream bit position The remaining co-located bits of the at least some of the culling procedures associated with the element are allocated to the lower signal pre-weight bit positions remaining in the second stream. The communication device of claim 18, wherein the bit corresponding device is further configured to correspond to the system bit configured in the second stream and the plurality of groups of the same bit to the symbol. And wherein each of the at least one of the above-mentioned system bits including the higher signal first weight bit position and the one of the same parity bits located at the lower signal first weight bit position are corresponding. The communication device of claim 12, wherein the bit corresponding device is further configured to correspond to the configured system bit and the plurality of groups of the same bit to a symbol; wherein Each of the at least one of the system bit and a group of the above-described co-located bits is associated. The communication device of claim 12, wherein the communication device further comprises a controller, wherein the controller is configured to determine a rejection ratio / ,among them The number of parity bits associated with the first stream described above and For the number of parity bits associated with the second stream described above, the above rejection ratio is determined according to the following equation: Where R is a code rate, M is the number of streams, and | A | is a modulation level; and wherein the communication method further includes culling the above-described parity bits according to the rejection ratio. The communication device of claim 12, wherein the bit corresponding device is further configured to correspond to the system bit configured in the first stream and a plurality of groups of the same bit; Each of the system bits located at a higher signal prior weight bit position and each of the above-described ones of the group of the same bit positions at a lower signal prior weight bit position are associated. A computer program product comprising at least one computer readable storage medium having a plurality of memory executable computer readable code instructions for generating a device for executing: a plurality of bits Encoding a coded bit having a plurality of system bits and their respective corresponding plurality of co-located bits, wherein the bit is encoded in order to transmit data through a plurality of channels of a multi-channel communication system, wherein the multi-channel communication system Include a higher reliability channel and a lower reliability channel; and allocate the system bit and the parity bit to a bit position corresponding to the first stream of one of the higher reliability channels, or corresponding And configuring, in the bit positions of the second stream of the one of the lower reliability channels, the step of configuring the system bit and the co-located bit comprises: allocating at least a plurality of the system bits to the bit of the first stream Positioning; allocating at least some of the remaining system bits to the second a symbol bit position having a higher signal precedence value in the stream, wherein the symbol bit position is used to indicate a bit position of the second stream having a higher signal prior weight; and assigning at least The above-mentioned parity bit to the remaining bit position remaining in the above two streams.