TWI415316B - Memory cell access device having a pn-junction with polycrystalline and single-crystal semiconductor regions - Google Patents

Abstract

A memory device includes a driver comprising a PN-junction in the form of a multilayer stake including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a PN-junction therebetween, in which the first doped semiconductor region is formed in a single crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a PN-junction between the first and second region.

Description

A memory cell access device has a PN junction of polycrystalline and single crystal semiconductor regions

The present invention relates to high density memory devices using phase change memory materials, such as chalcogenides and other programmable resistive materials, and methods of making such devices.

Such phase change memory materials, such as chalcogenides and the like, can be applied to the current in the integrated circuit by applying an amplitude such that the crystalline phase changes between an amorphous state and a crystalline state. In general, the amorphous state is characterized by a higher electrical resistance than the crystalline state, and this resistance value can be easily sensed to indicate the state of the data. This characteristic leads to the interest of using a programmable resistive material to form a non-volatile memory circuit that can be accessed and read at random.

The transition from amorphous to crystalline is generally a low current step. The transition from a crystalline state to an amorphous state (hereinafter referred to as a reset) is generally a high current step that includes a brief high current density pulse to melt or destroy the crystalline structure, after which the phase change material is rapidly Cooling suppresses the phase change process such that at least a portion of the phase change structure is maintained in an amorphous state. The magnitude of the current required for resetting can be reduced by reducing the size of the phase change memory element in the memory cell and/or the contact area between the electrode and the phase change material, so that it can pass at a smaller absolute current value. In the case of this phase change material element, a higher current density is achieved.

Since the occurrence of this phase change is caused by heating, a relatively large current is required to heat the phase change material and initiate the desired phase change. Field effect transistor access devices have been proposed as drivers for phase change memory cells, but field effect transistors (eg, MOSFETs) are weaker current drivers. Bipolar junction transistors (BJT) provide greater current drive capability than field-effect transistors, but have difficulties in integrating bipolar junction transistors and CMOS peripheral circuits and have highly complex designs and processes. The problem.

A diode access device has been proposed as a driver for phase change memory cells. However, the ends of the diode formed using doped multi-twist may have an unacceptably high off-state current. The use of doped single crystals formed at both ends of the diode may permit a relatively suitable lower off-state current, but the ends of the diode formed by the doped single crystal germanium are equivalent. complex. It has been proposed to include a polycrystalline germanium in a terminal structure and a single crystal germanium in a terminal structure. See U.S. Patent No. 7,309,921. However, such a structure does not completely solve the problem of higher off-state current from the polysilicon terminal, nor is it proposed as a memory cell access device. See U.S. Patent No. 7,157,314.

Accordingly, it is desirable to provide a reliable access device that provides sufficient current when stylizing phase-changing memory cells while having a suitably low off-state current, and is at an acceptable manufacturing cost and compatible with high efficiency logic circuitry.

The present invention discloses a memory device including an access device having a PN junction, the PN junction being a first doped semiconductor region comprising a first conductivity type, and a different from the first conductivity type a second doped semiconductor region of a second conductivity type, a PN junction defined between the first doped semiconductor and the second doped semiconductor, wherein the first doped semiconductor region is formed by a single crystal semiconductor And the second doped semiconductor region comprises a polycrystalline semiconductor. In an embodiment of the invention, the doping concentration of the polysilicon region is higher than the doping concentration of the transistor region. The second doped semiconductor region is implemented by embedding in a via hole and penetrating an insulating layer, or patterning a patterned semiconductor and then covering an insulating layer.

In some embodiments, the first doped semiconductor region comprises a lightly doped P-type semiconductor, and the second doped semiconductor region comprises a more heavily doped N-type polycrystalline semiconductor region and has a doped The impurity concentration is higher than the doping concentration of the lightly doped P-type semiconductor; in other embodiments, the first doped semiconductor region comprises a lightly doped N-type semiconductor, and the second doped semiconductor region comprises a A more heavily doped P-type polycrystalline semiconductor region. The concentrated doped semiconductor region of the polysilicon has a doping concentration higher than a concentration of the lightly doped semiconductor region of the single crystal semiconductor such that the electrical junction is within the single crystal semiconductor when the junction is When turned off, the off-state current of the diode is thus greatly reduced. The concentrated doped polycrystalline semiconductor region may have a doping concentration which is more than 10 times the doping concentration (atom/cm ³ ) of the lightly doped single crystal semiconductor region, and more preferably greater than 100 times to 1000 Times. For example, the ^heavily doped semiconductor region has a doping concentration of about 10 ⁺¹⁷ to 10 ⁺¹⁹ /cm ³ , and the lightly doped semiconductor region has a doping concentration of 10 ⁺¹⁴ /cm ³ to 10 ⁺¹⁶ Between /cm ³ .

In some embodiments, the single crystal semiconductor is a single crystal germanium; in some embodiments, the polycrystalline semiconductor is a polycrystalline germanium.

In some embodiments, an electrically conductive cap layer is further included over the second doped semiconductor region, and in some such embodiments, the cap layer comprises a metal telluride.

In some embodiments, the second doped semiconductor region is automatically aligned with the first doped semiconductor region; in some embodiments, the second doped semiconductor region forms a cylinder at the first doped semiconductor Above the area.

In some embodiments, the memory device further includes a phase change memory element coupled to the second doped semiconductor region.

In another aspect, the present invention discloses a memory device including a first access line extending in a first direction, and a second access line covering the first access line and extending in a second direction, and a plurality of memories Each cell contains an access device and a memory material. The access device includes a PN junction defined between the first doped semiconductor region and the second doped semiconductor region, the first doped semiconductor region having the first conductivity type in which the first doped semiconductor region is formed a single crystal semiconductor substrate, wherein the first doped semiconductor region is formed on a doped semiconductor first access line, and the first doped semiconductor region is electrically connected to a first access line. A second doped semiconductor region has a second conductivity type different from the first conductivity type, and the second doped semiconductor region includes a polycrystalline semiconductor. The memory material is electrically connected to a corresponding second access line. In some embodiments. The memory material is a phase change memory material.

In some embodiments. The access device further includes an electrically conductive cap layer over the second doped semiconductor region, and in some embodiments, the electrically conductive cap layer comprises a metal telluride. The memory cell may further comprise a bottom electrode contacting the electrically conductive cover layer, in this embodiment the memory material contacts the bottom electrode. The bottom electrode can be omitted in some embodiments, such as using a hole-type memory cell having a hole opening to the cover layer to fill the programmable resistive material. In other embodiments, the memory material contacts the second semiconductor region.

In some embodiments, the diode further includes a thin barrier layer and can be located on the PN junction. The barrier layer prevents dopants from diffusing through the PN junction and enhances the effectiveness of the diode without obstructing the on-state current during operation of the device.

In some embodiments, the memory cell further comprises a top electrode, and in the present embodiment the memory material contacts the top electrode. In some embodiments the top electrode constitutes the first access line.

Another aspect of the invention discloses a method of fabricating a memory cell driver comprising: providing a single crystal semiconductor region having a first conductivity type; forming a second conductivity type (eg, N-well) with a conductive doped region The upper region of the semiconductor substrate is suitable for use as an access line; forming a lightly doped region of the first conductivity type (where the lightly doped system is used for doping with polycrystalline materials described below) The concentration is compared to the inner surface of the conductive doped region at and near; the isolation trench is defined to define a top diode region strip having an exposed surface; and a second dielectric material is deposited at the bottom diode Above the body region strip; forming a junction via hole (or contact opening) penetrating the second dielectric material to expose a region of the lightly doped region on the surface of the bottom diode region strip; and forming One of the second conductivity types is a more heavily doped polycrystalline material within the contact opening, the more heavily doped polycrystalline material contacting the region of the lightly doped region. The polycrystalline material may be deposited within the contact opening and then doped; or the polycrystalline material may be deposited in a suitable doping manner.

The semiconductor wafer may be constructed with the single crystal semiconductor region; or an epitaxial-single crystal single crystal semiconductor layer may be formed over the insulating layer on the wafer to form the single crystal semiconductor region.

In some embodiments, the method further includes forming an electrically conductive cap layer on the surface of the concentrated doped polycrystalline material.

Another aspect of the invention discloses a method for fabricating a memory cell driver, comprising: providing a single crystal germanium semiconductor substrate having a first conductivity type; forming a second conductivity type conductive doped region in the semiconductor An upper surface of the substrate; forming a lightly doped region of the second conductivity type in the lightly doped region in or near an upper surface of the conductive doped region, the lightly doped polysilicon material having a lower than the conductive dopant a doping concentration of the doping concentration of the impurity region; forming trench isolation to define an underlying driver region strip having an exposed surface; depositing one of the second conductivity types to concentrate the polycrystalline material in the dense blend On the surface of the heteropolycrystalline material; depositing an electrically conductive covering material on the surface of the concentrated doped polycrystalline material; patterning the covering material and the densely doped polycrystalline material to form a top surface component a lightly doped region on a surface of the bottom junction region strip; a second dielectric material deposited on the surface of the first dielectric material and the bottom junction region strip and the top diode element; and planarization The Two dielectric material and one of the exposed surface area of the top surface of the element.

Another aspect of the invention discloses a method for fabricating a memory cell driver, comprising: providing a single crystal germanium semiconductor substrate having a first conductivity type; forming a lightly doped region of the first conductivity type adjacent to An upper surface of the substrate; depositing a densely doped polysilicon material of the second conductivity type on a surface of the lightly doped region to form trench isolation to define a diode driving strip having an exposed surface; Patterning the more heavily doped polycrystalline material in another direction to isolate a second junction element and expose a lightly doped region adjacent the first conductivity type; forming a spacer adjacent to the second junction component Forming an electrically conductive covering material over the second junction member; performing an implantation step of the first conductivity type on the exposed lightly doped region of the first conductivity type to make it thicker Doping; depositing a second dielectric material over the surface of the first dielectric material and the second diode component.

In some embodiments of the method, a thin layer of barrier material (eg, SiO ₂ or SiN _x O _y ) is formed on the lightly doped region of the first conductivity type prior to depositing the polycrystalline semiconductor material; A thin barrier layer is on the PN junction. The barrier layer can inhibit diffusion of dopants through the PN junction and can enhance the performance of the diode.

Forming the memory array together with peripheral devices has several advantages. Deposition of a polycrystalline material, such as a polycrystalline semiconductor node of the diode array and a FET gate at the peripheral device. Basically, doping the crystalline semiconductor material of the memory array region; forming trench isolation; growing an oxide over the memory array region and the peripheral device region; patterning the oxide to form a gate of the peripheral device And removing the oxide from the memory array; and depositing the polycrystalline material and patterning the peripheral device region to form a gate and patterning the array region to form a polysilicon, a denser doped component of the access device. Next, an inter-layer dielectric layer is formed, and an opening is formed between the peripheral device region and the memory array region. The opening fills the conductive contact plug material like tungsten in the peripheral device region to complete the elements of the memory array memory cell. Thus a single polysilicon process can use both the more heavily doped polycrystalline element and the peripheral polycrystalline structure in the array. It can save substantial costs on the process. In this embodiment, the transistor gate structure of the peripheral circuit region of the device and the more heavily doped polysilicon device of the driver comprise individual features of a single polysilicon layer.

In contrast to forming a diode having two regions with a polycrystalline material, the first diode region forming a single crystalline semiconductor material can provide a memory cell with a significant reduction in turn-off current or leakage current. In accordance with the disclosed embodiments, the first diode region can be formed on the crystalline semiconductor wafer and the PN junction can be defined on the wafer surface. It does not need to etch the wafer to form the PN junction. By forming the second diode region of the polycrystalline semiconductor material, rather than using a single crystal semiconductor material, the process system can be simplified because one of the epitaxial steps of forming a single crystal material is avoided.

The following implementation of the present invention with reference to the drawings generally refers to specific structural embodiments and methods. The drawings depict the features of the embodiments and the relationship to other features, which are not the dimensions of the actual structure. For the sake of clarity of expression, various embodiments are illustrated in the various figures, and the correspondence between the various elements of the drawings is not specifically renumbered, although they are distinguishable between the various figures. At the same time, for the purpose of clearer expression, certain features that are not necessary for understanding the purpose of the present invention are not indicated in the drawings. The invention is not limited by the detailed description of the invention, and the embodiments and methods disclosed herein may be practiced with other features, elements, methods, and embodiments. The preferred embodiments of the invention are not limited in scope, but are defined by the scope of the claims. Those skilled in the art will also appreciate various equivalent variations in the embodiments of the invention.

1 is a simplified pictorial representation of a portion of a memory array 100 using a memory device and a diode access device as described herein. Alternatively, the access device, in addition to the diode, also includes a PN junction that can be used as a bipolar transistor. Each memory cell of the memory array 100 includes a diode access device and a memory component (represented by the variable resistor in FIG. 1), and the memory component can be set to one of a plurality of resistance states, and Thus, one or more bits of data can be stored.

The memory array 100 includes a plurality of word lines 130 including word lines 130a, 130b, and 130c extending in parallel with the first direction, and a plurality of bit lines 120 including bit lines 120a, 120b extending in parallel with the second direction. 120c, wherein the second direction is perpendicular to the first direction. The word line 130 and the bit line 120 are arranged in such a manner that a given word line 130 and a given bit line 120 straddle each other instead of actually intersecting each other.

The memory cell 115 represents the memory cell of the memory array 100. The memory cell 115 includes a diode access device 121 and a memory device 160 arranged in series; the diode access device 121 is electrically coupled to the word line 130b, and the memory device 160 is electrically coupled to the memory device 160. Bit line 120b (and vice versa).

The reading and writing of the memory cells 115 of the memory array 100 can be achieved by applying appropriate voltages and/or currents to the corresponding word lines 130b and bit lines 120b to induce current through the selected memory cells 115. The magnitude and duration of the applied voltage and current depend on the operation being performed, such as a read operation or a write operation.

In a reset (or erase) operation of the memory cell 115 having the memory component 160 including the phase change material, a reset pulse is applied to the corresponding word line 130b and the bit line 120b to cause the phase change material to be active. The region is converted to an amorphous state by which the resistance within the range of resistance values associated with the reset state is set. The reset pulse is a relatively high energy pulse sufficient to raise at least the active region temperature of the memory element 160 above the transition (crystallization) temperature of the phase change material and above the melting temperature such that at least the active region is liquid. Then, the reset pulse is quickly terminated, resulting in a relatively fast cooling time, allowing the active region to rapidly cool below the transition temperature so that the active region can be stabilized to an amorphous state.

In a set (or stylized) operation of the memory cell 115 having the memory element 160 including the phase change material, applying a stylized pulse of appropriate size and duration to the corresponding word line 130b and bit line 120b is sufficient Increasing the temperature of at least a portion of the active region above the transition temperature and causing a transition of a portion of the active region from an amorphous state to a crystalline state, the conversion reducing the resistance of the memory device 160 and setting the memory cell 115 to a desired state.

Applying a suitable size and duration read pulse to the corresponding word line for one of the data values stored in the memory cell 115 having the memory element 160 including the phase change material 160 (or sensing) operation 130b and bit line 120b induce current to flow, which does not cause memory element 160 to change in resistance state. The current flowing through the memory cell 115 depends on the resistance of the memory element, that is, the value of the data stored in the memory cell 115.

2A and 2B show an embodiment of a portion of a memory cell array 100 in which the second multi-crystal region of the diode has the shape of an island, as depicted in cross-section. 2A is a direction along a bit line 120, and 2B is a direction along a word line 130. Figure 2C illustrates a form of forming a PN junction of the present invention having a depleted region mostly located in a crystalline region having a lower doping concentration. This form will have a smaller leakage current in the off state, which can improve the operation of the memory. Please refer to FIG. 2C, which uses the same reference numerals as in FIGS. 2A and 2B, and the illustrated diode includes a dense doped N+ region 216 implanted with polysilicon, and a use list. The lighter doped P-region 214 is deposited by the wafer. A physical boundary 215 is defined between the densely doped N+ region 216 and the lighter doped P-region 214 to define the PN junction. The width W _j of the PN junction is the sum of the depletion region 215-N and the depletion region 215-P. In the figure, their respective widths are denoted as W _{N and} W _P , and the W _P system is much larger than W _N . The widths of the depletion regions W _N and W _P are inversely proportional to the respective doping concentrations at zero bias, as is known below for the charge storage equation:

qN _A W _P =qN _D W _N

Where q is the charge, the concentration of the NA receptor (p-type doping), and the concentration of the ND system (n-type doping), while the ND system is much larger than NA, on the p-type material The depletion region is much larger than the depletion region on the n-type material.

Therefore, in the embodiment, the concentration of the N-type doping in the densely doped N+ region 216 is more than 100 times higher than the P-type doping concentration of the lightly doped P-region 214, and the width of the W _P is wider. It will also be more than 100 times larger than the width of W _N . The majority of the PN junction defined by the depletion region is present in the crystal portion 214 of the diode, and substantially the off current characteristic is primarily determined by the behavior of the crystal portion 214. The concentrated doped polycrystalline semiconductor region may be allowed to have a doping concentration of more than 10 times the doping concentration of the lightly doped single crystal semiconductor region, and more preferably greater than 100 times to 1000 times. For example, the ^heavily doped semiconductor region has a doping concentration of about 10 ⁺¹⁷ to 10 ⁺¹⁹ /cm ³ , and the lightly doped semiconductor region has a doping concentration of 10 ⁺¹⁴ /cm ³ to 10 ⁺¹⁶ Between /cm ³ .

FIG. 2C also illustrates that the crystal region 214 has a single crystal of an interface, the PN junction is formed thereon, and integrated with a densely doped access line 212, which is further improved in FIGS. 2A and 2B. Clearly illustrated. The top of the crystal region 214 includes a protrusion on a surface of the single crystal adjacent to the access device, and the depth is greater than the depth of the depletion region, and the depth of the depletion region is greater than that in the embodiment. W _{P of the} -type crystalline material. Thus, the depletion region formed in the crystal region 214 is isolated by the trench 225 adjacent to the diode within the single crystal body, the depth of which is greater than the width of the depletion region of the crystalline material. This way the junction of the junction and the adjacent junction can be placed closer together. The trench may be formed by over-etching to automatically align the polycrystalline region when patterning the polysilicon region 216, or using a sidewall spacer as an etch mask on the polysilicon region, as depicted in FIG. 18B Show. Of course, other techniques can be used to pattern the surface of the single crystal as the access line and the single crystal element.

Therefore, it is possible to achieve the lower leakage current on the single crystal junction or to substantially complete the structure of the present invention. However, forming a polycrystalline dense doped region 216 provides manufacturing convenience without the substantial cost of increasing leakage current.

Referring to FIGS. 2A and 2B, the memory cell 115 includes a first doped semiconductor region 213 having a first conductivity type, and a second doped semiconductor region over the first doped semiconductor region 213. 216. The second doped semiconductor region 216 has a second conductivity type different from the one of the first conductivity types. The first doped semiconductor region 213 includes a conductive doped region 212 covered by a lightly doped region 214. A PN junction 215 is defined between the lightly doped region 214 of the first doped semiconductor region 213 and the second doped semiconductor region 216. As shown in the illustrated embodiment, the first doped semiconductor region is a P-type semiconductor; the conductive doped region is labeled "P+", and the lightly doped region is labeled "P-". As shown in the illustrated embodiment, the second doped semiconductor region is labeled "N+" as a more heavily doped N-type semiconductor.

The first doped semiconductor region 213 is formed by doping the single crystal semiconductor substantially, whereby the first doped semiconductor region is a single crystal semiconductor. The second doped semiconductor region is a doped deposition polysilicon material. Therefore, the dipole system is composed of first and second semiconductor regions, and defines a PN junction therein; the first semiconductor region is formed by a single crystal semiconductor, and the second semiconductor region is composed of a plurality of A crystalline semiconductor is formed.

The doped single crystal semiconductor region may be formed by the wafer itself. Alternatively, the doped single crystal semiconductor region may be coated on a single insulator (SOI) substrate (eg, a germanium-insulator-germanium substrate).

The memory cell 115 includes a conductive cap layer 218 on the second doped semiconductor region 216. The first and second doped semiconductor regions 213, 216 and the conductive cap layer are constructed with a multilayer stack to define a diode. 121. In the illustrated embodiment, the conductive cap layer 218 comprises a metal telluride containing titanium, tungsten, cobalt, nickel, and niobium, which are formed using a self-aligned metal telluride process. It is also possible to use a patterned metal telluride process, generally implemented in tungsten germanium. The conductive cap layer 218 helps maintain the uniformity of an electric field applied to the first and second doped semiconductor regions 213, 216 during operation, and by providing a contact surface that is comparable to the first and second doping The semiconductor material of the hetero semiconductor regions 213, 216 has a higher conductivity. The conductive cap layer 218 also provides a low resistance ohmic contact between the diode 121 and the covered memory component 160. In addition, during the process of fabricating the memory cell array 100, the conductive cap layer 218 can serve as a protective etch stop layer for the second doped semiconductor region 216. Further, the metal halide is used to form the conductive cap layer, which is formed between the regions 218a, 218b on the surface of the denser doped region 212 and the memory cells. The conductive cap layer in the regions 218a, 218b removes a minority carrier from the denser doped region and improves the conductivity of the word line formed in the region 212. At the same time, the conductive cap layer in the region 218a, 218b provides a low resistance ohmic contact between the conductive plug 224 and the region 212.

As shown in the embodiments of FIGS. 2A and 2B, the width of the lightly doped single crystal semiconductor region 214 under the densely doped polycrystalline semiconductor region 212 is greater than the width of the second doped semiconductor region 216. As defined by spacers formed adjacent to the second doped semiconductor region 216. The conductive plug 224, typically tungsten and/or other material, contacts the contact opening of the densely doped semiconductor region 212 on the side of the second doped semiconductor region 216 and extends upwardly into contact with the upper structure, such as The description shown below or below. In an alternate embodiment, the conductive plug does not need to be between each of the memory cells of Figure 2B. Conversely, in some embodiments, such a plug can be provided in a less compact configuration, such as one memory cell at a time, four memory cells per interval, eight memory cells per interval, looking at the top structure or other The considerations in terms are determined.

Additionally, a thin barrier layer (not shown) may be selectively located between the PN junction, that is, between the lightly doped semiconductor region 214 and the more heavily doped semiconductor region 216. The barrier layer prevents dopants from diffusing through the PN junction and enhances the effectiveness of the diode. For example, a suitable barrier layer can be cerium oxide (SiO ₂ ) or cerium oxynitride (SiN _x O _y ); it can have a thickness between 5 and 25 angstroms, such as about 10 angstroms.

In Figure 2B, arrow 219 shows that the current direction is passed through the PN junction 215 through an upper memory element (not shown in the figure) through the diode and up and through the contact via, and finally Up to an upper access line (not shown in this figure), the densely doped semiconductor region 212 performs an internal substrate word line function over a finite length. As described above, the length between the contact and the inner substrate region word line can be extended in the embodiment using the metal halide regions 218a, 218b on the surface. As shown in the figure, since the width of the lightly doped semiconductor region 214 is greater than the width of the second doped semiconductor region 216, the current needs to be first passed before the relatively rich doped semiconductor region 212 is to be passed upward. The di-doped semiconductor region 216 passes through the lightly doped semiconductor region 214 under the spacer.

As will be discussed in greater detail below, the access diode has an island-shaped second region (generally shown in Figures 2A and 2B) when the second region is automatically aligned to the isolation trench. The first diode region strip 313 defined by 310 (Fig. 3) may or may not be aligned with the first diode region strip 413 defined by the isolation trench 410 (Fig. 4), in various Embodiments can be achieved with an optional process step.

Referring to the auto-alignment configuration of FIG. 3, the memory cell includes a first doped semiconductor region 313 having a first conductivity type, and a second doped semiconductor region 316 over the first doped semiconductor region 313. And the second doped semiconductor region 316 has a second conductivity type different from one of the first conductivity types. The first doped semiconductor region 313 includes a densely doped region 312 covered by a lightly doped region 314. A PN junction 315 is defined between the lightly doped region 314 of the first doped semiconductor region 313 and the second doped semiconductor region 316. The second doped semiconductor region 316 is automatically aligned, and the width of the second doped semiconductor region on the PN junction 315 is the same as the width of the lightly doped semiconductor region 314.

Referring to the non-automatic alignment configuration of FIG. 4, the memory cell includes a first doped semiconductor region 413 having a first conductivity type, and a second doped semiconductor region 416 at the first doped semiconductor region 413. Upper, and the second doped semiconductor region 416 has a second conductivity type different from one of the first conductivity types. The first doped semiconductor region 413 includes a densely doped region 412 covered by a lightly doped region 414. A PN junction 415 is defined between the lightly doped region 414 of the first doped semiconductor region 413 and the second doped semiconductor region. Because in this configuration, the second doped semiconductor region 416 is not self-aligned, the width of the second doped semiconductor region on the PN junction 415 is greater than the width of the lightly doped semiconductor region 414.

5A, 5B, 5C; 6A, 6B; 7A, 7B; 8A, 8B and 9A, 9B are diagrams showing various embodiments of the memory cell of the present invention, various of the memory cells The memory element is configured to be formed over the access diode and has an island-shaped second region that is automatically aligned with the first diode region strip.

Referring to Figures 5A, 5B, a conductive plug 320 is formed in contact with the cover layer 318 to increase the height of the cover array of memory elements. A dielectric layer 510 supports the array of memory elements. In this embodiment, the memory element 160 includes a bottom electrode in electrical contact with the second region of the diode, a memory material in electrical contact with the bottom electrode, and a top electrode over the memory material. Electrically coupled to the upper access line (bit line) 120b. In such a configuration, the bottom electrode 532 is formed and extends through a hole in the dielectric layer. The bottom electrode 532 contacts the underlying cap layer 318 and contacts a covered island of memory material 530 formed over the dielectric layer 510, and each memory material island is covered by a top electrode 534. The top electrode is coupled to the access line 120b by means of a conductive plug 522. A bottom region of each memory cell phase change material contacts the bottom electrode 532 and an active region 533 adjacent to the bottom electrode is a region in which the memory material of the memory element is induced to transition between at least two solid states. .

For example, the holes in the dielectric layer 510 can be formed by a "keyhole", and the required methods, materials, and processes are disclosed in U.S. Patent Application Serial No. Patent No. 11/855,979, "Phase Change Memory Cell in Via Array with Self-Aligned, Self-Converged Bottom Electrode and Mehtod for Manufacturing" is incorporated herein by reference. For example, the dielectric layer 510 may be formed on the top surface of the access circuit, and then an isolation layer and a sacrificial layer are sequentially formed. Next, a mask having an opening close to or equal to the smallest feature size in the process is formed on the sacrificial layer, the opening being located above the plug 320 or the diode cap layer 318. Then, the spacer layer and the sacrificial layer are selectively etched using the mask, thereby forming a contact opening in the isolation layer and the sacrificial layer and exposing a top surface of the dielectric layer 510. Next, the mask is removed, and a selective undercut etch is performed at the contact opening such that the isolation layer is etched leaving the sacrificial layer and dielectric layer 510. Next, a fill material is formed in the contact opening, and an auto-aligned void is created within the fill material formed in the contact opening due to the undercut etching process. Then, an anisotropic etching process is performed on the filling material to open the hole, and etching is continued until the dielectric layer 510 region is exposed under the hole, thereby forming a sidewall spacer, which is included in the opening contact opening. Filling material inside. The sidewall spacer has an opening size that is substantially determined by the size of the aperture and can therefore be less than the minimum feature size of a lithography process. Next, the sidewall spacer is used as an etch mask to etch the dielectric layer 510, thereby forming an opening in the dielectric layer having a size smaller than the minimum feature size. Next, an electrode layer is formed within the opening of the dielectric layer 510. Next, a planarization process such as chemical mechanical polishing CMP is performed to remove the isolation layer and the sacrificial layer and form the first electrode 532 (or bottom electrode) to obtain the illustrated structure.

Referring specifically to FIG. 5B, the first heavily doped region 312 (which is richerly doped enough to be a conductor and has a deuterated surface region) is electrically coupled to the upper word by conductive plugs 224, 526. Yuan line 130b. In the embodiment illustrated in FIG. 5B, the conductive plug 320 and the conductive plugs 224, 526 have tungsten. Other conductive materials can also be used.

FIG. 5C illustrates an alternate embodiment in which the word line 130b is coupled to the doped region 312 having a metal halide surface periodically or only at the periphery of the array. Thus, the conductive plugs 324, 526, shown in Figure 5B, are deleted in the embodiment of Figure 5C. Except for this, the 5Cth picture is the same as the 5Bth figure.

The bottom electrode 532 may comprise, for example, titanium nitride or tantalum nitride. Titanium nitride is preferred because it has good contact with the GST of the memory material (as described above), which is a commonly used material in semiconductor processes, and is at a high temperature of GST conversion (typically between 600 and 700). °C) provides good diffusion barriers. Alternatively, the bottom electrode 532 may be aluminum titanium nitride or aluminum nitride or more, for example, one or more elements selected from the group consisting of titanium, tungsten, molybdenum, aluminum, lanthanum, copper, platinum, rhodium, iridium. , nickel, oxygen and helium and combinations thereof.

In the illustrated embodiment, the dielectric layer 510 surrounding the bottom electrode and under the memory element comprises tantalum nitride. The dielectric material of the dielectric layer 510 can be selected for hole formation and by etching through an opening in a temporary covering material (e.g., tantalum oxide).

The top electrode 534 and the bit line 120 can comprise any material as used in reference to the bottom electrode 532 described above.

The dielectric material that continuously fills the isolation trench can comprise, for example, yttria, cerium oxide, and any material sufficient to electrically isolate the ridge of the diode.

In the illustrated embodiment the memory element 530 comprises a phase change material. The phase change element 530 can comprise, for example, one or more of the following group materials: ruthenium, osmium, iridium, selenium, indium, titanium, gallium, antimony, tin, copper, palladium, lead, silver, sulfur, antimony, oxygen, phosphorus. , arsenic, nitrogen and gold.

An embodiment of the memory cell of the present invention comprises a phase change memory material comprising a chalcogenide material and other materials. The chalcogenide includes any of the following four elements: oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of Group VIA of the Periodic Table of the Elements. Chalcogenides include the combination of a chalcogen element with a more positively charged element or radical. The chalcogenide alloy includes a combination of a chalcogen compound with other substances such as a transition metal or the like. The monochalcogenide alloy typically comprises more than one element selected from Group IVA of the Periodic Table of the Elements, such as germanium (Ge) and tin (Sn). Generally, the chalcogenide alloy includes one or more of the following elements: bismuth (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change-based memory materials have been described in the technical documentation, including the following alloys: gallium/germanium, indium/bismuth, indium/selenium, yttrium/niobium, lanthanum/niobium, lanthanum/niobium/niobium, indium/niobium /碲, gallium/selenium/bismuth, tin/bismuth/niobium, indium/bismuth/niobium, silver/indium/锑/碲, 锗/tin/锑/碲, 锗/锑/selenium/碲, and 碲/锗/锑 / sulfur. In the 锗/锑/碲 alloy family, a wide range of alloy compositions can be tried. This component can be represented by the following characteristic formula: Te _a Ge _b Sb _100-(a+b) , wherein a and b represent the percentage of each atom when the total number of atoms of the constituent elements is 100%. One researcher described the most useful alloys in that the average enthalpy concentration contained in the deposited material is well below 70%, typically below 60%, and the bismuth content in the general type alloy ranges from the lowest. 23% up to 58%, and the best line is between 48% and 58%. The concentration of cerium is above about 5% and its average range in the material ranges from a minimum of 8% to a maximum of 30%, typically less than 50%. Most preferably, the concentration range of lanthanum is between 8% and 40%. The main component remaining in this ingredient is hydrazine. (Ovshinky '112 patent, columns 10-11) Special alloys evaluated by another investigator include Ge ₂ Sb ₂ Te ₅ , GeSb ₂ Te ₄ , and GeSb ₄ Te ₇ . (Noboru Yamada, "Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording", SPIE v . 3109 , pp. 28-37 (1997)) More generally, transition metals such as chromium (Cr ), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and mixtures or alloys thereof, may be combined with niobium / tantalum / niobium to form a phase change alloy including Has a programmable resistance property. A special example of a memory material that can be used is described in columns 11-13 of the Ovshinsky '112 patent, examples of which are incorporated herein by reference.

Chalcogenides and other phase change materials are doped with impurities to adjust conductivity, switching temperature, melting point, and other properties used in doped chalcogenide memory elements. Representative impurities used in the doped chalcogenide include nitrogen, helium, oxygen, cerium oxide, cerium nitride, copper, silver, gold, aluminum, aluminum oxide, cerium, cerium oxide, cerium nitride, titanium, titanium oxide. . See U.S. Patent No. 6,800,504 and U.S. Patent Application Serial No. 2005/0029502.

The phase change alloy can be switched between the first structural state in which the material is in a generally amorphous state and the second structural state in a general crystalline state in the memory cell active channel region. These materials are at least bistable. The term "amorphous" is used to refer to a relatively unordered structure that is more unordered than one of the single crystals, with detectable features such as higher resistance values than crystalline states. The term "crystalline" is used to refer to a relatively ordered structure that is more ordered than amorphous and therefore includes detectable features such as lower resistance than amorphous. Typically, the phase change material can be electrically switched to all detectable different states between the fully crystalline state and the fully amorphous state. Other materials that are affected by changes in amorphous and crystalline states include atomic order, free electron density, and activation energy. This material can be switched to a different solid state, or can be switched to a mixture of two or more solids, providing a gray-scale portion from amorphous to crystalline. The electrical properties in this material may also change.

The phase change alloy can be switched from one phase to another by applying an electrical pulse. Previous observations indicate that a shorter, larger amplitude pulse tends to change the phase of the phase change material to a substantially amorphous state. A longer, lower amplitude pulse tends to change the phase of the phase change material to a substantially crystalline state. The energy in the shorter, larger amplitude pulses is large enough to disrupt the bonding of the crystalline structure, while the time is short enough to prevent the atoms from realigning into a crystalline state. A suitable curve depends on experience or simulation, especially for a particular phase change alloy. The phase change material disclosed herein is also commonly referred to as GST, it being understood that other types of phase change materials may also be used. The phase change read only memory (PCRAM) used in the present invention is Ge ₂ Sb ₂ Te ₅ .

Other programmable resistive memories that can be used in other embodiments of the invention include other materials that use different phase changes to determine resistance or other materials that can change their resistance state using current pulses, such as in resistive random access memory. The material of the body (RRAM), such as a metal oxide, comprises tungsten oxide (WO _x ), NiO, Nb ₂ O ₅ , CuO ₂ , Ta ₂ O ₅ , Al ₂ O ₅ , CoO, Fe ₂ O ₃ , HfO ₂ , TiO. ₂ , SrTiO ₃ , SrZrO ₃ and (BaSr)TiO ₃ . In addition, the material used in the magnetoresistive random access memory (MRAM) includes at least CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO ₂ ^, MnOFe ₂ O ₃ , One of FeOFe ₂ O ₅ , NiOFe ₂ O ₃ , MgOFe ₂ , EuO, and Y ₃ Fe ₅ O ₁₂ . Reference may be made to U.S. Patent Publication No. 2007/0176251 "Magnetic Memory Device and Method of Fabricating the Same", which is incorporated herein by reference. Further embodiments include solid phase electrolytic materials used to stylize metalized memory cells (PMC) or nano-ion memory cells such as silver doped strontium sulfide electrolytes and copper doped strontium sulfide electrolytes. See, for example, NE Gilbert et al., Solid-State Electronics 49 (2005) pp. 1813-1819, "A macro model of programmable metallization cell device", which is incorporated herein by reference.

An exemplary method for forming a chalcogenide may be a PVD sputtering or a magnetron sputtering method in which the reaction gas is argon gas, nitrogen gas, and/or helium gas at a pressure of 1 mTorr to 100 mTorr. This deposition step is generally carried out at room temperature. A collimator with an aspect ratio of 1 to 5 can be used to improve its filling performance. In order to improve the filling performance, a DC bias of tens to hundreds of volts can also be used. On the other hand, it is also feasible to combine DC bias and collimator at the same time.

It is sometimes necessary to perform a post-deposition annealing treatment in a vacuum or in a nitrogen atmosphere to improve the crystalline state of the chalcogenide material. The temperature of this annealing treatment is typically between 100 ° C and 400 ° C and the annealing time is less than 30 minutes.

Alternatively, the chalcogenide material can be formed by chemical vapor deposition techniques.

6A, 6B illustrate another embodiment of a memory cell array, wherein the memory element is formed on the access diode having an island-type second region aligned with the first diode region strip . The structure is similar to the structure of FIGS. 5A, 5B except that there is no conductive plug to separate the cover layer 318 from the bottom electrode 532 and the dielectric layer 510 surrounding the bottom electrode and the memory element 530. As shown in FIGS. 5A and 5B, the bottom electrode 532 is formed in and extends through a hole of the dielectric layer. The bottom electrode 532 contacts the underlying cap layer 318 and contacts a covered island of memory material 530 formed over the dielectric layer 510, and each memory material island is covered by a top electrode 534. The top electrode is coupled to the access line by means of a conductive plug. A bottom region of each memory cell phase change material contacts the bottom electrode 532 and an active region 533 adjacent to the bottom electrode is a region in which the memory material of the memory element is induced to transition between at least two solid states. .

With particular reference to FIG. 6B, the first heavily doped region 312 is electrically coupled to the upper word line 130b via a conductive plug (not shown) at a location of certain segments of the region 312 (not shown). Alternatively, the conductive plug can be positioned between each of the memory cells depicted in FIG. 5B.

7A and 7B illustrate another embodiment of a memory cell array, wherein the memory element is formed on the access diode having an island-type second region aligned with the first diode region strip. . The structure is similar to the structure of FIGS. 6A, 6B except that the memory material is a strip 730 instead of an island; and the top electrode is also formed as a strip 734 overlying the memory material and serves as One yuan line. As illustrated in the illustrations of FIGS. 7A and 7B, the bottom electrode 532 is formed in and extends through a hole in the dielectric layer. The bottom electrode 532 contacts the underlying cap layer 318 and contacts a strip of memory material 730 formed over the dielectric layer 510, and each strip of memory material is covered by a top electrode strip 734. A memory region of the memory strip 730 is induced to transition between at least two solid states in a small area of each memory cell phase change material that contacts the bottom electrode 532 and an active region 533 that is in contact with the bottom electrode. region.

With particular reference to FIG. 7B, the first heavily doped region 312 is electrically coupled to the upper word line 130b via a conductive plug (not shown) at a location of some of the regions 312 (not shown). Alternatively, the conductive plug can be positioned between each of the memory cells depicted in FIG. 5B.

8A, 8B illustrate another embodiment of a memory cell array, wherein the memory element is formed on the access diode having an island-type second region aligned with the first diode region strip. . In an embodiment, the memory material is a strip 830 rather than an island; and the top electrode is also formed as a strip 834 overlying the memory material and acting as a one-dimensional line. Moreover, in the present embodiment, there is a hole in the dielectric layer 810, but there is no separate bottom electrode. Rather, in this embodiment a portion of the memory material extends from the strip 830 through the aperture as indicated by reference numeral 832 and is coupled to the cover layer 318 at the top position of the diode stack 121.

With particular reference to FIG. 8B, the first heavily doped region 312 is electrically coupled to the upper word line 130b via a conductive plug (not shown) at a location of certain segments of the region 312 (not shown). Alternatively, the conductive plug can be positioned between each of the memory cells depicted in FIG. 5B.

9A and 9B illustrate another embodiment of a memory cell array, wherein the memory element is formed on the access diode having an island-shaped second region aligned with the first diode region strip. . In an embodiment, there are holes in the dielectric layer 910 (also as shown in Figures 8A, 8B), but there is no separate bottom electrode. However, there is no strip of memory material, and the top electrode 934 (also referred to as the bit line 930) is directly overlying the dielectric layer 910. The memory element of each memory cell is formed only within the hole as indicated by reference numeral 932 and is coupled to the cover layer 318 at the top position of the diode stack 121 and over the covered top electrode 934.

With particular reference to FIG. 9B, the first heavily doped region 312 is electrically coupled to the upper word line 130b via a conductive plug (not shown) at a location of certain segments of the region 312 (not shown). Alternatively, the conductive plug can be positioned between each of the memory cells depicted in FIG. 5B.

10A, 10B; 11A, 11B; 12A, 12B are diagrams showing various embodiments of the memory cell of the present invention, the memory cells of which are arranged on the access diode and There is an island-type second region that is not automatically aligned to the first diode region strip.

10A, 10B illustrate another embodiment of a memory cell array, wherein the memory element is formed on the access diode with an island-type second region that is not aligned with the first diode region. article. The structure is similar to the structure of FIGS. 8A, 8B except that the dielectric filling layer 1010 not only allows the memory material strip 1030 to be formed thereon but also surrounds at least the upper island portion of the diode stack 121, which includes the The second doped semiconductor 416 and the cap layer 418. Also like the embodiment of Figures 8A, 8B, there is no separate bottom electrode. Rather, in this embodiment, there is a hole in the dielectric fill layer 1010, but a portion of the memory material extends from the strip 1030 through the hole as indicated by reference numeral 1032 and is coupled to the cover layer 418. This top position of the diode stack 121.

With particular reference to FIG. 10B, the first heavily doped region 412 is electrically coupled to the upper word line 130b via a conductive plug (not shown) at a location of certain segments of the region 312 (not shown). Alternatively, the conductive plug can be positioned between each of the memory cells depicted in FIG. 5B.

11A, 11B illustrate another embodiment of a memory cell array, wherein the memory element is formed on the access diode having an island-type second region that is not aligned with the first diode region. article. In the present embodiment, the dielectric filling layer 1010 surrounds at least the upper island portion of the diode stack 121 , and includes the second doped semiconductor 416 and the cap layer 418 . The bottom electrode 1132 is formed and extends through a hole in the dielectric layer 1110. The bottom electrode 532 contacts the underlying cap layer 418 and contacts a covered memory material island 1130 formed over the dielectric layer 1110, and the column of memory material islands is covered by a top electrode strip 1134. It is used as a meta-line. The bottom electrode 1132 is contacted in a small area of each memory cell phase change material and an active region 1133 adjacent to the bottom electrode is in contact with the bottom electrode. The memory material island 1130 of the memory element is induced to transition between at least two solid states. Area.

With particular reference to FIG. 11B, the first heavily doped region 412 is electrically coupled to the upper word line 130b via a conductive plug (not shown) at a location of certain segments of the region 312 (not shown). Alternatively, the conductive plug can be positioned between each of the memory cells depicted in FIG. 5B.

12A and 12B illustrate another embodiment of a memory cell array in which the memory element is formed on the access diode with an island-shaped second region covering the first diode region strip. In this embodiment, as in the embodiment shown in FIGS. 11A and 11B, a dielectric filling layer 1210 surrounds at least the upper island portion of the diode stack 121, and includes the second doped semiconductor 416 and The cover layer 418, and the memory material is formed as an island 1230 instead of a strip; and the top electrode is also formed as a strip 1234 covering the memory material as a one-dimensional line. In the present embodiment, however, there is a hole in the dielectric layer 1210, but there is no separate bottom electrode. Instead, in this embodiment, a portion of the memory material extends from the island 1230 through the aperture as indicated by reference numeral 1232 and is coupled to the cover layer 418 at the top position of the diode stack 121.

Referring to the portion of FIG. 12B, the first heavily doped region 412 is electrically coupled to the upper word line 130b via a conductive plug (not shown) at a location of certain segments of the region 312 (not shown). Alternatively, the conductive plug can be positioned between each of the memory cells depicted in FIG. 5B.

Figures 13 through 20C illustrate the fabrication of an access diode having an island-type second region that is automatically aligned to the process steps of one of the first diode strip embodiments.

A semiconductor substrate (typically in the form of a semiconductor wafer, such as a wafer) is provided. In this embodiment, the substrate is a P-type semiconductor, forming an N-well 1310, and then doping the wafer to provide a relatively dense doped region, which is of the same conductivity type (in this embodiment) Covered by one of the P-types relative to the lightly doped region. This result is shown in Figure 13. In the figure, the relatively densely doped region 1312 is labeled "P+" and the relatively lightly doped region 1314 is labeled "P-".

Thereafter, a polycrystalline semiconductor material layer 1316 is formed over the lightly doped region 1314, the polycrystalline semiconductor material (typically polycrystalline germanium) being more heavily doped than the doped concentration of the lightly doped region, and having Different from the conductivity type of the lightly doped region under the substrate. This result is shown in Figure 14. In the figure, the relatively densely doped poly layer 1316 is labeled "N+"

In addition, a barrier layer required for the PN junction may be formed by epitaxial or deposition of a dielectric layer in the exposed lightly doped germanium region 1314 prior to forming the polycrystalline cap layer 1316. . For example, a suitable barrier layer can be cerium oxide (SiO2) or cerium oxynitride (SiNxOy); it can have a thickness between 5 and 25 angstroms, such as about 10 angstroms.

Next, an isolation trench is formed so as to be ridge-shaped by a dielectric layer 1530, as shown in FIGS. 15A, 15B, and 15C. Each ridge comprises a strip of relatively heavily doped crystalline semiconductor material 1312 (P+) overlying the N-well and covered by a strip of relatively lightly doped crystalline semiconductor material 1313 (P-). The collection becomes a first region 113 which is covered by a relatively heavily doped (different type) polycrystalline semiconductor material strip 1316 (N+).

Next, a mask is formed over the ridge, and the dielectric layer is between the ridges, as depicted in FIG. The mask is patterned into strips 1612 across the strip of relatively densely doped polycrystalline material 1316.

Next, an etching process is performed to remove the exposed strip of relatively densely doped polycrystalline material (and the exposed dielectric layer material) and the mask is removed, the results of which are shown in Figures 17A, 17B, and 17C. The etch stops at the surface of the relatively lightly doped region 1314 (P-) such that the configuration is comprised of relatively densely doped polysilicon islands 1716 on the first region 1313. In embodiments where the spacing between the N+ regions 1716 is small, this step includes over-etching to etch the surface past the lightly doped germanium region 1314 and is greater than the depth of the PN junction (ie, greater than the width of the hollow region of the 2C pattern). W _P ) to isolate adjacent depleted regions, this over-etching process is shown in FIG. 18, but the over-etching process can be applied to any embodiment including closely packed cells, and other alignment processes can be used. Example.

Thereafter, as shown in FIGS. 18A, 18B, and 18C, spacers 1810 are formed on the sidewalls of the relatively densely doped polysilicon islands 1716. The spacer 1810 shields a narrow range of regions of the relatively lightly doped crystalline semiconductor material strip 1314 (P-) adjacent to the relatively densely doped polysilicon island 1716, the width of which is determined by the width of the spacer 1810. The remaining area 1816 of the relatively lightly doped crystalline semiconductor material strip 1314 is exposed.

Thereafter, a concentrated doping process of the bare strip of lightly doped crystalline semiconductor material is performed, and the results are shown in Figures 19A, 19B, and 19C. The region 1512, which is now below the exposed surface 1816 of the ridge of the strip of crystalline semiconductor material 1313, is heavily doped in the same manner as the relatively densely doped crystalline semiconductor material strip 1312 (P+) on the N-well.

Next, as the same conductive cap layer 2018, for example, the foregoing metal germanide formed on the relatively dense doped polysilicon island 1716 and formed on the relatively densely doped crystalline semiconductor material 1512, the result is as shown in Figs. 20A, 20B. , shown in Figure 20C. This completed diode structure (see also Figures 2A, 2B, 3) can now be prepared to form subsequent memory elements thereon, the details of which are detailed below.

21A through 25C show an embodiment of a method of fabricating an access diode having an island-type second region that is not aligned with the first diode region strip.

As in the example of the embodiment of Figures 13 to 20C, a semiconductor substrate (generally in the form of a semiconductor wafer, such as a wafer) is provided. In this embodiment, the substrate is a P-type. The semiconductor, an N-type well 2110 is formed in any of the array regions, and the N-type well and the P-type well are formed in a portion of the peripheral region. In Fig. 21A, a peripheral active region 2129 is in an N-type well, and then the wafer is doped in any of the array regions to provide a relatively thick layer covered by a lightly doped region (e.g., P-type) of the same conductive form. Doped area. In these illustrations, the relatively heavily doped region 2112 is labeled "P+" and the lightly doped region 2114 is labeled "P-." An isolation trench is simultaneously formed in the array and the peripheral region to generate a ridge separated by the dielectric layer 2130, as shown in FIGS. 21A, 21B, and 21C. In the active region, for example, it is shown in FIG. 21C in a peripheral region of the oblique line. In the region 2129, conversely, it will be understood that the transistors in the peripheral region of the device are used for logic and other purposes, and have a complex layout, each ridge in the array including a covered N-well The relatively densely doped crystalline semiconductor material (2112, P+) is covered by the relatively lightly doped crystalline semiconductor material (2114, P-). The above components collectively form a first diode region 2113 which forms one of the entire doped crystalline semiconductor material. Although not shown in the drawings, a metal halide sidewall may be formed to improve the conductivity of a conductor composed of a P-type strip of material in the ridge. The foregoing steps may be performed by etching an etch-filled material in an embodiment similar to that of FIG. 21A. Portion 2130 is achieved by exposing the sides of regions 2114 and 2112, followed by deposition of a metal telluride precursor over the exposed sides and annealing to create a germanium structure. Thereafter, the remaining metal halide precursor on the substrate is removed from the automatically aligned metal halide element on the side of the ridge. Typical metal halide precursors include metals or combinations of metals such as cobalt, titanium, nickel, molybdenum, tungsten, rhenium, and platinum. Metal halide precursors may also include metal nitrides or other metal composites. The metal telluride strip (not shown) thus removes a small number of carriers from the P-type material and improves the conductivity of the substrate.

Thereafter, a gate dielectric layer 2128 is deposited in the peripheral region, which may be formed by a process that subsequently removes one of the array regions, or masks the array region. Next, a polycrystalline semiconductor material layer is simultaneously formed in the array and the peripheral region, and the polycrystalline semiconductor material layer is over the surface of the lightly doped region 2114 and the isolation trench dielectric layer 2130. The polycrystalline semiconductor material layer (typically polycrystalline germanium) is relatively heavily doped and has a conductive profile opposite the heavily doped region of the substrate underneath. Next, a capping layer is formed over the polycrystalline semiconductor layer, and the layers are patterned to form relatively lightly doped regions 2114 of the relatively lightly doped crystalline semiconductor material 2114, and appropriate interconnects are formed in the peripheral regions and The gate structure is shown in the figures 22A, 22B, and 22C. In these illustrations, each relatively heavily doped polysilicon strip 2116 is labeled "N+" and is located below the strip of cover material 2118. In this process and similar processes, a single polysilicon process can be shared by both the heavily doped polysilicon device and the peripheral polysilicon structure in the array to save significant manufacturing costs. In this embodiment, the transistor gate structure in the peripheral circuit region of the device and the concentrated doped polysilicon device of the diode include individual features in a single polysilicon layer. Thereafter, an interlevel dielectric layer is formed, and openings are simultaneously formed in the peripheral device region and the memory array region, the openings filling the conductive metal plug material, such as tungsten in the peripheral device region, and in accordance with the implemented memory cell embodiment, Complete the components of the memory cell with the array area. In an alternate embodiment, a metal telluride layer (not shown) may equally preferably be selectively formed on the surface of layer 2412 (see Figure 24B).

In an alternative embodiment, a barrier layer is preferably selectively formed on the PN junction, and the barrier layer may be grown on the exposed lightly doped germanium region 2114 prior to forming the polysilicon germanium cap layer 2116. Depositing a dielectric layer to form a suitable barrier layer, such as cerium oxide (SiO ₂ ) or cerium oxynitride (SiN _x O _y ), may have a thickness ranging from 5 angstroms to 25 angstroms. For example 10 angstroms.

Thereafter, focusing on the array region, the spacers 2310 are formed in a strip of material 2116 that is relatively densely doped with polysilicon, the spacers 2310 masking a narrow range of regions of the relatively lightly doped crystalline semiconductor material 2114 adjacent each relatively densely doped polysilicon. The strip of material 2116, and the width of the masked area can be determined by the spacer 2310, with the remaining area of the exposed relatively lightly doped crystalline semiconductor material labeled 2316.

Thereafter, a concentrated doping process of the bare strip of lightly doped crystalline semiconductor material is performed, and the results are shown in Figs. 24A, 24B, and 24C.

The region 2412, now under the exposed surface 2316 of the ridge of the strip of crystalline semiconductor material 2113, is doped with a strip of concentrated crystalline semiconductor material in the same manner as the strip 2112 (P+) of relatively densely doped crystalline semiconductor material on the N-well.

Thereafter, a mask is formed over the strip of cover material 2118 and the strip of material 2116 and the dielectric material 2130 of the relatively densely doped polysilicon are positioned between the ridges, patterned to cover at least a portion of the strip of cover material 2118 and typically A strip of material 2116 overlying the ridges of the strip of polycrystalline semiconductor material 2113. An etch process is performed to remove any exposed relatively densely doped polycrystalline material, and the mask is subsequently removed, the results of which are shown in Figures 25A, 25B, and 25C. The etching terminates at the surface of the implanted crystalline semiconductor material (2412, P+) such that the relatively densely doped polycrystalline islands 2520 overlying the ridges of the first region 2113 and covered by the conductive cap layer 2518 are constructed. In an alternate embodiment, a metal telluride layer (not shown) may equally preferably be selectively formed on the surface of layer 2412. This completed diode structure (see also Figures 2A, 2B, 4) can now be prepared to form subsequent memory elements thereon, the details of which are detailed below.

26A and 26B are schematic partial views showing a portion of an embodiment of a memory cell in which the second portion of the diode has a columnar pattern. The 26A is in the direction of the bit line 120, and the 26B is in the direction of the word line 130.

Referring to FIGS. 26A and 26B, the memory cell 115 includes a first doped semiconductor region 2613 having a first conductivity type, and a second doped semiconductor plug 2616 on the first doped semiconductor region 2613, the second doping The hetero semiconductor plug 2616 has a second conductivity pattern that is opposite the first conductivity type. The first doped semiconductor region 2613 includes a more heavily doped region 2612 covered by a lightly doped region 2614. A PN junction 2615 is defined between the lightly doped region 2614 of the first doped semiconductor region 2613 and the second doped semiconductor plug 2616. In the embodiment illustrated in the figures, the first doped semiconductor region is a p-type semiconductor; the conductive doped region is labeled "P+", and the lightly doped region is labeled "P-". Moreover, in the embodiments shown in the figures, the second doped semiconductor region is a densely doped n-type semiconductor labeled "N+", and has a doping concentration higher than that of the lightly doped region. .

The first doped semiconductor region 2613 is formed by doping the (single crystal) semiconductor substrate, and thus the first doped semiconductor region is a single crystal semiconductor. The second doped semiconductor region is formed by doping deposited polysilicon plugs in via holes in an insulating layer (not shown). Thus, the dipole system consists of first and second semiconductor regions defining a PN junction therebetween; the first semiconductor region is formed by a single crystal semiconductor and the second semiconductor region is formed of a polycrystalline semiconductor.

The doped single crystal semiconductor region can be formed in the wafer itself. Alternatively, the doped single crystal semiconductor region may be formed on a substrate (such as a germanium-insulating layer-turn) substrate covered with an "SOI" on the insulating layer.

Memory cell 115 includes a conductive cap layer 2618 of a second doped semiconductor plug 2616. The first and second doped semiconductor regions 2613, 2616 and the conductive cap layer 2618 form a multi-layer stack defining diode 121. In the illustrated embodiment, the conductive cap layer 2618 comprises a metal telluride containing, for example, Ti, W, Co, Ni, or Ta. The conductive cap layer 2618 helps maintain a cross across the first and second dopings by providing a higher conductive contact surface than the semiconductor material of the first and second doped semiconductor regions 2613, 2616. The electric field uniformity of the semiconductor regions 2613, 2616. The conductive cap layer 2618 also provides a low resistance ohm between the diode 121 and the cover memory element 160. Incidentally, the conductive cap layer 2618 can be used as a protective etch stop layer for the second doped semiconductor plug 2616 during fabrication of the memory cell array 100. Alternatively, in some preferred embodiments, a metal telluride layer may also be formed on the surface of the densely doped region layer 2612.

In the embodiment illustrated in FIGS. 26A and 26B, the width of the lightly doped region 2614 overlying the densely doped region layer 2612 is greater than the width of the second doped semiconductor plug 2616. A conductive plug 2624 is connected to the dense doped region layer 2612 at an array region spaced apart from or on the side of the second doped semiconductor plug 2616, and extends upwardly in contact with the upper structure, as shown below. And said.

Optionally, preferably a barrier layer is on the PN junction, the layer being formed in the exposed lightly doped germanium region 2614 by growing or depositing a dielectric layer prior to forming a polysilicon cap layer 2616. A suitable barrier layer can be, for example, cerium oxide (SiO ₂ ) or cerium oxynitride (SiN _x O _y ); and it can have a thickness in the range of about 5 to 25 angstroms, for example about 10 angstroms.

The arrow 2619 in Fig. 26B shows a current flow direction from an upper memory element (not shown) across the PN junction 2615 through the diode and through and through the contact via hole 2624. Flow to an upper access line (not shown in this figure). As shown in the figure, since the lightly doped germanium region 2614 is larger than the width of the second doped semiconductor plug 2616, the current must pass through the second doped semiconductor plug before it passes through the densely doped region layer 2612. 2616 passes through the lightly doped germanium region 2614 below the spacer.

27A, 27B; 28A, 28B; 29A, 29B; 30A, 30B; 31A, 31B; 32A, 32B and 33A and 33B show examples of different embodiments of memory cells Wherein the access diode has a second region of the columnar pattern.

27A, 27B illustrate an embodiment of a memory cell array in which memory elements are formed over the access diodes of the second region having the columnar pattern. In this embodiment, a dielectric layer 2710 overlies the conductive cap layer 2618 and an adjacent dielectric fill 2630. In this embodiment, there is no separate bottom electrode; a top electrode strip 2730 covers the dielectric layer 2710, and in this embodiment, the bit line 2734 covers the top electrode strip 2730 in direct electrical contact. The holes in the dielectric layer 2710 are narrower than the dielectric layer 2710 covering the lower side of the conductive cover layer 2618 and the upper side of the dielectric layer 2710 below the top electrode strip 2730. The memory element of each memory cell is formed only in the hole indicated by 2732, and the contact point is down to the narrow end of the conductive cover layer 2618 at the top of the diode stack 121, and up to the wider having the cover top electrode 2730. end.

Referring specifically to Figure 27B, the densely doped region layer 2612 is electrically coupled to the upper word line 130b by a conductive plug (not shown) at a location of certain segments of the region 2612 (not shown).

28A, 28B illustrate another embodiment of a memory cell array in which a memory element is formed over an access diode having a second region of a columnar pattern. In this embodiment, dielectric layer 2810 supports the array of memory elements. The memory element includes a bottom electrode in electrical contact with the second region of the access diode, a memory material in contact with the bottom electrode, and an access line (bit line) 120b above the memory material and above The top electrode of sexual contact. In this configuration, the bottom electrode 2832 is formed and extends through the holes of the dielectric layer 2810. The bottom electrode 2832 contacts the lower cover layer 2618 and contacts the islands of the memory material 2830 formed on the dielectric layer 2810, and each memory material island is covered by a top electrode 2834. The top electrode is coupled to the access line 120b by a conductive plug 2822. In each memory cell, a small area of the phase change material contacts the bottom electrode 2832, and an active area adjacent to the contact with the bottom electrode is a region of the memory element 2830, wherein the memory material can be induced between at least two solid states The transformation.

Referring specifically to Figure 28B, the first heavily doped region 2612 is electrically coupled to the upper word line 130b by a conductive plug (not shown) at a location of certain segments of the region 2612 (not shown). Moreover, the surface of the heavily doped region 2612 can be covered with a metal halide. 29A, 29B illustrate another embodiment of a memory cell array in which a memory element is formed over an access diode having a second region of a columnar pattern. In this embodiment, as in the embodiment shown in FIGS. 28A and 28B, a dielectric filler 2620 surrounds at least an island portion of the diode stack 121, which includes the second doped semiconductor 2616 and the conductive cap layer 2618. And the memory material is formed as an island rather than a strip; and a top electrode, such as island 2934, is formed overlying the memory material and coupled to the access line by a conductive plug 2922 (bit line) ) 120b. However, in this embodiment, there are holes in the dielectric layer 2910, but there are no separate bottom electrodes. Instead, in this embodiment, a portion of the memory material extends from the island 2930 through the holes indicated by 2932 and is brought into contact with the conductive cover layer 2618 at the top of the diode stack 121.

Referring specifically to Figure 29B, the first heavily doped region 2612 is electrically coupled to the upper word line 130b by a conductive plug (not shown) at a location of certain segments of the region 2612 (not shown). Moreover, the surface of the heavily doped region 2612 can be covered with a metal halide.

30A, 30B illustrate another embodiment of a memory cell array in which a memory element is formed over an access diode having a second region of a columnar pattern. In this embodiment, there are holes in the dielectric layer 3010, and as in the embodiment shown in Figures 29A, 29B, there is no separate bottom electrode. However, there are no strips or islands covering the memory material of the dielectric layer, and the top electrode 3034 is island-shaped and directly overlies the dielectric layer 3010. The memory element of each memory cell is formed only in the hole indicated by 3032, and is brought into contact with the conductive cover layer 2618 at the top of the diode stack 121 and with the top electrode 3034 above.

With particular reference to FIG. 30B, the first heavily doped region 2612 is electrically coupled to the upper word line 130b by a conductive plug (not shown) at a location of certain segments of the region 2612 (not shown). Moreover, the surface of the heavily doped region 2612 can be covered with a metal halide.

31A, 31B illustrate another embodiment of a memory cell array in which a memory element is formed over an access diode having a second region of a columnar pattern. In this embodiment, a dielectric layer 3110 supports the array of memory elements. As shown in Figures 28A, 28B, and 28C, the memory device includes a bottom electrode in electrical contact with the second region of the access diode, a memory material in contact with the bottom electrode, and over and above the memory material. The top line of the access line (bit line) 120b is in electrical contact. In this configuration, the bottom electrode 3132 is formed and extends through the holes of the dielectric layer 3110. The bottom electrode 3132 contacts the underlying cap layer 2618 and the cover strip contacting the memory material 3130 formed on the dielectric layer 3110, and each memory strip is covered by a top electrode strip 3134, which also serves as One bit line 120b. In each memory cell, a small area of the phase change material contacts the bottom electrode 3132, and an active area 3133 adjacent to the contact with the bottom electrode is a region of the memory element 3130, wherein the memory material induces at least two solid phases The transformation.

With particular reference to FIG. 31B, the first heavily doped region 2612 is electrically coupled to the upper word line 130b by a conductive plug (not shown) at a location of certain segments of the region 2612 (not shown). Moreover, the surface of the heavily doped region 2612 can be covered with a metal halide. 32A, 32B illustrate another embodiment of a memory cell array in which a memory element is formed over an access diode having a second region of a columnar pattern. In this embodiment, the memory material is formed as a strip 3230 instead of an island; and a top electrode, such as strip 3234, is formed over the memory material as a one-dimensional line. Further, in this embodiment, there are holes in the dielectric layer 3210, but there is no separate bottom electrode. Instead, in this embodiment, a portion of the memory material extends from the strip 3230 through the holes indicated by 3232 and is brought into contact with the conductive cover layer 2618 at the top of the diode stack 121.

Referring specifically to Figure 32B, the first heavily doped region 2612 is electrically coupled to the upper word line 130b by a conductive plug (not shown) at a location of certain segments of the region 2612 (not shown). Moreover, the surface of the heavily doped region 2612 can be covered by a metal halide.

Figures 33A and 33B illustrate another embodiment of a memory cell array formed over an access diode having a columnar second region. In this embodiment, there are holes in the dielectric layer 3310, and in the embodiment shown in Figs. 33A and 33B, there is no separated bottom electrode. However, there is also no strip of memory material here, and also as the top electrode 3334 of the bit line 3330 is disposed directly over the dielectric layer 3310. The memory elements of each memory cell are formed only in the holes, as indicated by symbol 3332, and the cover layer 2618 that connects the contacts to the top of the diode stack 121 and the top electrode 3334 disposed thereon.

Referring specifically to Figure 33B, the first heavily doped region 2612 is electrically coupled to the upper word line 130b by a conductive plug (not shown) at a location of certain segments of the region 2612 (not shown). Moreover, the surface of the heavily doped region 2612 can be covered by a metal halide.

Figures 34A through 39C show stages of an embodiment of a process for accessing a diode having a second region having a columnar pattern.

In the embodiments with reference to Figures 13 through 20C, a semiconductor substrate (typically a semiconductor wafer type, such as a germanium wafer) is provided. Whereas, in this embodiment, the substrate is a P-type semiconductor, an N-well 2110 is formed, and then the wafer is doped to provide a relatively lightly doped version of the same conductivity type (P-type in this embodiment) The relatively densely doped region covered by the miscellaneous region. In the drawing, the relatively densely doped region 2112 is represented by "P+", and the relatively lightly doped region 2114 is represented by "P-". An isolation trench is formed, resulting in a ridge separated by a dielectric layer 2130, as shown in Figures 21A, 21B, and 21C. Each ridge includes a relatively densely doped crystalline semiconductor material (2112, P+) strip on the N-well covered by strips of relatively lightly doped crystalline semiconductor material (2114, P-). These layers together form a first diode region 2113 formed entirely of doped crystalline semiconductor material.

The doped single crystalline semiconductor region can be formed in the wafer itself. Alternatively, the doped single crystalline semiconductor region may be formed on an insulating layer overlying a "SOI" substrate (such as a germanium-insulating layer - germanium) substrate.

Thereafter, a dielectric layer 3410 is formed on the structures shown in Figs. 21A, 21B, and 21C, resulting in the structures shown in Figs. 34A, 34B, and 34C.

Thereafter, the array of openings 3520 is formed through a dielectric layer 3410 of the structure illustrated in Figures 34A, 34B, 34C to expose a region 3522 of the top surface of the relatively lightly doped crystalline semiconductor material (2114, P-), resulting in The structures illustrated in Figures 35A, 35B and 36. The opening 3520 can be formed by a via hole etching technique.

Thereafter, the doped polysilicon plug 3716 is formed in the opening 3520 of the structure illustrated in Figs. 35A, 35B, and 36, resulting in the structures shown in Figs. 37A, 37B, and 37C. The doped polysilicon plug 3716 has an opposite conductivity to the relatively lightly doped crystalline semiconductor material (2114, P-), and thus the plug 3716 contacts a corresponding lightly doped crystalline semiconductor material (2114, P-) to define The PN junction 3715 is in between. The doped polysilicon plug 3716 can be formed by depositing a doped polysilicon material on structures such as those shown in Figures 35A, 35B, and 36, followed by a chemical mechanical polishing (CMP) planarization process.

Here, it is desirable to selectively use a barrier layer at the PN junction. Before the polysilicon plug 3716 is formed in the opening 3520 through the dielectric layer 3510, the barrier layer can be relatively light by growing or depositing a dielectric layer. The exposed region 3522 is over the exposed region 3522. A suitable barrier layer such as hafnium oxide (SiO2) or hafnium oxynitride (SiNxOy); and it can be formed to a thickness ranging from about 5 to 25 angstroms, for example about 10 angstroms.

Optionally, an array of second openings 3820 is formed through a dielectric layer 3510 of the structure illustrated in FIGS. 37A, 37B, 37C to expose a top of the relatively densely doped crystalline semiconductor material (2414, P+). The area 3822 of the surface results in the structure illustrated in Figures 38A, 38B and 38C. Opening 3820 can be formed by a via hole etch technique. Alternatively, a metal halide can be formed on top of the material 2414. Alternatively, as described above, the contact openings 3820 are only occasionally used in the array or at the periphery of the array.

The conductive plug 3924 is formed by depositing a conductive material in the opening 3820 as a via hole of the insulating layer 3510 in the structure illustrated by the 38A, 38B, 38C; and the conductive cover layer 3918 is formed on the doped polysilicon plug 3716. At the top surface, the structure shown in Figs. 39A, 39B, and 39C is caused. The resulting structure consists of a pillar of relatively densely doped polysilicon material (plug 3916) covered by a conductive cap layer 3918 over the lightly doped region of the ridge of the first diode region 2413; and at the surface of the diode structure The heavily doped region 2412 to the ridge of the first diode region 2413 provides a conductive plug 3924 as an electrical contact. This completed diode structure (see also Figures 26A, 26B) can now be prepared to form a subsequent memory element thereon, as described in detail below.

Figures 40A-44C illustrate stages of an embodiment having a forming procedure for a memory element over an access diode having an island-like second region comprised of a patterned polycrystalline body The strip is automatically aligned with the strip of the first doped region (as shown in Figures 7A, 7B).

For example, starting with the configuration shown in FIGS. 20A, 20B, and 20C, a dielectric layer 4010 is deposited over the conductive cap layer 2018 on top of the relatively heavily doped polysilicon island 1716, resulting in the 40A and 40B. structure.

Thereafter, an array of holes is formed in the dielectric layer 4010, and the holes fill the electrode material to form the bottom electrode 4032, as shown in Figs. 41A, 41B, and 41C.

Thereafter, a second array of openings 4220 can be formed through the dielectric layer 4110 of the structure shown in FIGS. 41A, 41B, and 41C to expose a region 4222 where the top surface of the relatively heavily doped crystalline semiconductor material (1512, P+) is implanted. , resulting in the structure illustrated in Figures 42A, 42B and 42C. The opening 4220 can be formed by, for example, an etching technique.

Thereafter, the conductive plug 4324 is formed by depositing a conductive material in the opening 4220 of the structure illustrated in FIGS. 42A, 42B, and 42C, resulting in the structures shown in FIGS. 43A, 43B, and 43C. As noted above, the conductive plug 4324 can be omitted or used only occasionally in some embodiments.

Thereafter, strips 4430 of memory material covered by strips 4443 of top electrode material are formed over the structures shown in Figures 43A, 43B and 43C, resulting in the structures shown in Figures 44A, 44B and 44C. The strips are arranged such that they traverse the bottom electrode 4032 such that the memory material contacts the underlying bottom electrode. As shown in this embodiment, the top electrode 4434 also serves as a bit line.

45A through 50B are diagrams showing stages of an embodiment having a forming process for a memory element over an access diode having an island-like second region that is not associated with the first doped region The strips are automatically aligned.

For example, starting with the configuration shown in Figures 25A, 25B, and 25C, a dielectric layer 4510 is deposited over the conductive cap layer 2518 on top of the relatively heavily doped polysilicon island 1316 (labeled in Figure 25A), resulting in The structure shown in Figures 45A and 45B.

Thereafter, an array of holes is formed in the dielectric layer 4510, and the holes fill the electrode material to form the bottom electrode 4532, as shown in Figs. 46A, 46B, and 46C. As noted above, the conductive plug 4724 can be omitted or used only occasionally in some embodiments.

Thereafter, a second array of openings 4720 can be formed through dielectric layer 4610 of the structure shown in FIGS. 46A, 46B, and 46C to expose regions 4722 where the top surface of the relatively heavily doped crystalline semiconductor material (1512, P+) is implanted. , resulting in the structure illustrated in Figures 47A, 47B and 47C. The opening 4720 can be formed by, for example, an etching technique.

Thereafter, the conductive plugs 4724 are formed by depositing a conductive material in the openings 4720 of the structures illustrated in Figures 47A, 47B, and 47C, resulting in the structures shown in Figs. 48A, 48B, and 48C.

Thereafter, the strips 4930 of the memory material covered by the strips 4934 of the top electrode material are formed over the structures as shown in Figs. 48A, 48B and 48C, resulting in the structures shown in Figs. 49A, 49B and 49C. The strips are arranged such that they traverse the bottom electrode 4532 so that the memory material contacts the underlying bottom electrode. As shown in this embodiment, the top electrode 4934 also serves as a bit line.

Thereafter, a dielectric layer filler 5010 is formed over the structures shown in FIGS. 49A, 49B, and 49C. An additional array of openings is formed through dielectric fill 5010 to expose the surface of conductive plug 4724, and additional conductive plugs 5024 are formed by depositing a conductive material in additional openings. Thereafter, word line 5034 is formed over dielectric layer fill 5010. The word lines 5034 are arranged such that they cross the additional conductive plugs 5024 such that the word lines are in electrical contact with the lower conductive plugs. The resulting structure is shown in panels 50A, 50B. As noted above, the conductive plug 5024 can be omitted or used only occasionally in some embodiments.

51A through 54C are diagrams showing stages of an embodiment having a forming process for a memory element over an access diode having a second region of a columnar pattern (eg, 27A, 27B) Shown). For example, starting from the configuration shown in FIGS. 39A, 39B, and 39C, a dielectric layer 5110 is formed over the conductive cap layer 3918 on top of the relatively heavily doped polysilicon pillars 3916, and an array of tapered vias 5120 It is formed by exposing a region of the lower conductive cap layer 3918 to the dielectric layer 5110. The resulting structure is as shown in Figs. 51A and 51B and 51C.

Thereafter, the hole is filled with the memory material 5232, and the result is as shown in Figs. 52A, 52B, and 52C.

Thereafter, strips 5330 of top electrode material are formed over the columns of memory material elements 5232, and bit lines 120b are formed over the top electrode strips. The strips can be formed by, for example, a deposition-mask-etch process. The resulting structure is shown in Figures 53A, 53B, and 53C.

Thereafter, an additional dielectric layer fill 5410 is formed over the structures shown in FIGS. 53A, 53B, 53C, and the word line 130b is patterned over the structure, as shown in FIG. 54C, as discussed above, The joints here are made occasionally.

Other embodiments are also covered by the scope of the appended claims.

100. . . Memory array

115. . . Memory cell

120, 120a, 120b, 120c. . . Bit line

121. . . Diode (diode access device)

130, 130a, 130b, 130c. . . Word line

160. . . Memory component

212. . . Thicker doped access line

213. . . First doped semiconductor region

214. . . Lighter doped P-region (crystal region, crystal region)

215. . . PN junction (boundary)

215-N, 215-P. . . Deficient area

216. . . Thicker doped N+ region

225. . . Trench

218. . . Conductive coating

224, 526, 2922, 3924, 4324, 4724. . . Conductive plug

310. . . Isolation trench

313, 413. . . First diode region strip (first doped semiconductor region)

314, 414, 1314. . . Lightly doped region

316, 416. . . Second doped semiconductor region

510, 810, 910, 1110. . . Dielectric layer

530. . . Memory material

532, 1132. . . Bottom electrode (first electrode)

533, 1133. . . Active area

534,934. . . Top electrode

730, 734, 830, 1030. . . Strip (memory strip)

1010, 1210. . . Dielectric fill layer

1130. . . Memory material island

1313. . . First area

1314. . . Relatively lightly doped region

1316. . . Polycrystalline semiconductor material layer

1530. . . Dielectric layer

1716. . . N+ region (relatively doped polycrystalline germanium island)

1810, 2310. . . Spacer

2113. . . Crystalline semiconductor material strip

2114. . . Lightly doped crystalline semiconductor material

2116. . . Relatively doped polycrystalline germanium material strip

2128. . . Gate dielectric layer

2310. . . Isolated trench dielectric layer

2412. . . Layer surface

2613. . . First doped semiconductor region

2615. . . PN junction

2616. . . Second doped semiconductor plug

2618. . . Conductive coating

3110, 3410. . . Dielectric layer

3130. . . Memory material

3133. . . Active area

3230, 3234, 4930, 4934, 5330. . . Strip

3334, 4434. . . Top electrode

3520. . . Opening

3522. . . Exposed area

3716. . . Doped polysilicon plug

3822. . . Top surface area

3916. . . Relatively heavily doped polycrystalline niobium

3918. . . Conductive coating

4010, 5010. . . Dielectric layer filler

4032, 4532. . . Bottom electrode

5024. . . Additional conductive plug

5120. . . Conical hole

5232. . . Fill memory material

5410. . . Additional dielectric layer filler

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simplified schematic diagram showing a memory array using a diode access device as described herein.

2A and 2B are cross-sectional views showing a unit diode access device including a patterned polysilicon body.

2C is a view showing the diode access device of the present invention, and the junction is a characteristic pattern of the single crystal portion of the diode.

3 and 4 are cross-sectional views showing another embodiment of a unit diode access device.

5A-5C are cross-sectional views showing an embodiment of a memory cell having a diode access device.

6A and 6B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

7A and 7B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

8A and 8B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

9A and 9B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

10A and 10B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

11A and 11B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

12A and 12B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

13-20C is a diagram showing the steps of manufacturing a process for a diode access device in the embodiment of Figs. 2A, 2B, and 3.

21A-25C are diagrams showing the steps of manufacturing a process for a diode access device in the embodiment of Figs. 2A, 2B, and 4.

26A and 26B are cross-sectional views showing another embodiment of a unit diode access device including a polysilicon plug.

27A and 27B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

28A and 28B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

29A and 29B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

30A and 30B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

31A and 31B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

32A and 32B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

33A and 33B are cross-sectional views showing another embodiment of a memory cell having a diode access device.

34A-39C are diagrams showing another step of manufacturing a process such as the diode access device of the embodiment of Figs. 26A and 26B.

40A-44C is a diagram showing the fabrication of a memory device on a diode access device such as the embodiment of FIGS. 2A, 2B, and 3, and obtaining a memory cell device as shown in FIGS. 7A and 7B. A one-step diagram of the process.

45A-50B is a diagram showing the fabrication of a memory device on a diode access device such as the embodiment of FIGS. 2A, 2B, and 4, and obtaining a memory cell device as shown in FIGS. 7A and 7B. A one-step diagram of the process.

51A-54C are diagrams showing the process of fabricating a memory device on a diode access device such as the embodiment of Figs. 26A and 26B, and obtaining a process of the memory cell device as shown in Figs. 27A and 27B. One step diagram.

In the drawings of many examples, the corresponding drawings are labeled "A" and "B", which generally show two sections perpendicular to each other, that is, the orientation of the section in FIG. 2A is in FIG. 2B. A-A' is marked. And the orientation of the cross section of Fig. 2B is indicated by B-B' in Fig. 2A. When the corresponding drawing is labeled "C", it refers to a plan view.

121. . . Dipole

212. . . Thicker doped access line

213. . . First doped semiconductor region

214. . . Lighter doped P-region

215. . . PN junction (boundary)

216. . . Thicker doped N+ region

218. . . Conductive coating

Claims (64)

A memory cell comprising an access device comprising: a first doped semiconductor region having a first conductivity type; and a second doped semiconductor region having a second conductivity type different from the first conductivity type, Defining a PN junction between a doped semiconductor region and the second doped semiconductor region; wherein the first doped semiconductor region is formed in a single crystal semiconductor, and the second doped semiconductor region comprises a polycrystalline semiconductor; The doping concentration of the second doped semiconductor region is higher than 10 times of the doping concentration of the first doped semiconductor region. The memory cell of claim 1, further comprising a programmable resistive memory element coupled to the second doped semiconductor region. The memory cell of claim 1, wherein the doping concentration of the second doped semiconductor region is 10 to 1000 times the doping concentration of the first doped semiconductor region. The memory cell of claim 1, wherein the first doped semiconductor region comprises a P-type semiconductor and the second doped semiconductor region comprises an N-type polycrystalline semiconductor. The memory cell of claim 1, wherein the first doped semiconductor region comprises an N-type semiconductor and the second doped semiconductor region comprises a P-type polycrystalline semiconductor. For example, the memory cell described in item 1 of the patent application includes an electric A conductive conductive layer is over the second doped semiconductor region. The memory cell of claim 6, wherein the cover layer comprises a metal halide. The memory cell of claim 1, wherein the second doped semiconductor region is automatically aligned with the first doped semiconductor region. The memory cell of claim 1, wherein the second doped semiconductor region and the transistor gate of a peripheral circuit region comprise respective patterned polysilicon bodies in a single polysilicon layer. The memory cell of claim 1, comprising a peripheral region comprising a peripheral circuit, a single crystal semiconductor, a channel for providing a potent transistor, a gate dielectric material and a gate on the channel, and Wherein the second doped semiconductor region is connected to the first doped semiconductor region without an intervening gate dielectric material. The memory cell of claim 1, comprising a peripheral region comprising a peripheral circuit, a single crystal semiconductor, a channel for providing a potent transistor, a gate dielectric material and a gate on the channel, and Wherein the second doped semiconductor region is connected to the first doped semiconductor region without an intervening gate dielectric material, and wherein the second doped semiconductor region and the gate in the peripheral region comprise respective patterns The polycrystalline germanium is hosted in a single polycrystalline germanium layer. The memory cell of claim 1, further comprising a barrier layer between the first doped semiconductor region and the second doped semiconductor region Between domains. The memory cell of claim 12, wherein the barrier layer comprises cerium oxide. The memory cell of claim 12, wherein the barrier layer comprises SiN _x O _y . The memory cell of claim 12, wherein the barrier layer has a thickness between 5 angstroms and 25 angstroms. A memory device includes: a plurality of first access lines, a semiconductor body comprising a doped, single crystal having a first conductivity type extending in a first direction; and a plurality of second access lines extending in a second direction a plurality of memory cells each comprising an access device comprising a first doped semiconductor region having the first conductivity type in the doped, single crystal semiconductor body, wherein the first doped semiconductor region is coupled Connecting to a first access line corresponding to one of the plurality of first access lines, a second doped semiconductor region having a second conductivity type different from the first conductivity type, the second doped semiconductor region Including a polycrystalline semiconductor, defining a PN junction between the first doped semiconductor region and the second doped semiconductor region, and an electrically conductive cap layer on the second doped semiconductor region; and a memory material Electrically connected to the electrically conductive cover layer, the memory material is located below and electrically connected to a corresponding second access line. The doping concentration of the second doped semiconductor region is higher than the doping concentration of the first doped semiconductor region. The memory device of claim 16, wherein the doping concentration of the second doped semiconductor region is higher than 10 times the doping concentration of the first doped semiconductor region. The memory device of claim 16, wherein the first doped semiconductor region and the second doped semiconductor region of the PN junction form a depletion region, the depletion region of the first doped semiconductor region Having a depth greater than 10 times the depth of the depletion region of the second doped semiconductor region, and wherein the first doped semiconductor region is adjacent to the doped, single crystal semiconductor body of the access device The surface includes a protrusion having a height greater than the depth of the depletion region of the first doped semiconductor region. The memory device of claim 16, wherein the first doped semiconductor region comprises a P-type semiconductor and the second doped semiconductor region comprises an N-type polycrystalline semiconductor, and the cap layer comprises a metal Telluride. The memory device of claim 19, wherein the first access line comprises a conductively doped P-type semiconductor in the doped, single crystal semiconductor body. The memory device of claim 19, wherein the first access line comprises a conductive doped P-type semiconductor in the doped, single crystal semiconductor body, and a conductive cap layer is included in the conductive doping P- The surface of the semiconductor is above the surface. The memory device of claim 16, wherein the first doped semiconductor region comprises an N-type semiconductor in the doped, single crystal semiconductor body, and the second doped semiconductor region comprises a P-type Crystal semiconductor. The memory device of claim 22, wherein the first access line comprises a conductive doped N-type semiconductor in the doped, single crystal semiconductor body. The memory device of claim 22, wherein the first access line comprises a conductive doped N-type semiconductor in the doped, single crystal semiconductor body, and a conductive cap layer is included in the conductive doping The surface portion of the N-type semiconductor. The memory device of claim 16, further comprising a bottom electrode between the cover layer and the memory material. The memory device of claim 16, wherein the second doped semiconductor region is automatically aligned with the first doped semiconductor region. The memory device of claim 16, wherein the second doped semiconductor region and the transistor gate in a peripheral circuit region comprise respective patterned polysilicon bodies in a single polysilicon layer. The memory device described in claim 16 of the patent application further includes A barrier layer is interposed between the first doped semiconductor region and the second doped semiconductor region. The memory device of claim 28, wherein the barrier layer comprises cerium oxide. The memory device of claim 28, wherein the barrier layer comprises SiN _x O _y . The memory device of claim 28, wherein the barrier layer has a thickness ranging from 5 angstroms to 25 angstroms. A memory cell includes: a storage element, and a PN junction coupled to the storage element as an access device, comprising a polysilicon node of a first conductivity type and a single crystal of a second conductivity type An interface between the germanium nodes; the single crystal germanium node is located above a second germanium node of the second conductivity type within a polysilicon body of the first conductivity type, wherein the doping concentration of the poly germanium node is high The doping concentration of the single crystal germanium node and the depletion region adjacent to the interface have respective depths, and the single crystal germanium node includes a component protruding from a surface of the polycrystalline germanium body, the protruding height of the component being greater than the single The depth of the depletion region of the wafer node. A memory cell comprising: a storage element, and a diode coupled as an access device to the storage element, comprising a polysilicon node of a first conductivity type, a second conductivity type a first single crystal germanium node; a dielectric layer over the poly germanium node of the diode; an electrode extending through the dielectric layer to connect the plurality of germanium nodes of the diode to the storage element, And a metal plug passes through the same dielectric layer, the electrode having a top surface connected to the storage element, and the top surface of the electrode is smaller than a top surface of the metal plug. A method for fabricating a memory cell driver, comprising: providing a single crystal germanium semiconductor substrate having a first conductivity type; forming a lightly doped region of the first conductivity type within the substrate and adjacent to An upper surface of the substrate; a dense doped polysilicon material of a second conductivity type deposited on a surface of the lightly doped region, the dense doped polysilicon material having a higher doping concentration than the lightly doped region a doping concentration; forming trench isolation to define a driving strip disposed in one direction; depositing a first dielectric material to fill the trench to isolate and cover the driving strip; planarizing to expose one surface of the driving strip Patterning the more heavily doped polycrystalline material in another direction to isolate a second driving element and exposing a lightly doped region adjacent the first conductivity type; forming a spacer adjacent to the second driving element a step of performing the implanting of the first conductivity type on the exposed lightly doped region of the first conductivity type to make it more heavily doped; forming an electrically conductive covering material in the second driving element And drives at least over a portion of the article; and depositing a second dielectric material on the first and the second dielectric material One of the drive elements is on the surface. A memory cell comprising an access device having a multi-layer stack, the method comprising: a first doped semiconductor region comprising a first conductivity type in a single crystal substrate; and an insulating layer comprising a via hole on the substrate And a second doped semiconductor plug in the via hole and contacting the first doped semiconductor region, the second doped semiconductor plug having a second conductivity type different from the first conductivity type, such that the second a doped semiconductor region and the second doped semiconductor plug define a PN junction; wherein the second doped semiconductor plug comprises a polycrystalline semiconductor, and the doping concentration of the second doped semiconductor plug is higher than the first The doping concentration of a doped semiconductor region is more than 10 times. The memory cell of claim 35, further comprising a programmable resistive memory element over the insulating layer and coupled to the second doped semiconductor plug. The memory cell of claim 35, wherein the doping concentration of the second doped semiconductor plug is 10 to 1000 times the doping concentration of the first doped semiconductor region. The memory cell of claim 35, wherein the first doped semiconductor region comprises a P-type semiconductor and the second doped semiconductor plug comprises an N-type polycrystalline semiconductor. Such as the memory cell described in claim 35, wherein the A doped semiconductor region comprises an N-type semiconductor and the second doped semiconductor plug comprises a P-type polycrystalline semiconductor. The memory cell of claim 35, further comprising an electrically conductive cover layer over the second doped semiconductor plug. The memory cell of claim 40, wherein the cover layer comprises a metal halide. The memory cell of claim 35, further comprising a barrier layer between the first doped semiconductor region and the second doped semiconductor plug. The memory cell of claim 42, wherein the barrier layer comprises cerium oxide. The memory cell of claim 42, wherein the barrier layer comprises SiN _x O _y . The memory cell of claim 42, wherein the barrier layer has a thickness ranging from 5 angstroms to 25 angstroms. A memory device includes: a plurality of doped semiconductor first access lines extending in a first direction; a plurality of second access lines extending in a second direction; a plurality of memory cells, each memory cell comprising a memory The device includes a first doped semiconductor region having the first conductivity type, The first doped semiconductor region is formed in a single crystal semiconductor substrate, and wherein the first doped semiconductor region is formed on a doped semiconductor first access line, and an insulating layer includes a via hole on the substrate a second doped semiconductor plug having a second conductivity type different from the first conductivity type, the second doped semiconductor plug comprising a polycrystalline semiconductor, the first doped semiconductor region and the second doping A PN junction is defined between the semiconductor plugs, and an electrically conductive cover layer is disposed on the second doped semiconductor plug; and a memory material is electrically connected to the conductive cover layer, the memory material is located in a corresponding second And electrically connected to the access line, wherein the doping concentration of the second doped semiconductor plug is higher than the doping concentration of the first doped semiconductor region. The memory device of claim 46, wherein adjacent semiconductor first access lines are separated by a trench isolation. The memory device of claim 46, wherein the first doped semiconductor region comprises a lightly doped P-type semiconductor and the second doped semiconductor plug comprises a more heavily doped N-type polycrystalline semiconductor, The doping concentration is higher than the doping concentration of the lightly doped P-type semiconductor, and the cap layer comprises a metal halide. The memory device of claim 48, wherein the first access line comprises a conductively doped P-type semiconductor. The memory device of claim 48, wherein the The first access line includes a conductively doped P-type semiconductor and includes a conductive cap layer on a surface portion of the conductive doped P-type semiconductor. The memory device of claim 46, wherein the first doped semiconductor region comprises a lightly doped N-type semiconductor, and the second doped semiconductor plug comprises a more heavily doped P-type polycrystalline semiconductor The doping concentration is higher than the doping concentration of the lightly doped N-type semiconductor. The memory device of claim 51, wherein the first access line comprises a conductive doped N-type semiconductor. The memory device of claim 51, wherein the first access line comprises a conductive doped N-type semiconductor and a conductive cap layer is disposed on a surface portion of the conductive doped N-type semiconductor. The memory device of claim 50, further comprising a bottom electrode between the cover layer and the memory material. The memory device of claim 50, further comprising a barrier layer interposed between the first doped semiconductor region and the second doped semiconductor plug. The memory device of claim 55, wherein the barrier layer comprises cerium oxide. The memory device of claim 55, wherein the barrier layer comprises SiN _x O _y . The memory device of claim 55, wherein the barrier layer has a thickness ranging from 5 angstroms to 25 angstroms. A memory cell comprising an access device comprising: a first doped semiconductor region having a first conductivity type; and a second doped semiconductor plug having a second conductivity type different from the first conductivity type Defining a PN junction between the first doped semiconductor and the second doped semiconductor plug; wherein the first doped semiconductor region is formed in a single crystal semiconductor, and the second doped semiconductor plug comprises a polycrystalline semiconductor The doping concentration of the second doped semiconductor plug is higher than the doping concentration of the first doped semiconductor region, and the memory cell further includes a programmable resistive memory device coupled to the second doped semiconductor embolism. A memory cell includes: a storage element, and a diode coupled to the storage element as an access device, comprising a polysilicon node of a first conductivity type and a single crystal germanium node of a second conductivity type The polysilicon node includes a polysilicon plug embedded in a contact opening and passing through a specific dielectric layer, and includes a metal plug in the other contact opening and passing through the same specific dielectric layer, wherein the polysilicon node The doping concentration is higher than the doping concentration of the single crystal germanium node. A method for fabricating a memory cell driver includes: providing a single crystal germanium semiconductor substrate having a first conductivity type; Forming a conductive doped region of a second conductivity type over a region of the semiconductor substrate; forming a lightly doped region of the second conductivity type within a vicinity of an upper surface of the conductive doped region, the light doping The region has a doping concentration lower than a doping concentration of the conductive doped region; trench isolation is formed to define a bottom driver region strip; a first dielectric material is deposited to fill the trench isolation and cover the bottom driver region strip Flattening to expose a surface of the first dielectric material and the bottom electrode driving region strip; depositing a second dielectric material over the surface of the first dielectric material and the bottom driver region strip Forming a contact opening penetrating the two dielectric material to expose a region of the lightly doped region on the surface of the bottom driver region strip; forming one of the first conductivity types of the more heavily doped polycrystalline material at the contact opening The densely doped polycrystalline material establishes a PN junction in the exposed region of the lightly doped region, and the doping concentration of the densely doped polycrystalline material is higher than the doping concentration of the lightly doped region ;as well as Into an electrically conductive coating layer on one surface of the doped poly thicker polycrystalline material. The method of claim 61, wherein the densely doped polycrystalline material forming the first conductivity type comprises depositing the polycrystalline material by chemical vapor deposition to fill the contact opening in the contact opening Then, planarization is performed by a chemical mechanical deposition method. The method of claim 61, wherein the electrically conductive cover layer is formed on the polycrystalline material in the contact opening. Long one metal halide. The method of claim 61, further comprising forming a barrier layer between the more heavily doped polycrystalline material and the exposed region of the lightly doped region.