TWI407766B - Multi-channel multi-media integrated circuit and method thereof - Google Patents

Abstract

The present invention discloses a multi-channel multi-media data processing method, comprising the steps of: providing a demodulator circuit and a multi-media processing circuit, the multi-media processing circuit including a DRAM; receiving multi-channel analog signals, and performing analog-to-digital conversion and demodulation on the signals by the demodulator circuit; storing the converted and demodulated multi-channel signals in the DRAM; and reading the signals of at least one channel from the DRAM.

Description

Multi-channel multimedia integrated integrated circuit and method

The invention relates to a multi-channel multimedia integrated integrated circuit, in particular to a multi-channel multimedia integrated integrated circuit capable of accelerating memory reading speed when processing multi-channel data, and related multi-channel multimedia data processing method.

A circuit for receiving and processing multi-channel multimedia broadcast data is generally constructed as shown in FIG. 1, and includes a separate demodulator chip 110 and a separate multimedia processor chip 120. The demodulator chip 110 demodulates the received multimedia broadcast data and transmits it to the multimedia processor chip 120 for further processing to generate display signals and/or audio signals, which are displayed through the display 130 and the speaker 140. Play. Such a structure can be found, for example, in high-end mobile phones, high-end PDAs (personal digital assistants), car-action mobile TVs, etc., and the multimedia broadcast data processed by them can be wireless network communication materials, television signals, and the like.

In this prior art architecture, the external RF signal is first received by the RF receiving circuit (RF) 101, in which the RF signal is down-converted, and the down-converted analog signal is transmitted to the analog-to-digital converter 111. The analog-to-digital conversion is performed, and then demodulated by an Orthogonal Frequency Division Multiplexer Demodulator (OFDM demodulator) 112. The digital signal obtained by the above processing is under the control of the controller 113, according to The data is interleaved with the address generated by the address processor 114 and stored in the SRAM (Static Random Access Memory) 118. Since the error correction function is required, the data storage time is different from the reading direction, and the main function of the data interleaving address processor 114 is to determine the address where the data is stored and read. (For details on the technical aspects of storing and reading data in an interleaved manner, please refer to the applicant's application No. 95133847, which is not described here.) The data stored in the SRAM 118 is stored back to the SRAM after error correction. Inside. Then, under the control of the controller 113, the data that has undergone the restoration correction is transmitted to the multimedia processor chip 120 for further processing. Between the chips 110 and 120, a serial peripheral interface (SPI) is usually used to transmit data in a sequential manner.

In the multimedia processor chip 120, generally, a dynamic random access memory (DRAM 128) and a static random access memory (SRAM 129) are provided, and the memory control interface 127 is used to communicate with other circuits. . The video decoder 122 reads the data through the control interface 127, performs appropriate decoding, and outputs it through the display controller 126 to play the image on the display 130. Display 130 is generally a liquid crystal screen, but may be other displays as well. In addition, the audio decoder 123 also reads the data through the control interface 127, performs appropriate decoding, and outputs the data to the speaker 140 for playback. In addition, for better picture effects, the JPEG codec circuit 124 is usually provided in the chip 120 to compress and decompress the film or image file; and the image processing circuit 125 for processing image contrast and color. , brightness, and so on.

When the multimedia broadcast material has multiple transmission channels, such as television signals, the user may wish to continuously switch among multiple channels to select the desired program. In order to allow the user to immediately and smoothly display the screen without changing the delay, it is necessary to pre-set a number of channels that the user does not currently watch, such as the channel currently being watched, or even more channels. The download is stored in the SRAM 118, and error correction and the like are processed in advance; thus, when the user switches channels, the data is ready to be played immediately.

However, in the above-mentioned prior art architecture, all channel data needs to be transmitted to the multimedia processor chip 120 after a complete error correction operation in the demodulator chip 110, and the data is transmitted in sequence by the two chips. The width is very narrow, slowing down the overall processing speed. In addition, only one of the channels stored in SRAM 118 will be actually utilized. With regard to cost considerations, it is not possible to expand the capacity of the SRAM 118 without limitation. In other words, limited by the capacity of the SRAM 118, the number of channels allowed to be stored is limited, and when the user randomly switches channels, delays are inevitable.

In view of this, the present invention is directed to the deficiencies of the prior art described above, and proposes a multi-channel multimedia integrated integrated circuit to improve the aforementioned deficiency.

A first object of the present invention is to provide a multi-channel multimedia integrated integrated circuit capable of accelerating a memory reading speed when processing multi-channel data, and avoiding a delay when a user randomly switches channels.

A second object of the present invention is to provide a multi-channel multimedia integrated integrated circuit capable of assisting in displaying a multi-channel picture on a display.

A third object of the invention is to provide a related method.

In order to achieve the above object, according to one embodiment of the present invention, a multi-channel multimedia integrated integrated circuit is provided, coupled to a radio frequency receiving circuit, and the radio frequency receiving circuit receives a plurality of channels of radio frequency multimedia data signals. The multi-channel multimedia integrated integrated circuit includes: an analog digital converter coupled to the radio frequency receiving circuit for analog-digital conversion of the radio frequency multimedia data signals of the plurality of channels; a demodulator, and the analog-to-digital conversion The device is coupled to receive the analog-to-digital converted signal and demodulate the signal; the controller is configured to control the storage and processing of the demodulated signal; and the dynamic random access memory is configured to store the plurality of channels The demodulated signal, wherein the multi-channel multimedia integrated integrated circuit has both demodulation and multimedia data processing functions.

Moreover, the present invention also provides a multi-channel multimedia data method, comprising the steps of: providing a demodulation circuit and a multimedia processing circuit, wherein the multimedia processing circuit has a dynamic random access memory; The variable circuit receives the analog signal of the plurality of channels, and performs analog-to-digital conversion and demodulation; separately stores the converted and demodulated signals of the plurality of channels in the dynamic random access memory; and The dynamic random access memory reads signals of at least one channel.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

Referring to Figure 2, one of the embodiments of the present invention is shown in a schematic circuit diagram. In the present embodiment, the circuits 11, 12, 13, 14 constitute the demodulation circuit 10, and the other circuits constitute the multimedia processing circuit 20. According to one of the preferred embodiments of the present invention, all circuits except the radio frequency receiving circuit 101 are integrated in the same integrated circuit chip 100. Thus, the dedicated SRAM (the component 118 in the prior art) required in the original demodulator chip can be omitted, and the circuits 11, 12, 13, 14 in the original demodulator chip can be controlled by the same memory. The interface 27 accesses the memory (DRAM 28 and SRAM 29). Moreover, in the architecture of the embodiment, the received multi-channel data can be directly stored in the DRAM 28, and the data can be transmitted in a parallel rather than a sequential manner to speed up the processing; in addition, due to the same area and cost, the DRAM The capacity is much larger than that of the SRAM, so the capacity of the DRAM 28 can be fully utilized to store more channels than the conventional technology. Under the framework of this case, the number of channels that can be stored is about 3-10 times that of the prior art.

The multi-channel signal processing method of the embodiment of Fig. 2 is as follows. First, the radio frequency receiving circuit (RF) 101 continuously receives external radio frequency signals of a plurality of channels, and performs frequency reduction. The down-converted analog signals are transmitted to the analog-to-digital converter 11 for analog-to-digital conversion, and then subjected to orthogonal frequency division multiplexing. The modulator 12 is demodulated. The digital signals obtained after the above processing are stored in the respective channel areas in the DRAM 28 under the control of the controller 13, and subjected to error correction processing. Each channel area does not have to have a one-to-one correspondence with external channels; the external channel signals can be dynamically stored in any channel area.

Since the memory capacity is relatively increased, when the user randomly switches channels, the screen can be displayed smoothly and immediately. And the overall circuit processing speed has also increased. Moreover, due to the increased number of channel signals that can be stored, the present invention can provide multiple channel parallel processing functions that are not available in the prior art, for example, multiple channels can be provided on the display, with equal-sized segments or Different sizes of mother and child pictures are displayed to obtain the content of the program by simultaneously displaying the programs of multiple channels; for example, the program of one channel can be displayed on the display while recording the program of another channel or more channels at the same time. The recording method is, for example, directly stored in the DRAM in the form of the original signal, or compressed into another file format for storage, or output to other external storage media (for example, an external hard disk, a compact disk, a memory storage disk commonly known as a thumb).

In the circuit of the embodiment of Fig. 2, for example, a video game processing circuit 31 may be provided for the user to play the game; a 3D image processing circuit 33 for performing 3D image processing, and the like.

As can be seen from the prior art, the present invention can save hardware costs, improve data processing efficiency, and can store more channels than the prior art, making the user more convenient.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. For those skilled in the art, various equivalent changes can be immediately considered within the spirit of the invention. For example, between the circuit blocks shown, other circuits that do not affect the main circuit function can be inserted; depending on the received signal, the demodulator 112 is not limited to the OFDM demodulator; the display is not necessarily limited to the LCD screen; the radio frequency receiving The circuit 101 is not necessarily an independent external component, but may be integrated within the circuit 10 or the integrated circuit 100, and the like. Equivalent changes or modifications of the concept and spirit of the invention are intended to be included within the scope of the invention.

10. . . Demodulation circuit

31. . . Video game processing circuit

11. . . Analog digital converter

33. . . 3D image processing circuit

12. . . Orthogonal frequency division multiplexing demodulator

100. . . Integrated circuit chip

13. . . Controller

110. . . Demodulator chip

14. . . Data interleaving address processor

101. . . Radio frequency receiving circuit

20. . . Multimedia processing circuit

111. . . Analog digital converter

twenty two. . . Video decoder

112. . . Orthogonal frequency division multiplexing demodulator

twenty three. . . Audio decoder

113. . . Controller

twenty four. . . JPEG codec circuit

114. . . Data interleaving address processor

25. . . Image processing circuit

118. . . SRAM

26. . . Display controller

120. . . Multimedia processor chip

27. . . Memory control interface

122. . . Video decoder

28. . . DRAM

123. . . Audio decoder

29. . . SRAM

124. . . JPEG codec circuit

125. . . Image processing circuit

129. . . SRAM

126. . . Display controller

130. . . monitor

127. . . Memory control interface

140. . . speaker

128. . . DRAM

Schematic description:

Figure 1 is a schematic circuit diagram showing a conventional circuit for receiving and processing multimedia broadcast data.

Fig. 2 is a schematic circuit diagram showing a hardware circuit structure according to an embodiment of the present invention.

10. . . Demodulation circuit

11. . . Analog digital converter

12. . . Orthogonal frequency division multiplexing demodulator

13. . . Controller

14. . . Data interleaving address processor

20. . . Multimedia processing circuit

twenty two. . . Video decoder

twenty three. . . Audio decoder

twenty four. . . JPEG codec circuit

25. . . Image processing circuit

26. . . Display controller

27. . . Memory control interface

28. . . DRAM

29. . . SRAM

31. . . Video game processing circuit

33. . . 3D image processing circuit

100. . . Integrated circuit chip

101. . . Radio frequency receiving circuit

130. . . monitor

140. . . speaker

Claims (12)

A multi-channel multimedia integrated integrated circuit coupled to a radio frequency receiving circuit, the radio frequency receiving circuit receiving a plurality of channels of radio frequency multimedia data signals, the multi-channel multimedia integrated integrated circuit comprising: an analog digital converter, and the radio frequency The receiving circuit is coupled to perform analog-digital conversion on the radio frequency multimedia data signals of the plurality of channels; the demodulation transformer is coupled to the analog digital converter, and receives the analog-to-digital converted signal and demodulates the signal; a controller for controlling storage and processing of the demodulated signal; a dynamic random access memory for storing the demodulated signal of the plurality of channels; a memory control interface, and the dynamic random The access memory is coupled, and the memory control interface is coupled to the controller; and the multimedia data processing unit performs multimedia data processing using the data stored by the dynamic random access memory, wherein the multi-channel is processed. The multimedia integrated integrated circuit has both demodulation and multimedia data processing functions, and the demodulation is shared with the multimedia data processing function. A dynamic random access memory. For example, the multi-channel multimedia integrated integrated circuit described in claim 1 further includes: a data interleaving address processor for determining an address for storing and reading data. The multi-channel multimedia integrated integrated circuit of claim 1, further comprising: a static random access memory coupled to the memory control interface and the dynamic random access memory. Multi-channel multimedia integrated integration as described in item 1 of the patent application scope The circuit, wherein the multimedia data processing unit comprises one or more of the following circuits, coupled to the memory control interface: a video decoder, an audio decoder, a JPEG codec circuit, an image processing circuit, a display controller, and a video game. Processing circuit, 3D image processing circuit, or a combination of both. The multi-channel multimedia integrated integrated circuit according to claim 1, wherein the radio frequency receiving circuit is integrated in the multi-channel multimedia integrated integrated circuit. A method for processing multi-channel multimedia data, comprising the steps of: providing a demodulation circuit and a multimedia processing circuit, wherein the multimedia processing circuit has a dynamic random access memory; and receiving the multi-demodulation circuit Analog signals of the channels, and analog-to-digital conversion and demodulation; the signals of the converted and demodulated multiple channels are individually stored in the dynamic random access memory; and from the dynamic random storage Read the signal of at least one channel in the memory. The method of claim 6, further comprising the step of: performing error correction on the signals of the converted plurality of channels. The method of claim 6, wherein the converted signals of the plurality of channels are stored in the dynamic random access memory in a parallel transmission manner. The method of claim 6, wherein the signal of at least two channels is read from the dynamic random access memory, and the method further comprises The next step: displaying the signals of at least two channels simultaneously on a display. The method of claim 9, wherein the divided pictures or the mother and child pictures of different sizes are simultaneously displayed. The method of claim 6, wherein the at least two channels of the signal are read from the DRAM, and the method further comprises the step of: displaying the signal of one of the channels on a display. And record the signal of another channel. The method of claim 6, wherein the signal of the other channel is recorded in an external storage medium.