TWI406410B - Semiconducting nanostructure - Google Patents

Semiconducting nanostructure Download PDF

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TWI406410B
TWI406410B TW99101724A TW99101724A TWI406410B TW I406410 B TWI406410 B TW I406410B TW 99101724 A TW99101724 A TW 99101724A TW 99101724 A TW99101724 A TW 99101724A TW I406410 B TWI406410 B TW I406410B
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crystal plane
substrate
semiconductor nanostructure
ridge
orientation
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TW99101724A
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TW201126711A (en
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Jian Wu
Zheng Liu
Wen-Hui Duan
Bing-Lin Gu
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Hon Hai Prec Ind Co Ltd
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Abstract

The present invention relates to a semiconducting nanostructure. The semiconducting nanostructure includes a substrate and at least one ridge. The substrate includes a first crystal plane and a second crystal plane perpendicular to the first crystal plane. The at least one ridge extends from the first crystal plane along a crystal orientation of the second crystal plane.

Description

半導體奈米結構 Semiconductor nanostructure

本發明涉及一種半導體奈米結構,尤其涉及一種二維半導體奈米結構。 The present invention relates to a semiconductor nanostructure, and more particularly to a two-dimensional semiconductor nanostructure.

隨著半導體電子器件之工藝尺度進入奈米量級,其內部之核心單元電晶體之尺度也要求向奈米量級發展。如先前半導體電子器件中常用之金屬氧化物半導體場效應電晶體(MOSFET),當該金屬氧化物半導體場效應電晶體之尺度縮小為奈米量級時,其P型或N型半導體結構之物理性能也發生了改變,其主要體現為該半導體結構中之載流子(電子或空穴)遷移率明顯下降。先前技術中應用於MOSFET中之半導體結構多為一膜狀結構之矽,為增加載流子之遷移速率,其通常採用之手段為,施加一應力改變半導體結構之晶格尺寸,從而使該半導體結構之能帶發生改變,該能帶之改變可提高該半導體結構中載流子之遷移率。然而,上述方式未能考慮制約半導體結構中載流子遷移率提高之另一個重要因素“雜質散射”。所謂雜質散射係指載流子在經過一雜質原子時,該載流子和雜質原子之間會存在庫侖力之相互作用,使得該雜質原子與該載流子相互吸引或相互排斥,從而使該載流子之遷移方 向發生偏移。 As the process scale of semiconductor electronic devices enters the nanometer scale, the scale of the inner core cell transistor is also required to develop to the nanometer scale. Metal oxide semiconductor field effect transistors (MOSFETs), which are commonly used in semiconductor electronic devices, when the scale of the metal oxide semiconductor field effect transistor is reduced to the order of nanometers, the physical properties of the P-type or N-type semiconductor structure The performance has also changed, mainly due to the significant decrease in the mobility of carriers (electrons or holes) in the semiconductor structure. In the prior art, the semiconductor structure applied to the MOSFET is mostly a film-like structure. In order to increase the carrier migration rate, a method is generally employed to apply a stress to change the lattice size of the semiconductor structure, thereby making the semiconductor The energy band of the structure changes, and the change in the band increases the mobility of carriers in the semiconductor structure. However, the above method fails to consider another important factor "impurity scattering" that restricts the increase in carrier mobility in a semiconductor structure. The impurity scattering means that when a carrier passes through an impurity atom, a Coulomb force interaction exists between the carrier and the impurity atom, so that the impurity atom and the carrier mutually attract or repel each other, thereby making the Carrier migration The offset occurs.

請參見“Quantum confinement of crystalline silicon nanotubes with nonuniform wall thickness: Implication to modulation doping”, Appl. Phys. Lett, B. Yan et al, Vol91, P103107(2007)”,該文獻發現,被摻雜之准一維之矽奈米管具有雜質散射較小之現象。具體為,該矽奈米管具有不均勻之壁厚,該壁厚之不均勻性可使得載流子定位於較厚之壁內。在實際應用過程中,為提高載流子濃度,該文獻揭示可在較薄之壁內進行P型或N型摻雜,摻雜元素會留在較薄之壁內,而載流子則大部分分佈於較厚之壁內,該摻雜元素與載流子相分離之現象可使得影響載流子遷移率之雜質散射減少。 See "Quantum confinement of crystalline silicon nanotubes with nonuniform wall thickness: Implication to modulation doping", Appl. Phys. Lett, B. Yan et al, Vol 91, P103107 (2007)", which finds that the doped one The U.S. tube has a phenomenon in which the impurity scattering is small. Specifically, the U-tube has a non-uniform wall thickness, and the unevenness of the wall thickness allows the carrier to be positioned in a thicker wall. In practical applications, in order to increase the carrier concentration, the literature discloses that P-type or N-type doping can be performed in a thinner wall, the doping element will remain in the thinner wall, and the carrier will be mostly Distributed in a thicker wall, the phenomenon that the doping element is separated from the carrier phase can reduce the scattering of impurities that affect carrier mobility.

然,該文獻揭示之半導體奈米結構僅係一種一維半導體奈米結構,其結構對減小雜質散射之規律並不能適用於二維半導體奈米結構,即其並未揭示一種可減小雜質散射對載流子遷移率影響之二維半導體奈米結構。 However, the semiconductor nanostructure disclosed in this document is only a one-dimensional semiconductor nanostructure, and its structure for reducing the scattering of impurities cannot be applied to a two-dimensional semiconductor nanostructure, that is, it does not reveal a kind of impurity reduction. A two-dimensional semiconductor nanostructure that affects the mobility of carriers.

有鑒於此,提供一種可降低雜質散射對載流子遷移率影響之二維半導體奈米結構實為必要。 In view of this, it is necessary to provide a two-dimensional semiconductor nanostructure which can reduce the influence of impurity scattering on carrier mobility.

一種半導體奈米結構,其包括:一基底及至少一個脊部,該基底包括一第一晶面及垂直於該第一晶面之第二晶面,所述至少一個脊部從所述基底中之第一晶面開始沿所述第二晶面之晶面取向延伸出。 A semiconductor nanostructure comprising: a substrate and at least one ridge, the substrate comprising a first crystal plane and a second crystal plane perpendicular to the first crystal plane, the at least one ridge from the substrate The first crystal plane begins to extend along the crystal plane orientation of the second crystal plane.

一種半導體奈米結構,其包括:一基底及至少一脊部,該基底包括一第一晶面及垂直於該第一晶面之第二晶面,所述至少一個脊部從所述基底中之第一晶面開始沿所述第二晶面之晶面取向延伸出,該基底之材料為矽,該脊部之材料由矽及均勻分散於該矽中之複數P型摻雜原子組成,該第一晶面之晶面取向為(110),該第二晶面之晶面取向為垂直於該第一晶面取向之(001),該脊部之一半高度處截面之寬度小於10奈米。 A semiconductor nanostructure comprising: a substrate and at least one ridge, the substrate comprising a first crystal plane and a second crystal plane perpendicular to the first crystal plane, the at least one ridge from the substrate The first crystal plane begins to extend along the crystal plane orientation of the second crystal plane, and the material of the substrate is germanium, and the material of the spine is composed of germanium and a plurality of P-type dopant atoms uniformly dispersed in the crucible. The crystal plane orientation of the first crystal plane is (110), and the crystal plane orientation of the second crystal plane is (001) perpendicular to the orientation of the first crystal plane, and the width of the cross section at one half height of the ridge is less than 10 nm. Meter.

一種半導體奈米結構,其包括:一基底及至少一脊部,該基底包括一第一晶面及垂直於該第一晶面之第二晶面,所述至少一個脊部從所述基底中之第一晶面開始沿所述第二晶面之晶面取向延伸出,該基底之材料為矽,該脊部之材料由矽及均勻分散於該矽中之複數N型摻雜原子組成,該該第一晶面之晶面取向為(001),該第二晶面之晶面取向為垂直於該第一晶面取向之(110),該脊部之一半高度處截面之寬度小於10奈米。 A semiconductor nanostructure comprising: a substrate and at least one ridge, the substrate comprising a first crystal plane and a second crystal plane perpendicular to the first crystal plane, the at least one ridge from the substrate The first crystal plane begins to extend along the crystal plane orientation of the second crystal plane, and the material of the substrate is germanium, and the material of the spine is composed of germanium and a plurality of N-type dopant atoms uniformly dispersed in the crucible. The crystal plane orientation of the first crystal plane is (001), and the crystal plane orientation of the second crystal plane is perpendicular to the (110) orientation of the first crystal plane, and the width of the cross section at one half height of the ridge is less than 10 Nano.

相較於先前技術,由於本發明提供之半導體奈米結構可使空穴或電子被強烈地束縛在基底中,且根據調製摻雜效應,脊部之摻雜原子和空穴在空間上相互分離,即摻雜原子大部分分佈在脊部,而空穴或電子則大部分分佈在基底中,從而使雜質散射對空穴或電子之遷移速度影響較小,從而大大提高了空穴或電子之遷移速度。 Compared with the prior art, since the semiconductor nanostructure provided by the present invention allows holes or electrons to be strongly bound in the substrate, and according to the modulation doping effect, the doping atoms and holes of the ridge are spatially separated from each other. That is, most of the doping atoms are distributed in the ridge, and holes or electrons are mostly distributed in the substrate, so that the scattering of impurities has less influence on the migration speed of holes or electrons, thereby greatly increasing the holes or electrons. Migration speed.

10,20‧‧‧半導體奈米結構 10,20‧‧‧Semiconductor nanostructure

12,22‧‧‧基底 12,22‧‧‧Base

13,23‧‧‧第一晶面 13,23‧‧‧First crystal face

14,24‧‧‧脊部 14,24‧‧‧ ridge

15,25‧‧‧第二晶面 15,25‧‧‧second crystal face

16,26‧‧‧溝道 16,26‧‧‧Channel

18,28‧‧‧保護層 18,28‧‧‧protection layer

圖1係本發明第一實施例半導體奈米結構之結構示意圖。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a semiconductor nanostructure according to a first embodiment of the present invention.

圖2係本發明第一實施例半導體奈米結構中空穴在脊部之佔有率、脊部與基底之間之能量差與脊部頂表面寬度之間之關係。 Fig. 2 is a view showing the relationship between the occupation ratio of holes in the ridges, the energy difference between the ridges and the substrate, and the width of the top surface of the ridges in the semiconductor nanostructure of the first embodiment of the present invention.

圖3係本發明第二實施例半導體奈米結構之結構示意圖。 3 is a schematic view showing the structure of a semiconductor nanostructure according to a second embodiment of the present invention.

以下將結合附圖詳細說明本發明實施例提供之半導體奈米結構。 The semiconductor nanostructure provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

本發明提供一種半導體奈米結構,該半導體奈米結構包括一基底及至少一個脊部。該基底包括一第一晶面及垂直於該第一晶面之第二晶面,所述至少一個脊部從所述基底中之第一晶面開始沿所述第二晶面之晶面取向延伸出。所述第一晶面之晶面取向為(001)或(110),所述第二晶面之晶面取向為垂直於該第一晶面之晶面取向之(110)或(001)。具體為,若該基底之第一晶面之晶面取向為(001),則該基底之第二晶面之晶面取向(110),若該基底之第一晶面之晶面取向為(110),則該基底之第二晶面之晶面取向為(001)。 The present invention provides a semiconductor nanostructure comprising a substrate and at least one ridge. The substrate includes a first crystal plane and a second crystal plane perpendicular to the first crystal plane, and the at least one ridge is oriented from the first crystal plane of the substrate along the crystal plane of the second crystal plane Extend out. The crystal plane orientation of the first crystal plane is (001) or (110), and the crystal plane orientation of the second crystal plane is (110) or (001) perpendicular to the crystal plane orientation of the first crystal plane. Specifically, if the crystal plane orientation of the first crystal plane of the substrate is (001), the crystal plane orientation (110) of the second crystal plane of the substrate, if the crystal plane orientation of the first crystal plane of the substrate is ( 110), the crystal plane orientation of the second crystal face of the substrate is (001).

請參閱圖1,本發明第一實施例提供一種半導體奈米結構10,該半導體奈米結構10包括一基底12、複數脊部14及複數溝道16。該基底12具有一晶面取向為(110)之第一晶面13及一晶面取向為(001)之第二晶面15。該複數脊部14從所述基底12中之第一晶面13開始沿所述第二晶面15之晶面取向( 001)延伸出,且該複數脊部14沿該基底12之長度方向連續地間隔設置。相鄰之兩個脊部14之間定義為一溝道16。 Referring to FIG. 1, a first embodiment of the present invention provides a semiconductor nanostructure 10 including a substrate 12, a plurality of ridges 14, and a plurality of channels 16. The substrate 12 has a first crystal plane 13 having a crystal plane orientation of (110) and a second crystal plane 15 having a crystal plane orientation of (001). The plurality of ridges 14 are oriented from the first crystal plane 13 in the substrate 12 along the crystal plane of the second crystal plane 15 ( 001) is extended, and the plurality of ridges 14 are continuously spaced apart along the length direction of the substrate 12. The adjacent two ridges 14 are defined as a channel 16.

所述基底12為一半導體材料,其由複數該半導體材料之原子層相互層疊形成,其材料具體可為矽、鍺、碳化矽或鍺化矽等。該基底12之形狀為一膜狀結構,該膜狀結構之厚度方向為z軸方向,寬度方向為x軸方向,長度方向為y軸方向。該基底12之寬度和長度不限,可根據實際需要選定。該基底12之厚度不能太大,太大則不會出現量子限制效應,從而使空穴無法限制於該基底12之內部,故,該基底12應具有較小之厚度,當該基底12之厚度小到一固定值時,可使能級發生改變,從而出現量子限制效應,優選地,該基底12之厚度為5個該基底材料原子層~15個該基底材料之原子層。本實施例中,該基底12為8個矽原子層厚度之單晶矽膜,即該矽膜之厚度為13.4Å。所謂量子限制效應係指微結構中之至少一維度與電子德布羅意(deBroglie)波長相當,故電子在此維度中之運動受到限制,電子態呈量子化分佈,連續之能帶將分解為離散之能級,當能級間距大於某些特徵能量(如熱運動)時,該微結構將表現出和大塊樣品不同之甚至係特有之性質。 The substrate 12 is a semiconductor material formed by laminating a plurality of atomic layers of the semiconductor material, and the material thereof may specifically be tantalum, niobium, tantalum carbide or tantalum or the like. The shape of the substrate 12 is a film-like structure in which the thickness direction is the z-axis direction, the width direction is the x-axis direction, and the length direction is the y-axis direction. The width and length of the substrate 12 are not limited and can be selected according to actual needs. The thickness of the substrate 12 cannot be too large, and if it is too large, the quantum confinement effect does not occur, so that holes cannot be confined to the inside of the substrate 12. Therefore, the substrate 12 should have a small thickness when the thickness of the substrate 12 is When the value is as small as a fixed value, the energy level is changed, so that the quantum confinement effect occurs. Preferably, the thickness of the substrate 12 is 5 atomic layers of the base material layer to 15 atomic layers of the base material. In this embodiment, the substrate 12 is a single crystal germanium film having a thickness of 8 germanium atoms, that is, the thickness of the germanium film is 13.4 Å. The so-called quantum confinement effect means that at least one dimension in the microstructure is equivalent to the deBroglie wavelength, so the motion of electrons in this dimension is limited, the electronic state is quantized, and the continuous energy band is decomposed into Discrete energy levels, when the energy level spacing is greater than some characteristic energy (such as thermal motion), the microstructure will exhibit even unique properties that are different from bulk samples.

所述脊部14與所述基底12一體成形,該脊部14之主體材料與基底12之材料相同,本實施例為單晶矽。且該脊部14之主體材料中還進一步均勻摻雜有一受主摻雜原子,該受主摻雜原子在該基底12中之濃度不限,可根據實際情況選定。所述受 主摻雜原子可為硼、銦或鎵等,該受主摻雜原子可使該整個半導體奈米結構10具有較高濃度之空穴,從而使該整個半導體奈米結構10成為P型半導體奈米結構。 The ridge 14 is integrally formed with the substrate 12, and the material of the ridge 14 is the same as that of the substrate 12. This embodiment is a single crystal crucible. The host material of the ridge portion 14 is further uniformly doped with an acceptor dopant atom, and the concentration of the acceptor dopant atom in the substrate 12 is not limited, and may be selected according to actual conditions. The subject The main doping atom may be boron, indium or gallium, etc., and the acceptor doping atom may cause the entire semiconductor nanostructure 10 to have a higher concentration of holes, thereby making the entire semiconductor nanostructure 10 a P-type semiconductor Rice structure.

本實施例中,該複數脊部14皆均勻摻雜有受主原子硼。該摻雜原子僅摻雜於脊部14,根據調製摻雜效應,該摻雜原子和空穴在空間上會相分離,即經過摻雜後,摻雜原子會基本分佈於所述複數脊部14中,而由該摻雜原子所提供之空穴會大部分分佈於所述基底12中。 In this embodiment, the plurality of ridges 14 are uniformly doped with boron as the acceptor atom. The doping atoms are only doped to the ridges 14. According to the modulation doping effect, the doping atoms and the holes are spatially separated, that is, after doping, the doping atoms are substantially distributed in the plurality of ridges. In 14, the holes provided by the dopant atoms are mostly distributed in the substrate 12.

該脊部14可為任意形狀,其高度方向為z軸方向,其高度大於4個基底材料之原子層,該高度越大,摻雜入該脊部14之摻雜原子之含量可更高,且該摻雜原子所提供之空穴含量也更高,根據量子限制效應,摻雜原子所提供之空穴大部分會被限制於基底12中,從而可使得該半導體奈米結構10之基底12具有更大之空穴濃度。該脊部14之寬度方向為y軸方向,該脊部14之寬度和長度設定均以該脊部14之一半高度處之截面寬度和長度為基準,該脊部14之半高度之截面寬度小於10奈米。另外,該複數脊部14之寬度可以相同也可以不同。該脊部14半高度處之截面長度方向為圖中x軸方向,該長度不限。 The ridge portion 14 may have any shape with a height direction of a z-axis direction and a height greater than that of the atomic layers of the four base materials. The higher the height, the higher the content of dopant atoms doped into the ridge portion 14 may be. And the content of holes provided by the dopant atoms is also higher. According to the quantum confinement effect, most of the holes provided by the dopant atoms are confined in the substrate 12, so that the substrate 12 of the semiconductor nanostructure 10 can be made. Has a larger hole concentration. The width direction of the ridge portion 14 is the y-axis direction, and the width and length of the ridge portion 14 are set based on the cross-sectional width and length at one half height of the ridge portion 14. The half-height of the ridge portion 14 has a smaller cross-sectional width. 10 nm. In addition, the width of the plurality of ridges 14 may be the same or different. The longitudinal direction of the section at the half height of the ridge 14 is the x-axis direction in the drawing, and the length is not limited.

本實施例中,該脊部14為一立方體形狀,該脊部14之高度為4個所述基底材料之原子層之高度,即為5.5Å。該脊部14之長度與基底12之寬度可以相同或不同,本實施例中,該脊部14之長度與基底12之寬度相同。 In this embodiment, the ridge portion 14 has a cubic shape, and the height of the ridge portion 14 is the height of the atomic layer of the four base materials, that is, 5.5 Å. The length of the ridge 14 may be the same as or different from the width of the substrate 12. In this embodiment, the length of the ridge 14 is the same as the width of the substrate 12.

請參閱圖2,圖中虛線表示脊部14之寬度與脊部14和基底12間之能量之間之關係,從圖中可以發現,該基底12和脊部14之能量差大小與脊部14之寬度呈反比,故,當脊部14之寬度較小時,如圖中所示小於10奈米,該脊部14和基底12之能量差較大,量子限制效應較明顯,使得空穴被強烈地限制於基底12,從而可提高空穴之遷移率。圖中實線表示脊部14之寬度與空穴在脊部14之佔有率之間之關係,從圖中可以發現,空穴在脊部14之佔有率與脊部14之寬度呈正比,即,隨著脊部14頂表面寬度變大,空穴在脊部14之佔有率變大,從圖中可以發現,脊部14之寬度小於10奈米時,該脊部14之空穴佔有率較小,即小於14%,量子限制效應明顯,從而使摻雜原子所提供之空穴僅有少部分分佈於脊部14中,大部分則分佈於基底12中,而由於該脊部14具有較多之摻雜原子,從而使得影響基底12中空穴遷移率之雜質散射不明顯,使空穴遷移率變高。故,該脊部14之寬度越小,量子限制效應越明顯,該半導體奈米結構10之基底12中之空穴佔有率越大,而由於該脊部14具有較多之摻雜原子,從而使得雜質散射不明顯,使空穴遷移率變高。該脊部14之寬度應小於10奈米,優選為0.6奈米~2.1奈米,本實施例中,該脊部14之寬度為1奈米。 Referring to FIG. 2, the dotted line indicates the relationship between the width of the ridge 14 and the energy between the ridge 14 and the substrate 12. As can be seen from the figure, the energy difference between the substrate 12 and the ridge 14 and the ridge 14 The width is inversely proportional. Therefore, when the width of the ridge 14 is small, as shown in the figure, less than 10 nm, the energy difference between the ridge 14 and the substrate 12 is large, and the quantum confinement effect is more obvious, so that the hole is It is strongly confined to the substrate 12, so that the mobility of holes can be improved. The solid line in the figure indicates the relationship between the width of the ridge 14 and the occupancy of the cavity at the ridge 14. As can be seen from the figure, the occupancy of the cavity in the ridge 14 is proportional to the width of the ridge 14, that is, As the width of the top surface of the ridge 14 becomes larger, the occupancy of the cavity in the ridge 14 becomes larger. It can be seen from the figure that the cavity occupancy of the ridge 14 is less than 10 nm. Smaller, i.e., less than 14%, has a significant quantum confinement effect such that only a small portion of the holes provided by the dopant atoms are distributed in the ridges 14, most of which are distributed in the substrate 12, since the ridges 14 have A larger number of doped atoms make the scattering of impurities affecting the hole mobility in the substrate 12 less pronounced, resulting in higher hole mobility. Therefore, the smaller the width of the ridge 14 is, the more pronounced the quantum confinement effect is, the larger the hole occupation ratio in the substrate 12 of the semiconductor nanostructure 10 is, and since the ridge 14 has more dopant atoms, The scattering of impurities is made inconspicuous, and the hole mobility becomes high. The width of the ridge 14 should be less than 10 nm, preferably 0.6 nm to 2.1 nm. In this embodiment, the width of the ridge 14 is 1 nm.

所述溝道16之寬度,即相鄰兩個脊部14之間之距離以確保相鄰之兩個脊部14之間無原子間之直接相互作用力為宜,從而使得脊部14之空穴只能移動到基底12,而不能在各個脊部14之間相互移動,使量子限制效應更加明顯,該溝道16之寬度 方向為圖中y軸方向,本實施例中,該溝道16之寬度需大於10個基底材料之原子層。 The width of the channel 16, i.e., the distance between adjacent two ridges 14 is such that there is no direct interaction between the adjacent two ridges 14 so that the ridge 14 is empty. The holes can only move to the substrate 12, but cannot move between the respective ridges 14, making the quantum confinement effect more pronounced, and the width of the channel 16 The direction is the y-axis direction in the figure. In this embodiment, the width of the channel 16 needs to be greater than 10 atomic layers of the base material.

可見,該半導體奈米結構10整體為一圖形化結構,該圖形化結構可引起量子限制效應之產生,使空穴之分佈受到顯著之調製,且空穴被強烈地束縛在基底12內。所述脊部14從所述基底12之第一晶面13開始沿所述第二晶面15之晶面取向(001)延伸出,該延伸方向使基底12和脊部14內之能帶各向異性,從而使半導體奈米結構10中之價帶頂被強烈地限制在基底12內,故使整個半導體奈米結構10之空穴之分佈得到調製,使空穴被強烈地限制在基底12內。具體之,上述圖形化之半導體奈米結構10可使其內之能帶發生疊帶效應並形成第一子價帶和第二子價帶,且該能帶之價帶頂遠離其第二子價帶,即該價帶頂與第二子價帶之間具有較寬之禁帶,使空穴在兩者之間較難躍遷,故,空穴之遷移主要受價帶頂周圍之第一子價帶之影響,而該價帶頂與第一子價帶中之空穴具有基本相同之空間分佈,即其中之空穴基本完全分佈於基底12內部,從而使得量子限制效應很明顯,即該半導體奈米結構10之空穴大部分被限制在該基底12中。 It can be seen that the semiconductor nanostructure 10 as a whole is a patterned structure which can cause a quantum confinement effect, the distribution of holes is significantly modulated, and the holes are strongly bound in the substrate 12. The ridge portion 14 extends from the first crystal face 13 of the substrate 12 along the crystal face orientation (001) of the second crystal face 15, and the extension direction causes the energy bands in the substrate 12 and the ridge portion 14 to be respectively The anisotropy, so that the valence band top in the semiconductor nanostructure 10 is strongly confined within the substrate 12, so that the distribution of the holes of the entire semiconductor nanostructure 10 is modulated such that the holes are strongly confined to the substrate 12. Inside. Specifically, the patterned semiconductor nanostructure 10 can have a banding effect on the energy band therein and form a first sub-valency band and a second sub-valence band, and the valence band of the band is away from the second sub-portion. The valence band, that is, the wider band gap between the top of the valence band and the second sub-price band, makes the hole more difficult to transition between the two, so the migration of holes is mainly the first around the top of the valence band. The influence of the sub-valence band, and the valence band top has substantially the same spatial distribution as the holes in the first sub-valence band, that is, the holes therein are substantially completely distributed inside the substrate 12, so that the quantum confinement effect is obvious, that is, Most of the holes of the semiconductor nanostructure 10 are confined in the substrate 12.

此外,所述半導體奈米結構10進一步包括一保護層18,該保護層18可覆蓋於該半導體奈米結構10之所有表面,也可僅覆蓋該半導體奈米結構10中之脊部14和溝道16之表面,從而避免半導體奈米結構10之表面出現晶格馳豫現象,影響該整個結構之物理性能。本實施例中,該保護層18為一氫原子層。 In addition, the semiconductor nanostructure 10 further includes a protective layer 18 covering all surfaces of the semiconductor nanostructure 10, or only the ridges 14 and trenches of the semiconductor nanostructure 10 The surface of the track 16 prevents lattice relaxation on the surface of the semiconductor nanostructure 10, affecting the physical properties of the entire structure. In this embodiment, the protective layer 18 is a hydrogen atom layer.

可以理解,該半導體奈米結構10之脊部14也可以為一個,其具體數量可根據實際應用中所需載流子之濃度而定,若需要較高之載流子濃度,可設置較多之脊部14,從而可摻雜較多之受主原子,若所需載流子濃度較低,可設置較少之脊部14,從而可摻雜較少之受主原子。 It can be understood that the ridge portion 14 of the semiconductor nanostructure 10 can also be one. The specific number can be determined according to the concentration of carriers required in practical applications. If a higher carrier concentration is required, more can be set. The ridges 14 are thus doped with more acceptor atoms. If the required carrier concentration is lower, fewer ridges 14 can be provided, so that fewer acceptor atoms can be doped.

請參閱圖3,本發明第二實施例提供一種半導體奈米結構20,該半導體奈米結構20包括一基底22、複數脊部24及複數溝道26。該基底22包括一晶面取向為(001)之第一晶面23及一晶面取向為(110)之第二晶面25;該複數脊部24從所述基底22中之第一晶面23開始沿所述第二晶面25之晶面取向(110)延伸出,且該複數脊部24相互間隔設置;相鄰之兩個脊部24之間定義為一溝道26。 Referring to FIG. 3, a second embodiment of the present invention provides a semiconductor nanostructure 20 including a substrate 22, a plurality of ridges 24, and a plurality of channels 26. The substrate 22 includes a first crystal plane 23 having a crystal plane orientation of (001) and a second crystal plane 25 having a crystal plane orientation of (110); the plurality of ridge portions 24 from the first crystal plane of the substrate 22 23 begins to extend along the crystal plane orientation (110) of the second crystal plane 25, and the plurality of ridges 24 are spaced apart from each other; the adjacent two ridges 24 are defined as a channel 26.

該半導體奈米結構20之表面還進一步包括一保護層28,該保護層28覆蓋於該半導體奈米結構20之複數脊部24及複數溝道26之表面。本實施例與第一實施例之區別在於,本實施例中之第一晶面23之晶面取向為(001),第二晶面25之晶面取向為(110)。 The surface of the semiconductor nanostructure 20 further includes a protective layer 28 overlying the surface of the plurality of ridges 24 and the plurality of trenches 26 of the semiconductor nanostructure 20. The difference between this embodiment and the first embodiment is that the crystal plane orientation of the first crystal plane 23 in the present embodiment is (001), and the crystal plane orientation of the second crystal plane 25 is (110).

所述脊部24之主體材料與基底22之材料相同,且該脊部24之材料還包括一均勻摻雜於該主體材料之施主摻雜原子,該施主摻雜原子可為磷、砷或銻等,該施主摻雜原子可使整個半導體奈米結構20具有較高濃度之電子,從而使該整個半導體奈米結構20成為N型半導體奈米結構。 The material of the ridge portion 24 is the same as the material of the substrate 22, and the material of the ridge portion 24 further includes a donor dopant atom uniformly doped to the host material, and the donor dopant atom may be phosphorus, arsenic or antimony. Alternatively, the donor dopant atoms can cause the entire semiconductor nanostructure 20 to have a higher concentration of electrons, thereby making the entire semiconductor nanostructure 20 an N-type semiconductor nanostructure.

本實施例中,該半導體奈米結構20之基底22、脊部24及溝道26之尺寸,如長度、寬度和高度對該半導體奈米結構20之性質影響規律均與第一實施例中之基底12、脊部14及溝道16之尺寸對所述半導體奈米結構10之性質影響規律相似,故,該基底22、脊部24及溝道26之尺寸選擇原則與第一實施例之基底12、脊部14及溝道16之尺寸之選擇原則相同,在此不再贅述。 In this embodiment, the dimensions of the substrate 22, the ridges 24, and the channels 26 of the semiconductor nanostructure 20, such as the length, width, and height, affect the properties of the semiconductor nanostructure 20, and are the same as in the first embodiment. The size of the substrate 12, the ridges 14 and the channels 16 have similar effects on the properties of the semiconductor nanostructures 10. Therefore, the substrate 22, the ridges 24 and the trenches 26 have a size selection principle and the substrate of the first embodiment. 12. The selection of the dimensions of the ridges 14 and the channels 16 is the same, and will not be described herein.

本實施例中之半導體奈米結構20整體為一圖形化結構,該圖形化結構可使得基底22和脊部24內之能帶各向異性,使得價帶頂被強烈地限制在基底22內,從而使電子分佈受到顯著之調製。具體為,該圖形化之半導體奈米結構20可使其內之能帶發生疊帶效應並形成第一子價帶和第二子價帶,且該能帶之價帶頂遠離其第二子價帶,即該價帶頂與第二子價帶之間具有較寬之禁帶,使電子在兩者之間較難躍遷,故,電子之遷移主要受價帶頂周圍之第一子價帶之影響,而該價帶頂與第一子價帶中之電子具有基本相同之空間分佈,即其中之電子基本完全分佈於基底22內部,從而使得量子限制效應很明顯,且電子被強烈地束縛在基底22內,且電子與上述摻雜原子在空間上相互分離,從而可減少雜質散射對電子遷移率之影響。可以理解,脊部之數量也可以選擇為一個,其具體數量根據實際應用中所需載流子之濃度而定。 The semiconductor nanostructure 20 in this embodiment is a patterned structure that can make the energy band anisotropy in the substrate 22 and the ridges 24 such that the valence band top is strongly confined within the substrate 22. Thereby the electron distribution is significantly modulated. Specifically, the patterned semiconductor nanostructure 20 can have a banding effect on the energy band therein and form a first sub-valence band and a second sub-valency band, and the band edge of the band is away from the second sub-portion The valence band, that is, the wide band gap between the top of the price band and the second sub-price band makes the electrons difficult to transition between the two. Therefore, the migration of electrons is mainly subject to the first sub-price around the top of the price band. The influence of the band, and the valence band top has substantially the same spatial distribution as the electrons in the first sub-valence band, that is, the electrons therein are substantially completely distributed inside the substrate 22, so that the quantum confinement effect is obvious, and the electrons are strongly It is trapped in the substrate 22, and the electrons are spatially separated from the above-mentioned dopant atoms, thereby reducing the influence of impurity scattering on the electron mobility. It can be understood that the number of ridges can also be selected as one, and the specific number depends on the concentration of carriers required in practical applications.

本發明實施例之半導體奈米結構具有以下優點:由於本發明實施例提供之半導體奈米結構可使空穴或電子被強烈地束縛 在基底中,且根據調製摻雜效應,脊部之摻雜原子和電子或空穴在空間上相互分離,即摻雜原子大部分分佈在脊部,而空穴或電子則大部分分佈在基底中,從而使雜質散射對空穴或電子之遷移率影響較小,從而大大提高了空穴或電子之遷移率。 The semiconductor nanostructure of the embodiment of the invention has the following advantages: the semiconductor nanostructure provided by the embodiment of the invention can make holes or electrons strongly bound In the substrate, and according to the modulation doping effect, the doping atoms and electrons or holes of the ridge are spatially separated from each other, that is, the doping atoms are mostly distributed in the ridge, and the holes or electrons are mostly distributed on the substrate. Therefore, the scattering of impurities has less influence on the mobility of holes or electrons, thereby greatly increasing the mobility of holes or electrons.

綜上所述,本發明確已符合發明專利之要件,遂依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。 In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

10‧‧‧半導體奈米結構 10‧‧‧Semiconductor nanostructure

12‧‧‧基底 12‧‧‧Base

13‧‧‧第一晶面 13‧‧‧First crystal face

14‧‧‧脊部 14‧‧‧ ridge

15‧‧‧第二晶面 15‧‧‧Second crystal face

16‧‧‧溝道 16‧‧‧Channel

18‧‧‧保護層 18‧‧‧Protective layer

Claims (17)

一種半導體奈米結構,其包括:一基底及至少一個脊部,該基底包括一第一晶面及垂直於該第一晶面之第二晶面,所述至少一個脊部從所述基底中之第一晶面開始沿所述第二晶面之晶面取向延伸出,所述基底之厚度為5個所述基底材料原子層~15個所述基底材料原子層之厚度。 A semiconductor nanostructure comprising: a substrate and at least one ridge, the substrate comprising a first crystal plane and a second crystal plane perpendicular to the first crystal plane, the at least one ridge from the substrate The first crystal plane begins to extend along the crystal plane orientation of the second crystal plane, and the thickness of the substrate is a thickness of 5 atomic layers of the base material to 15 atomic layers of the base material. 如請求項第1項所述之半導體奈米結構,其中,所述第一晶面之晶面取向為(110),所述第二晶面之晶面取向為(001)。 The semiconductor nanostructure of claim 1, wherein the crystal plane orientation of the first crystal plane is (110), and the crystal plane orientation of the second crystal plane is (001). 如請求項第1項所述之半導體奈米結構,其中,所述第一晶面之晶面取向為(001),所述第二晶面之晶面取向為(110)。 The semiconductor nanostructure of claim 1, wherein the crystal plane orientation of the first crystal plane is (001), and the crystal plane orientation of the second crystal plane is (110). 如請求項第2或3項所述之半導體奈米結構,其中,所述脊部之一半高度處之截面寬度小於10奈米。 The semiconductor nanostructure of claim 2, wherein the cross-sectional width at one half of the ridge is less than 10 nm. 如請求項第2項所述之半導體奈米結構,其中,所述脊部進一步摻雜有一摻雜原子,該摻雜原子為硼、銦或鎵。 The semiconductor nanostructure of claim 2, wherein the ridge is further doped with a dopant atom, and the dopant atom is boron, indium or gallium. 如請求項第3項所述之半導體奈米結構,其中,所述脊部進一步摻雜有一摻雜原子,該摻雜原子為磷、砷或銻。 The semiconductor nanostructure of claim 3, wherein the ridge is further doped with a dopant atom, which is phosphorus, arsenic or antimony. 如請求項第2或3項所述之半導體奈米結構,其中,所述半導體奈米結構包括複數脊部,該複數脊部沿所述基底之長度方向連續地間隔設置,該相鄰之兩個脊部之間定義為一溝道。 The semiconductor nanostructure of claim 2, wherein the semiconductor nanostructure comprises a plurality of ridges, the plurality of ridges being continuously spaced apart along a length of the substrate, the adjacent two The ridges are defined as a channel. 如請求項第7項所述之半導體奈米結構,其中,所述基底由複數原子層層疊形成。 The semiconductor nanostructure of claim 7, wherein the substrate is formed by laminating a plurality of atomic layers. 如請求項第8項所述之半導體奈米結構,其中,所述溝道之 寬度大於10個基底材料原子層。 The semiconductor nanostructure of claim 8, wherein the channel Width greater than 10 atomic layers of substrate material. 如請求項第8項所述之半導體奈米結構,其中,所述基底之厚度為8個所述基底材料原子層之厚度。 The semiconductor nanostructure of claim 8, wherein the thickness of the substrate is 8 thicknesses of the atomic layer of the base material. 如請求項第1項所述之半導體奈米結構,其中,所述基底和脊部之材料為矽。 The semiconductor nanostructure of claim 1, wherein the material of the substrate and the ridge is ruthenium. 如請求項第1項所述之半導體奈米結構,其中,該半導體奈米結構進一步包括一設置於該半導體奈米結構脊部及溝道表面之保護層。 The semiconductor nanostructure of claim 1, wherein the semiconductor nanostructure further comprises a protective layer disposed on the ridge and the channel surface of the semiconductor nanostructure. 如請求項第12項所述之半導體奈米結構,其中,所述保護層由複數氫原子組成。 The semiconductor nanostructure of claim 12, wherein the protective layer is composed of a plurality of hydrogen atoms. 一種半導體奈米結構,其包括:一基底及至少一脊部,該基底包括一第一晶面及垂直於該第一晶面之第二晶面,所述至少一個脊部從所述基底中之第一晶面開始沿所述第二晶面之晶面取向延伸出,該基底之材料為矽,該脊部之材料由矽及均勻分散於該矽中之複數P型摻雜原子組成,該第一晶面之晶面取向為(110),該第二晶面之晶面取向為垂直於該第一晶面取向之(001),該脊部之一半高度處截面之寬度小於10奈米。 A semiconductor nanostructure comprising: a substrate and at least one ridge, the substrate comprising a first crystal plane and a second crystal plane perpendicular to the first crystal plane, the at least one ridge from the substrate The first crystal plane begins to extend along the crystal plane orientation of the second crystal plane, and the material of the substrate is germanium, and the material of the spine is composed of germanium and a plurality of P-type dopant atoms uniformly dispersed in the crucible. The crystal plane orientation of the first crystal plane is (110), and the crystal plane orientation of the second crystal plane is (001) perpendicular to the orientation of the first crystal plane, and the width of the cross section at one half height of the ridge is less than 10 nm. Meter. 如請求項第14項所述之半導體奈米結構,其中,所述半導體奈米結構包括複數脊部,該相鄰之兩個脊部之間定義為一溝道,該溝道之寬度大於10個所述基底材料之原子層。 The semiconductor nanostructure of claim 14, wherein the semiconductor nanostructure comprises a plurality of ridges defined as a channel between the two adjacent ridges, the channel having a width greater than 10 An atomic layer of the substrate material. 一種半導體奈米結構,其包括:一基底及至少一脊部,該基底包括一第一晶面及垂直於該第一晶面之第二晶面,所述至少一個脊部從所述基底中之第一晶面開始沿所述第二晶面之 晶面取向延伸出,該基底之材料為矽,該脊部之材料由矽及均勻分散於該矽中之複數N型摻雜原子組成,該第一晶面之晶面取向為(001),該第二晶面之晶面取向為垂直於該第一晶面取向之(110),該脊部之一半高度處截面之寬度小於10奈米。 A semiconductor nanostructure comprising: a substrate and at least one ridge, the substrate comprising a first crystal plane and a second crystal plane perpendicular to the first crystal plane, the at least one ridge from the substrate a first crystal face begins along the second crystal face The orientation of the crystal plane is extended, and the material of the substrate is ruthenium, and the material of the ridge portion is composed of ruthenium and a plurality of N-type dopant atoms uniformly dispersed in the ruthenium, and the crystal plane orientation of the first crystal plane is (001), The crystal plane orientation of the second crystal plane is oriented perpendicular to the first crystal plane orientation (110), and the width of the cross section at one half height of the ridge portion is less than 10 nm. 如請求項第16項所述之半導體奈米結構,其中,所述半導體奈米結構包括複數脊部,該相鄰之兩個脊部之間定義為一溝道,該溝道之寬度大於10個所述基底材料之原子層。 The semiconductor nanostructure of claim 16, wherein the semiconductor nanostructure comprises a plurality of ridges defined as a channel between the two adjacent ridges, the channel having a width greater than 10 An atomic layer of the substrate material.
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TW200711240A (en) * 2005-06-30 2007-03-16 Intel Corp Planar waveguides with air thin films used as antireflective layers, beam splitters and mirrors
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200711240A (en) * 2005-06-30 2007-03-16 Intel Corp Planar waveguides with air thin films used as antireflective layers, beam splitters and mirrors
US20080135888A1 (en) * 2006-12-08 2008-06-12 Deok-Hyung Lee FinFET and method of manufacturing the same

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