TWI404067B - Memory device and method for operating the memory device - Google Patents

Abstract

A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.

Description

Memory device and method of operating same

The present invention relates to a method of operating a memory device, and more particularly to a method of operating a flash memory.

The flash memory has the advantages of multiple operations such as storing, reading, erasing, etc., and the stored data does not disappear after power-off, so it becomes a personal computer, a portable computer, and a digital device. A non-volatile memory component widely used in electronic devices such as cameras. However, after a period of use of the flash memory, there will be some errors in the bits, which may result in data access errors. In view of the above, the prior art generally uses an Error Correction Code to perform error correction.

1A and 1B are respectively a flow chart of a prior art method of programming and reading a flash memory using an error correction code. As shown in FIG. 1A, in the process of staging the flash memory, the prior art stores the received user data into the temporary memory (steps S111 and S112), that is, generates an error according to the user data. The correction code is encoded (step S113), and the user data and the error correction code are simultaneously written into the flash memory (step S114). Thereby, as shown in FIG. 1B, in the process of reading the flash memory, the prior art stores the read error correction code and the read data into the register (steps S121 and S122), that is, The error correction code can be used to correct the read data, and further the user data is obtained (step S123). By the prior art, the user profile can be temporarily stored and outputted (steps S124 and S125).

It is worth noting that for multi-level cell (MLC) flash memory, since it records the bit information through a plurality of different levels of threshold voltage, as shown in FIG. 2 The MLC flash memory tends to have an overlap distribution 210 of the threshold voltage VT, so that the read level RD cannot distinguish the bit information. In addition, over-programming of memory cells and charge loss are the main causes of threshold voltage shift, and over-stylization occurs in the process of writing user data to flash memory. And the charge loss is continuously accumulated as the memory cell circulates.

For the prior art, it simply uses the single error correction code generated prior to writing the user profile for error correction. Therefore, the prior art must continuously improve the error correction code for errors caused by over-stylization of the user data during writing, or errors caused by charge loss after the user data is written. The number of bits can be corrected for errors. However, with the increase in the number of correctable bits of the error correction code, it has been necessary in the prior art to add hardware facilities to support the calculation of complex and large error correction codes.

The present invention provides a method of operating a memory device that, in addition to facilitating the improvement of the correction capability of the memory device, further contributes to reducing the complexity of the hardware device of the memory device.

The invention provides a method for operating a memory device, which can improve the correction capability of the memory device.

The present invention provides a memory device with better correction capabilities.

The present invention provides a method of operating a memory device comprising the following steps. In the process of controlling the memory device, a first error correction code is generated based on a user profile. Next, the user data is written to the memory device. Thereafter, the user data in the memory device is read, and a second error correction code is generated based on the read user data. Finally, the first and second error correction codes are written to the memory device.

From another point of view, the present invention further provides a method for operating a memory device, wherein the memory device stores a first and a second error correction code, and the method of operating the memory device includes the following steps: Reading a first error correction code, a second error correction code, and a read data in the memory device; then, correcting the read data with the second error correction code to obtain a temporary data; and using the first error correction The code corrects the temporary data to obtain a user profile.

In an embodiment of the present invention, the method for operating the memory device further includes: storing the read data to a temporary storage device; updating the read data stored in the temporary storage device with temporary data; Update temporary data stored in the scratchpad; and output user data.

The invention further provides a memory device comprising a memory, an error correction circuit and an operation circuit. The error correction circuit is electrically connected to the memory. The operation circuit is configured to cause the error correction circuit to generate a first error correction code according to a user data that has not been written to the memory, and to cause the error correction circuit to generate a second error according to a read data from the memory. Correction code.

Based on the above, the present invention generates first and second error correction codes before and after the user data is stored in the memory device. Thereby, the present invention can use the first and second error correction codes to perform phase correction on the user data, thereby enabling the present invention to utilize the first and second error correction codes of the lower correctable bit number, ie Good correction ability can be achieved. In other words, the present invention will reduce the complexity of the hardware facility as compared to the prior art.

The above described features and advantages of the present invention will be more apparent from the following description.

3 is a flow chart of a method for operating a memory device according to an embodiment of the invention, and FIG. 4 is a flow chart of a method for operating a memory device according to another embodiment of the present invention. The flow of the stylized memory device will be described, and the flow of reading the memory device will be described mainly with reference to FIG. In addition, the operation methods described in the embodiments of FIG. 3 and FIG. 4 can be applied to multi-level memory cell flash memory, but are not intended to limit the present invention.

Referring to FIG. 3, in the process of programming the memory device, the embodiment first receives a user data as shown in step S310, and stores the received user data in a temporary storage in step S320. In the device. Next, as shown in step S330, a first error correction code is generated based on the user profile.

On the other hand, in step S340, the user profile is written to the memory device. Further, in view of the detailed flow of data writing, first, in step S341, the memory device is programmed according to the user data. Then, in step S342, a write verification is performed on the memory device to determine whether the programmed memory cell in the memory device has a threshold voltage level that matches the bit information of the user data. Next, in step S343, it is determined whether the memory device passes the write verification. Thereby, when the write verification has not passed, the above steps S341 to S343 are repeated. On the other hand, when the write verification is passed, step S350 will be performed.

In step S350, the user profile in the memory device will be read. It is worth noting that in the process of writing user data, user data may generate error bits due to over-programming. In addition, after the user data is written, the user data may also generate an error bit due to charge loss. Therefore, the user data read in step S350 may have an error bit and is regarded as a piece of read data.

Referring to FIG. 3, after reading the user data in the memory device, a second error correction code is generated according to the read user data in step S360. Next, in step S370, the first and second error correction codes are written to the memory device. Thereby, the user data can be phase-corrected by using the first and second error correction codes, thereby enabling the embodiment to utilize the first and second error correction codes of the lower correctable bit number. Good correction ability.

For example, as shown in FIG. 4, in the process of reading the memory device, first, in step S410, the first error correction in the memory device is read according to the address stored in the original user data. The code, the second error correction code, and a read data. It should be noted that the read data defined in step S350 and step S410 is actually the user data read from the memory device at different time points. Since the reading time point is different, the user data (reading data) read in step S350 and the user data (reading data) read in step S410 are different. The degree of charge loss may vary.

Referring to FIG. 4, in step S420, the read data is stored in a temporary storage device, and through step S430, the read data is corrected by using the second error correction code to obtain a temporary data. In the process of correcting the read data, first, in step S431, the error bit of the read data is detected by using the second error correction code and the read data. Thereafter, in step S432, the error bit of the read data is corrected to obtain temporary data. In other words, in this embodiment, the second error correction code is used to perform the first stage correction on the partial bit error formed by the charge loss.

Next, in step S440, the read data stored in the temporary storage is updated with the temporary data, so that the temporary data is stored in the temporary storage. On the other hand, as shown in step S450, the temporary data is corrected using the first error correction code to obtain user data. In the process of correcting the temporary data, first, in step S451, the error bit of the temporary data is detected by using the first error correction code and the temporary data. Next, in step S452, the error bit of the temporary data is corrected to obtain user data.

In other words, in the present embodiment, the first error correction code is used to perform the second-stage correction on the bit error caused by over-staging and charge loss. Therefore, in this embodiment, the temporary data stored in the temporary storage device is updated by the user data through the step S460, so that the user data is stored in the temporary storage device, and the user data is output through the step S470.

FIG. 5 is a circuit block diagram of a memory device according to an embodiment of the invention. Referring to FIG. 5, the memory device 500 includes an operation circuit 510, an error correction circuit 520, a register 530, and a memory 540. The error correction circuit 520 and the register 530 are electrically connected to the memory 540. The operation circuit 510 is electrically connected to the error correction circuit 520 and the register 530.

When the memory device 500 receives the user profile, the user profile is temporarily stored in the register 530, and the operation circuit 510 causes the error correction circuit 520 to generate based on the user profile that has not been written to the memory 540. A first error correction code. User data is then written to memory 540. When the memory 540 is verified by writing, the user data stored in the memory 540 will be read. It is worth noting that the user data read may be misinterpreted or/and the loss of charge with incorrect bits and is considered a read data. At this time, the operation circuit 510 will cause the error correction circuit 520 to generate a second error correction code based on the read data.

In a read mode of operation, error correction circuit 520 will again read the user profile stored in memory 540. It is worth noting that the user bits read from the memory device may have their error bits increased over time due to different degrees of charge loss, so the read from the memory 540 is read again. The data will be treated as another reading. Thereafter, the operation circuit 510 will use the second error correction code to correct another read data to obtain a temporary data, and use the first error correction code to correct the temporary data to obtain the original user data. The temporary data and the read data may be temporarily stored in the temporary register 530. The detailed operation of the memory device 500 is included in the above embodiments, and thus will not be described herein.

In summary, the present invention separately encodes user data before and after being stored in the memory device to generate first and second error correction codes. Thereby, the present invention can use the first and second error correction codes to perform phase correction on the user data, thereby enabling the present invention to utilize the first and second error correction codes of the lower correctable bit number, ie Good correction ability can be achieved.

For example, if the number of correctable bits of the first and second error correction codes is N bits and M bits, respectively, and N and M are positive integers, if N is greater than M, the present invention only needs to carry The N-bit correction capability error-correct-algorithm, in contrast, if M is greater than N', the present invention only requires an error correction algorithm with M-bit correction capability. That is to say, the invention can be pre-set to a suitable number, in particular for the characteristics of 矽, where the erroneous bit is mainly controlled in the stage of pass-through verification or later. However, prior art always requires an error correction algorithm with (N+M) bit correction capability to provide correction data. Thereby, the present invention can achieve a good correction capability without increasing the number of correctable bits of the first and second error correction codes as compared with the prior art. In other words, the present invention will reduce the complexity of the hardware installation and contribute to the increase in the operating speed of the memory.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

S111~S114. . . Used to illustrate the flow of each step of Figure 1A

S121~S125. . . Used to illustrate the flow of each step of Figure 1B

210. . . Overlapping distribution

S310~S370, S341~S343. . . Used to explain the steps of the steps of the embodiment of FIG.

S410~S470, S431, S432, S451, S452. . . Used to explain the steps of the steps of the embodiment of FIG.

500. . . Memory device

510. . . Operating circuit

520. . . Error correction circuit

530. . . Register

540. . . Memory

1A is a flow chart of a prior art method of staging a flash memory using an error correction code.

FIG. 1B is a flow chart of a prior art method of reading a flash memory using an error correction code.

2 is a schematic diagram showing the distribution of the threshold voltage of the MLC flash memory.

3 is a flow chart of a method of operating a memory device in accordance with an embodiment of the invention.

4 is a flow chart showing a method of operating a memory device in accordance with another embodiment of the present invention.

FIG. 5 is a circuit block diagram of a memory device according to an embodiment of the invention.

S310~S370, S341~S343. . . Used to explain the steps of the steps of the embodiment of FIG.

Claims (10)

A method for operating a memory device, comprising: generating a first error correction code according to a user data; writing the user data to the memory device; reading the user data in the memory device, and Generating a second error correction code based on the read user data; and writing the first and second error correction codes to the memory device. The method of operating a memory device according to claim 1, wherein the step of writing the user data to the memory device comprises: programming the memory device according to the user data; The device performs a write verification; determines whether the memory device passes the write verification; and repeats the above three steps when the write verification has not passed. The method of operating a memory device according to claim 1, wherein the memory device is a multi-level memory cell flash memory. A method for operating a memory device includes: generating a first error correction code based on a user data that has not been written to the memory; and reading the user data written to the memory to obtain a first Reading the data, and generating a second error correction code according to the first read data; writing the first and the second error correction code to the memory device; reading the first in the memory device Error correction code and the second error correction code, and reading the user data written to the memory again Obtaining a second read data; correcting the second read data by using the second error correction code to obtain a temporary data; and correcting the temporary data by using the first error correction code to obtain the user data. The method of operating the memory device of claim 4, further comprising: storing the second read data to a temporary register; and updating the second stored in the temporary register with the temporary data Reading the data; updating the temporary data stored in the temporary register with the user data; and outputting the user data. The method of operating a memory device according to claim 4, wherein the step of correcting the second read data by using the second error correction code to obtain the temporary data comprises: using the second error correction code and The second read data, detecting an error bit of the second read data; and correcting the error bit of the second read data to obtain the temporary data. The method for operating a memory device according to claim 4, wherein the step of correcting the temporary data by using the first error correction code to obtain the user data comprises: using the first error correction code and the temporary Data, detecting the temporary The error bit of the data; and correcting the error bit of the temporary data to obtain the user data. The method of operating a memory device according to claim 4, wherein the memory device is a multi-level memory cell flash memory. A memory device includes: a memory; an error correction circuit electrically connected to the memory; and an operation circuit for causing the error correction circuit to be based on a user data not yet written to the memory A first error correction code is generated and configured to cause the error correction circuit to generate a second error correction code based on a read data from the memory. The memory device of claim 9, wherein the operation circuit in a read operation mode causes the error correction circuit to: read a data from the memory; and utilize the second error correction code Correcting the data read from the memory to obtain a temporary data; and correcting the temporary data by using the first error correction code to obtain the user data.