TWI401754B - Method of manufacturing semiconductor device - Google Patents

Description

Semiconductor device manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device using a through-silicon via (TSV) technique.

A three-dimensional integrated circuit (3D IC) is an advanced wafer stacking technology that stacks chips with different functions into a three-dimensional integrated circuit (IC). Compared with the two-dimensional IC, the 3D IC stacking technology not only shortens the 3D IC signal transmission path, but also speeds up the operation of the 3D IC and has low power consumption. To implement 3D IC stacking technology, TSV technology is a new generation technology that enables stacked wafers to be interconnected. TSV technology makes the signal transmission path between chips in 3D ICs shorter, so the performance of 3D ICs will be faster, and because there is no limit on the number of stacked crystals, TSV technology has become one of the hotkey technologies.

The traditional TSV technology manufacturing method first forms a plurality of blind vias on the wafer, then fills the blind vias with conductive materials, then thins the wafers, and finally forms bumps, diced wafers, stacked bumps, etc. Process.

The traditional TSV technology makes the perforation by grinding the back side of the wafer to make it thin until the blind holes become perforated. Generally, the depth of the blind hole is made deeper than the depth of the last hole. After thinning, some of the bottom of the blind hole will be ground, and the conductive material will be grounded, so the tradition The TSV technology will cause waste of conductive materials and increase costs.

Furthermore, the process time required to fill the deeper blind holes is longer, less economical, and the speed of filling the conductive material between the bottom of the blind hole and the inner wall of the deeper hole is controlled to make the blind hole sufficiently The process of plating without forming an unfilled hollow portion is difficult and the success rate is not high. In addition, blind holes with high aspect ratios tend to cause poor deposition quality of the insulating layer and the metal seed layer.

In summary, the current TSV technology still has the disadvantages of requiring a long filling time and a low success rate of filling holes, and adding some conductive materials to be ground and causing waste. These shortcomings still have to be overcome to facilitate the continued development of 3D IC technology.

One example of the present invention provides a method of fabricating a semiconductor device by which a through-silicon via (TSV) technique can be used to shorten the processing time, improve the reliability of its manufacturing, and reduce the waste of conductive materials. .

An embodiment of the method for fabricating a semiconductor device of the present invention first provides a wafer having an active surface and a back surface disposed opposite the active surface. Next, the back side of the wafer is polished to obtain a thinned wafer. Thereafter, a plurality of through holes having openings on the active surface and the back surface are formed on the thinned wafer. Then, an insulating layer is formed on the active surface of the thinned wafer and the inner walls of the through holes. Subsequently, a conductive layer is formed on the insulating layer. Next, the conductive material is electrochemically filled in the through holes. Thereafter, bumps are formed on at least one opening of each of the through holes. Finally, the thinned wafer is diced to form separate dies.

Another embodiment of the method of fabricating a semiconductor device of the present invention first provides a wafer having an active surface and a back surface disposed opposite the active surface. Next, the back side of the wafer is polished to obtain a thinned wafer. Thereafter, a plurality of through holes having openings on the active surface and the back surface are formed on the thinned wafer. Then, a conductive layer is formed on the back surface or the active surface. Next, the conductive material is electrochemically filled in the through holes. Thereafter, the conductive layer is removed. Then, bumps are formed on at least one opening of each of the through holes. Finally, the thinned wafer is diced to form separate dies.

1A to 1I are a series of schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1A, a method of fabricating a semiconductor device disclosed in a first embodiment of the present invention first provides a wafer 10. The wafer 10 includes an active surface 12 and a back surface 14 disposed opposite the active surface 12. The active surface 12 refers to the surface on which the wafer 10 carries integrated circuitry, while the back surface 14 can be substantially parallel to the active surface 12. Next, as shown in FIG. 1B, the back surface 14 of the wafer 10 is polished to a predetermined thickness to form a thinned wafer 16. The predetermined thickness may be between 10 microns and 200 microns, and preferably the predetermined thickness may be about 50 microns. Thereafter, as shown in FIG. 1C, a plurality of via holes 18 are formed on the thinned wafer 16. The through holes 18 extend through the thinned wafer 16 such that each of the through holes 18 has two openings (20a and 20b) on the active surface 12 and the back surface 14, respectively. The manner of forming a plurality of via holes 18 on the thinned wafer 16 may be selected from reactive ion etching (RIE), deep reactive ion etching (DRIE), laser (LASER), and wet etching (Wet etching). One of the methods. Then, as shown in FIG. 1D, an insulating layer 22 is formed on the active surface 12 of the thinned wafer 16 and the inner walls 24 of the through holes 18. The insulating layer 22 provides electrical insulation, which may additionally function as a barrier metal diffusion of the vias 18 to the thinned wafer 16.

Subsequently, as shown in FIG. 1E, a barrier layer 28 and a conductive layer 26 are sequentially formed on the insulating layer 22. The barrier layer 28 can block the through hole 18 filling metal to penetrate the thinned wafer 16, and the conductive layer 26 can be a metal seed layer for electroplating and an electrochemical method for filling holes. Deposition process. Moreover, as shown in FIG. 1F, the conductive material 30 is electrochemically filled in the through holes 18, wherein the conductive material 30 may be a metal material such as copper or an alloy of copper. Further, as shown in FIG. 1G, the two openings (20a and 20b) of the through holes 18 are formed with corresponding bumps 32 connected to the conductive material 30. Alternatively, as shown in FIG. 1H, the thinned wafer 16 is diced to form dies 34 that are independent of one another. Finally, a plurality of crystal grains 34 are stacked, wherein the corresponding bumps 32 of the upper and lower adjacent crystal grains 34 are abutted. The reflowing of the bumps 32 between the top and bottom bumps allows the bumps 32 to be joined to each other, so that the stacked crystal grains 34 are joined to each other to form a stacked structure. The material of the bump 32 may be lead-containing solder mainly including tin (Sn), lead (Pb), silver (Ag) or the like, or lead-free solder, such as pure tin bump, tin-silver (Sn-Ag), It is composed of a material such as tin-silver-bismuth (Sn-Ag-Bi), tin-silver-copper (Sn-Ag-Cu) or tin-silver-copper-bismuth (Sn-Ag-Cu-Bi).

2A to 2H are a series of schematic cross-sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. As shown in FIG. 2A, a method of fabricating a semiconductor device disclosed in a second embodiment of the present invention is first provided. A wafer 10. The wafer 10 includes an active surface 12 and a back surface 14 disposed opposite the active surface 12. The active surface 12 refers to the surface on which the wafer 10 carries integrated circuitry, while the back surface 14 can be substantially parallel to the active surface 12. Next, as shown in FIG. 2B, the back surface 14 of the wafer 10 is polished to a predetermined thickness to form a thinned wafer 16. The thinned wafer 16 may have a thickness between 10 microns and 200 microns, and preferably the predetermined thickness may be about 50 microns. Thereafter, as shown in FIG. 2C, a plurality of via holes 18 are formed on the thinned wafer 16. The through holes 18 extend through the thinned wafer 16 such that each of the through holes 18 has two openings (20a and 20b) on the active surface 12 and the back surface 14, respectively. The manner of forming a plurality of vias 18 on the thinned wafer 16 may be selected from the group consisting of reactive ion etching (RIE), deep reactive ion etching (DRIE), laser (LASER), and wet etching (Wet etching). one. Then, as shown in FIG. 2D, a conductive carrier 36 is disposed on the back side 14 of the thinned wafer 16. In another embodiment, the conductive carrier 36 is disposed on the active surface 12 of the thinned wafer 16. The conductive carrier 36 is used in an electrochemical deposition process for filling holes, and the material thereof may be selected from one of copper (Cu), titanium/tungsten (Ti/W), or an alloy thereof.

Subsequently, as shown in FIG. 2E, the conductive material 30 is electrochemically filled in the via holes 18, and after the via holes 18 are filled, the conductive carrier 36 is removed by an etchant. The conductive material 30 may be a metal material such as copper or an alloy of copper. Further, as shown in FIG. 2F, bumps 32 corresponding to the conductive material 30 are formed on the two openings (20a and 20b) of the through holes 18. Again, as shown in FIG. 2G, the thinned wafer 16 is diced to form separate dies 34. Finally, as shown in FIG. 2H, a plurality of crystal grains 34 are stacked, wherein The corresponding bumps 32 of the lower adjacent crystal grains 34 are abutted. The reflowing of the bumps 32 between the top and bottom bumps allows the bumps 32 to be joined to each other, so that the stacked crystal grains 34 are joined to each other to form a stacked structure.

3A to 3H are a series of schematic cross-sectional views showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention. As shown in FIG. 3A, a method of fabricating a semiconductor device according to a third embodiment of the present invention first provides a wafer 10. The wafer 10 includes an active surface 12 and a back surface 14 disposed opposite the active surface 12. The active surface 12 refers to the surface on which the wafer 10 carries integrated circuitry, while the back surface 14 can be substantially parallel to the active surface 12. Next, as shown in FIG. 3B, the back surface 14 of the wafer 10 is polished to a predetermined thickness to form a thinned wafer 16. The predetermined thickness may be between 10 microns and 200 microns, and preferably the predetermined thickness may be about 50 microns. Thereafter, as shown in FIG. 3C, a plurality of via holes 18 are formed on the thinned wafer 16. The through holes 18 extend through the thinned wafer 16 such that each of the through holes 18 has two openings (20a and 20b) on the active surface 12 and the back surface 14, respectively. The manner of forming a plurality of vias 18 on the thinned wafer 16 may be selected from the group consisting of reactive ion etching (RIE), deep reactive ion etching (DRIE), laser (LASER), and wet etching (Wet etching). one. Then, as shown in FIG. 3D, an insulating layer 22 is formed on the active surface 12 of the thinned wafer 16 and the inner walls 24 of the through holes 18. The insulating layer 22 provides electrical insulation and the function of the filler metal with the barrier vias 18 to penetrate the thinned wafer 16.

Subsequently, as shown in FIG. 3E, a barrier layer 28 and a conductive layer 26 are sequentially formed on the insulating layer 22. The barrier layer 28 can block the through hole 18 to fill the metal penetration To thin the wafer 16, the conductive layer 26 can be a metal seed layer for electroplating and used for the electrochemical deposition process when filling holes. Moreover, as shown in FIG. 3F, the conductive material 30 is electrochemically filled in the through holes 18, wherein the conductive material 30 may be a metal material such as copper or an alloy of copper. Then, as shown in FIG. 3G, the vias 18 are formed on the openings 20a of the active surface 12 of the thinned wafer 16 to form bumps 32 connected to the conductive material 30. In another embodiment, the bump 32 is formed in the opening 20b of the through hole 18 on the back surface 14. Finally, the conductive material 30 of each of the via holes 18 without the other opening 20b of the bump 32 is etched by a micro-etching process to form a concave shape as shown in FIG. 3H. After the micro-etching process is completed, the thinned wafers 16 are diced to form separate wafers 34 that are independent of each other and bondable to each other.

4A to 4I are a series of schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to a fourth embodiment of the present invention. As shown in FIG. 4A, a method of fabricating a semiconductor device according to a fourth embodiment of the present invention first provides a wafer 10. The wafer 10 includes an active surface 12 and a back surface 14 disposed opposite the active surface 12. The active surface 12 refers to the surface on which the wafer 10 carries integrated circuitry, while the back surface 14 can be substantially parallel to the active surface 12. Next, as shown in FIG. 4B, the back surface 14 of the wafer 10 is polished to a predetermined thickness to form a thinned wafer 16. The predetermined thickness may be between 10 microns and 200 microns, and preferably the predetermined thickness may be about 50 microns. Thereafter, as shown in FIG. 4C, a plurality of via holes 18 are formed on the thinned wafer 16. The through holes 18 extend through the thinned wafers 16 such that the through holes 18 are respectively located on the active surface 12 and the back surface 14 Two openings (20a and 20b). The manner of forming a plurality of vias 18 on the thinned wafer 16 may be selected from the group consisting of reactive ion etching (RIE), deep reactive ion etching (DRIE), laser (LASER), and wet etching (Wet etching). one. Then, as shown in FIG. 4D, an insulating layer 22 is formed on the active surface 12 of the thinned wafer 16 and the inner walls 24 of the through holes 18. The insulating layer 22 provides a function of electrically insulating and a function of the filler metal having the barrier via 18 penetrating into the thinned wafer 16.

Subsequently, as shown in FIG. 4E, a barrier layer 28 and a conductive layer 26 are sequentially formed on the insulating layer 22. The barrier layer 28 can block the through hole 18 filling metal to penetrate the thinned wafer 16, and the conductive layer 26 can be a metal seed layer for electroplating and used for electrochemical filling. Deposition process. Moreover, as shown in FIG. 4F, the conductive material 30 is electrochemically filled in the through holes 18, wherein the conductive material 30 may be a metal material such as copper or an alloy of copper. Then, as shown in FIG. 4G, each of the through holes 18 is located on the opening 20a of the active surface 12 to form a bump 32 connected to the conductive material 30, respectively. In another embodiment, the bump 32 is formed in the opening 20b of the through hole 18 on the back surface 14. In addition, as shown in FIG. 4H, the back surface 14 of the thinned wafer 16 not provided with the bumps 32 is etched by a micro-etching process to expose the conductive materials of the via holes 18 to form a pillar shape. Convex. Finally, as shown in FIG. 4I, after the micro-etching process is finished, the thinned wafers 16 are diced to form independent and mutually bondable to form a stacked structure of dies 34.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various changes based on the teachings and disclosures of the present invention. The substitutions and modifications may be made without departing from the spirit of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

10‧‧‧ wafer

12‧‧‧Active surface

14‧‧‧ Back

16‧‧‧Thin wafer

18‧‧‧through hole

20a, 20b‧‧‧ openings

22‧‧‧Insulation

24‧‧‧ inner wall

26‧‧‧ Conductive layer

28‧‧‧Shielding layer

30‧‧‧Electrical materials

32‧‧‧Bumps

34‧‧‧ grain

36‧‧‧ Conductive carrier

1A to 1I are a series of cross-sectional views illustrating a method of fabricating a semiconductor device according to a first embodiment of the present invention; and FIGS. 2A to 2H are a series of cross-sectional views illustrating a second embodiment of the present invention. FIG. 3A to FIG. 3H are a series of schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to a third embodiment of the present invention; and FIGS. 4A to 4I are a series of cross-sectional views illustrating an example of a semiconductor device; A method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

22‧‧‧Insulation

26‧‧‧ Conductive layer

28‧‧‧Shielding layer

30‧‧‧Electrical materials

32‧‧‧Bumps

34‧‧‧ grain

Claims (22)

A method of fabricating a semiconductor device, comprising the steps of: providing a wafer, wherein the wafer has an active surface and a back surface opposite to the active surface; grinding the back surface of the wafer to obtain a thinned wafer; Forming a plurality of vias on the thinned wafer, wherein each of the vias has two openings respectively on the back surface of the wafer and the active surface; forming an insulating layer on the active surface of the thinned wafer And the inner wall of the through holes; forming a conductive layer on the insulating layer; electrochemically filling the conductive material in the through holes; forming bumps on the at least one opening of the through holes; And cutting the thinned wafer to form separate grains. The method of fabricating a semiconductor device according to claim 1, wherein the plurality of via holes are formed on the thinned wafer in a manner selected from reactive ion etching (RIE), deep reactive ion etching (DRIE), and laser ( LASER) and one of the Wet etching methods. A method of manufacturing a semiconductor device according to claim 1, wherein the conductive material is electrochemically filled with copper or an alloy thereof in a step of electrochemically filling a conductive material in the through holes. The method of fabricating a semiconductor device according to claim 1, wherein the step of electrochemically filling the conductive material in the via holes comprises the step of micro-etching the surface of the conductive material for the via holes. The method of manufacturing a semiconductor device according to claim 1, wherein the step of electrochemically filling the conductive material in the through holes includes a wafer The back side is subjected to a step of micro-etching. The manufacturing method of the semiconductor device of claim 1, wherein the bumps are formed on the at least one opening of the via holes, the bumps being formed on the active surface of the thinned wafer The opening. The manufacturing method of the semiconductor device of claim 1, wherein the step of forming a bump on the at least one opening of the via holes is formed on the through hole on the back surface of the thinned wafer Opening. The method of manufacturing a semiconductor device according to claim 1, wherein the step of grinding the back surface of the wafer comprises the steps of: grinding the back surface of the wafer to a predetermined thickness to obtain the thinned wafer, wherein the predetermined thickness Between 10 microns and 200 microns. A method of fabricating a semiconductor device according to claim 8, wherein the predetermined thickness is about 50 μm. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a conductive layer comprises sequentially forming a barrier layer and a metal seed layer on the insulating layer. A method of fabricating a semiconductor device according to claim 1, further comprising the step of bonding a plurality of the die layers. A method of fabricating a semiconductor device, comprising the steps of: providing a wafer, wherein the wafer has an active surface and a back surface opposite to the active surface; grinding the back surface of the wafer to obtain a thinned wafer; Forming a plurality of vias on the thinned wafer, wherein each of the vias has two openings respectively on the back surface of the wafer and the active surface; and a conductive carrier is disposed on the back surface or the active surface; Electrochemically filling a conductive material in the via holes; removing the conductive carrier; forming bumps on the at least one opening of the via holes; and cutting the thinned wafer to form independent of each other The grain. The method of fabricating a semiconductor device according to claim 12, wherein the plurality of via holes are formed on the thinned wafer in a manner selected from reactive ion etching (RIE), deep reactive ion etching (DRIE), and laser ( LASER) and one of the Wet etching methods. A method of fabricating a semiconductor device according to claim 12, wherein the conductive material is electrochemically filled with copper or an alloy thereof in a step of electrochemically filling a conductive material in the through holes. The method of fabricating a semiconductor device according to claim 12, wherein the step of electrochemically filling the conductive material in the via holes comprises the step of micro-etching the surface of the conductive material for the via holes. The method of fabricating a semiconductor device according to claim 12, wherein the step of electrochemically filling the conductive material in the via holes comprises a step of micro-etching the back surface of the wafer. The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming bumps on the at least one opening of the via holes is formed on the active surface of the thinned wafer The opening. The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming a bump on the at least one opening of the via holes is formed in the via hole on the back surface of the thinned wafer Opening. A method of manufacturing a semiconductor device according to claim 12, wherein the step of grinding the back surface of the wafer comprises the steps of: The back side of the wafer is ground to a predetermined thickness to obtain the thinned wafer, wherein the predetermined thickness is between 10 microns and 200 microns. The method of fabricating a semiconductor device according to claim 19, wherein the predetermined thickness is preferably about 50 μm. The method of fabricating a semiconductor device according to claim 12, wherein the conductive carrier material is selected from one of copper (Cu), titanium/tungsten (Ti/W) or an alloy thereof. A method of fabricating a semiconductor device according to claim 12, further comprising the step of bonding a plurality of the die stacks.