TWI399799B - Method for manufacturing gate structure of semiconductor device and semiconductor device - Google Patents

Description

Method for manufacturing gate structure of semiconductor element and semiconductor element

The present invention relates to the field of semiconductor integrated circuit technology, and in particular to a method of fabricating a gate structure of a semiconductor device and a semiconductor device.

In recent years, efforts have been made, such as pseudomorphic HEMTs, indium phosphide-based lattice-matched heterostructure field effect transistors (HFETs), variability, high meta-migration transistors (metamorphic HEMTs), and thin A great deal of effort has been put into the design of high-speed components for various compound semiconductors such as InGaAsSb dilute-channel HEMTs and nitrogen-based high electron mobility transistors (nitride-based HEMTs). It is well known that the elemental properties of heterostructure field effect transistors and high electron mobility transistors can be substantially improved by reducing the gate length.

However, the conventional semiconductor device process can only provide a semiconductor high-speed device structure of a conventional gate, and it is particularly expensive to align a process device and a photo-etching technique to obtain a semiconductor high-speed device having a low line-width gate size; in particular, a conventional semiconductor Component process technology still requires additional process steps to form structures such as passivation layers or field plates, so further improvements in process cost and component characteristics are needed.

The present invention provides a method of fabricating a gate structure of a semiconductor device to effectively reduce process cost and obtain better component characteristics.

The present invention further provides a semiconductor component having a lower fabrication cost and better component characteristics.

A method of fabricating a gate structure for a semiconductor device according to an embodiment of the invention includes the steps of forming a passivation layer on a gate contact layer. Next, a first lithography process is performed to form a first patterned photoresist layer on the passivation layer, wherein the first patterned photoresist layer has a first window exposing a portion of the passivation layer. Thereafter, an etching process is performed to remove portions of the passivation layer exposed to the first window, thereby forming a gate window in the passivation layer. Then, the first patterned photoresist is removed. Then, performing a second lithography process by using an offset exposure alignment method to form a second patterned photoresist layer on the passivation layer, wherein a portion of the second patterned photoresist layer is filled in a portion of the gate window to cover a portion a gate contact layer, the second patterned photoresist layer has a second window partially overlapping the gate window, and the second window exposes a portion of the gate contact layer and a portion of the passivation layer and forms a meandering window with the gate window. Thereafter, a 闸-type gate structure is formed in the Γ-type window. Then, the second patterned photoresist layer is removed.

In an embodiment of the invention, the first lithography process and the second lithography process use the same reticle, and when the second lithography process is performed, the reticle offset distance is smaller than the line width of the reticle.

In an embodiment of the invention, the reticle offset distance is one-half of the line width of the reticle during the second lithography process.

In an embodiment of the invention, the Γ-type gate structure includes a gate electrode and a field plate. The gate electrode is located in the gate window and the second window and is in contact with the gate contact layer, and the field plate is located in the second window and extends from the side of the gate electrode to the passivation layer.

In an embodiment of the invention, the material of the gate contact layer comprises germanium, germanium dioxide, antimony telluride, phosphide semiconductor, germanide semiconductor or nitride semiconductor.

In an embodiment of the invention, the step of forming a passivation layer on the gate contact layer includes forming a tantalum nitride layer on the gate contact layer.

In an embodiment of the invention, the step of forming a passivation layer on the gate contact layer comprises chemical vapor deposition.

In an embodiment of the invention, the etching process is a wet etching process or a dry etching process.

A semiconductor device according to an embodiment of the invention includes a semiconductor layer structure, a passivation layer, and a germanium gate structure. The semiconductor layer structure includes a gate contact layer on the gate contact layer and having a gate window. The Γ-type gate structure comprises a gate electrode and a field plate, wherein a part of the gate electrode is located in the gate window and is in contact with the gate contact layer, and the field plate is one of a part of the gate electrode outside the gate window The side extends to the passivation layer.

In an embodiment of the invention, the length of the gate window in one direction is equal to the sum of the length of the gate electrode in the direction and the length of the field plate in the direction.

In an embodiment of the invention, the material of the passivation layer comprises tantalum nitride.

In an embodiment of the invention, the material of the gate contact layer comprises germanium, germanium dioxide, antimony telluride, phosphide semiconductor, germanide semiconductor or nitride semiconductor.

In an embodiment of the invention, the semiconductor device further includes a substrate, and the semiconductor layer structure is formed on the substrate. The material of the substrate may be tantalum, cerium oxide, antimony telluride, gallium arsenide, indium phosphide, tantalum carbide or aluminum oxide.

In an embodiment of the invention, the semiconductor layer structure further includes a channel layer between the gate contact layer and the substrate. The channel layer may be made of tantalum, niobium, gallium arsenide, indium gallium arsenide, indium phosphide or a nitride semiconductor.

In an embodiment of the invention, the semiconductor device further includes a source electrode and a drain electrode, all of which are in contact with the channel layer. The passivation layer is between the source electrode and the drain electrode, and the field plate is located on a side of the gate electrode adjacent to the source electrode or the drain electrode.

In an embodiment of the invention, the semiconductor layer structure further includes a buffer layer between the channel layer and the substrate. The buffer layer may be made of tantalum, niobium, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium gallium phosphide or a nitride semiconductor.

In an embodiment of the invention, the semiconductor layer structure further includes a nucleation layer between the buffer layer and the substrate.

Another embodiment of the present invention provides a semiconductor device including a substrate, a buffer layer, a barrier layer, a two-dimensional electron gas channel layer, a source electrode, a gate electrode, a passivation layer, and a gate structure. The buffer layer and the barrier layer are sequentially formed on the substrate, and the two-dimensional electron gas channel layer is located at the hetero interface of the buffer layer and the barrier layer. Both the source electrode and the drain electrode are in contact with the two-dimensional electron gas channel layer, and the passivation layer is on the barrier layer between the source electrode and the drain electrode and has a gate window. The gate structure is composed of a gate electrode and a field plate extending from the gate electrode to the source electrode side or the drain electrode side, and the gate electrode is in contact with the gate contact layer through the gate window, and the field plate is used by The passivation layer is spaced apart from the gate contact layer.

In an embodiment of the invention, the length of the gate window in one direction is equal to the sum of the length of the gate electrode in this direction and the length of the field plate in this direction.

In an embodiment of the invention, the semiconductor device further includes a nucleation layer between the substrate and the buffer layer.

In the method for fabricating the gate structure of the semiconductor device of the present invention, the offset exposure alignment method can achieve the effect of effectively reducing the gate size at a lower process cost by using a mask having a larger line width. Further, in the gate structure of the semiconductor device of the present invention and the method of fabricating the same, since the passivation layer and the field plate between the gate electrode and the gate electrode are formed, leakage current and amplification breakdown voltage can be greatly reduced, and further Enhance multiple characteristics such as high frequency cutoff frequency and output power gain.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A to 1G are flowcharts showing a method of fabricating a gate structure of a semiconductor device according to an embodiment of the present invention. The same element symbols in the drawings represent the same elements or layers. The method of fabricating the gate structure of the semiconductor device of the present embodiment includes the following steps: First, as shown in FIG. 1A, a passivation layer 30 is formed on the gate contact layer 21. The material of the gate contact layer 21 may be selected from ruthenium, ruthenium dioxide, ruthenium osmium, phosphide semiconductor, germanide semiconductor or nitride semiconductor. In this embodiment, aluminum gallium nitride (Al _0.27 Ga _0.73 N) is taken as an example. In addition, the material of the passivation layer 30 is, for example, tantalum nitride, but is not limited thereto. The passivation layer 30 of this embodiment may be formed on the gate contact layer 21 by a plasma enhanced chemical vapor deposition (PECVD) process, but is not limited thereto. The thickness of the passivation layer 30 is, for example, 30 nm. After the passivation layer 30 is deposited, the formed passivation layer 30 may not be subjected to an annealing treatment.

Next, as shown in FIG. 1B, a lithography process is performed to form a first patterned photoresist layer 40 on the passivation layer 30, wherein the first patterned photoresist layer 40 has a first window 41 exposing a portion of the passivation layer 30. In this embodiment, a specific step of forming the first patterned photoresist layer 40 by using a lithography process is, for example, forming a photoresist material layer on the passivation layer 30, wherein the photoresist layer is formed by spin coating (spin). -coating). Next, the photoresist material layer is exposed and developed by using a photomask having a specific line width (for example, 1.2 μm) and an aligner to form a first window 41 in the photoresist material layer, thereby forming the first patterned light. Resistive layer 40. The aligner described above is, for example, provided with an ultraviolet light source having a wavelength of 365 nm. Further, the length W1 of the first window 41 in one direction (e.g., horizontal direction) is substantially equal to the line width of the photomask (e.g., 1.2 μm). The material of the photoresist material layer may be a positive photoresist material or a negative photoresist material.

Then, as shown in FIG. 1C, an etching process is performed to remove portions of the passivation layer 30 exposed to the first window 41, thereby forming a passivation layer 31 having a gate window 32, wherein the gate window 32 exposes a portion of the gate contact Layer 21. The length of the gate window 32 in the horizontal direction is substantially equal to the line width of the aforementioned mask. Here, the first patterned photoresist layer 40 is used as an etch mask, and the etching process may be performed by a wet etching process, and the chemical etching solution used includes hydrofluoric acid and water in a mixing ratio of 1:1, but not This is limited. In addition, the etching process herein may also be a dry etching process.

Thereafter, as shown in FIG. 1D, the first patterned photoresist layer 40 is removed to completely expose the passivation layer 31 having the gate window 32. Here, the first patterned photoresist layer 40 can be removed by an ashing process, but is not limited thereto.

Next, as shown in FIG. 1E, another lithography process is performed in an offset exposure alignment manner to form a second patterned photoresist layer 50 on the passivation layer 31, wherein a portion of the second patterned photoresist layer 50 is filled in. A portion of the gate window 32 covers a portion of the gate contact layer 21. The second patterned photoresist layer 50 has a second window 51 partially overlapping the gate window 32, and the second window 51 exposes a portion of the gate contact layer 21 and a portion of the passivation layer 31, and is formed together with the gate window 32. Type window. In this embodiment, the specific step of forming the second patterned photoresist layer 50 by the lithography process in the offset exposure alignment manner is, for example, forming a photoresist material layer on the passivation layer 31, and the photoresist layer is filled. The method of forming the photoresist layer 32 into the gate window 32 is, for example, spin coating. Then, the photoresist layer and the aligner used in the first lithography process are exposed and developed in an offset exposure alignment manner to form a second window 51 in the photoresist material layer, and the removal is located A layer of photoresist material within the gate window 32 further forms a second patterned photoresist layer 50. The above-mentioned offset exposure alignment means that the position of the reticle is offset in the second lithography process compared to the first lithography process. The distance at which the mask is offset is set to be smaller than the line width of the mask. In the present embodiment, the distance at which the reticle is offset is, for example, one-half of the line width of the reticle. Further, the length W2 of the second window 51 in the horizontal direction is also equal to the line width of the reticle. The material of the photoresist material layer may be a positive photoresist material or a negative photoresist material. It should be noted that the degree of overlap between the gate window 32 and the second window 51 determines the length of the subsequently formed gate electrode in the horizontal direction and the length of the field plate in the horizontal direction. In other words, the embodiment of the present invention can adjust the distance of the reticle offset according to different designs, so that the gate length and the field plate length can meet the requirements. In addition, in the embodiment, the two lithography processes use the same reticle, but in another embodiment, the lithography process may also use different reticle.

Next, as shown in FIG. 1F, a 闸-type gate structure 60 is formed in the Γ-type window. Specifically, in the present embodiment, for example, a nickel/gold stacked layer structure is formed by vapor deposition to obtain a germanium gate structure 60, wherein the thickness of the nickel layer is, for example, 100 nm, and the thickness of the gold layer is, for example, 50 nm. Here, the second patterned photoresist layer 50 serves as a vapor deposition mask. The 闸-type gate structure 60 includes an integrally formed gate electrode 61 and a field plate 63. The gate electrode 61 is located in the gate window 32 and the second window 51 and is in contact with the gate contact layer 21 (for example, forming a Schottky In contact, the field plate 63 is located in the second window 51 and extends from the side of the gate electrode 61 to the passivation layer 31.

Thereafter, as shown in FIG. 1G, the second patterned photoresist layer 50 is removed to produce the desired germanium gate structure 60. The second patterned photoresist layer 50 can be removed by a lift-off process.

Since the method of manufacturing the gate structure of the semiconductor device of the present embodiment employs the method of offset exposure, the length of the gate electrode 61 can be made shorter than the line width of the mask, and the field plate 63 can be simultaneously fabricated. .

2 is a schematic structural view of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 2, the semiconductor device 100 of the present embodiment has a Γ-type gate structure 60 manufactured by the method for fabricating the gate structure of the above-described semiconductor device. The semiconductor device 100 includes a substrate 10, a semiconductor layer structure 20, a source electrode S, a drain electrode D, a passivation layer 31, and a germanium gate structure 60. The semiconductor layer structure 20 is generally a plurality of semiconductor layer stack structures formed on the substrate 10. In the present embodiment, the semiconductor layer structure 20 includes the gate contact layer 21, the channel layer 23, the buffer layer 25, and the crystal core layer 27 in order from the top to the bottom, but is not limited thereto.

The material of the substrate 10 may be selected from ruthenium, ruthenium dioxide, ruthenium osmium, gallium arsenide, indium phosphide, tantalum carbide or aluminum oxide. The channel layer 23 is located between the gate contact layer 21 and the substrate 10, and may be made of tantalum, niobium, gallium arsenide, indium gallium arsenide, indium phosphide or a nitride semiconductor. In the present embodiment, the channel layer 23 is, for example, a two-dimensional electron gas channel layer formed at a hetero interface between the gate contact layer 21 and the buffer layer 25. The buffer layer 25 is located between the channel layer 23 and the substrate 10. The material of the buffer layer 25 may be tantalum, tantalum, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium gallium phosphide or nitride semiconductor. Take gallium nitride (GaN) as an example. A nucleation layer 27 is located between the buffer layer 25 and the substrate 10 to facilitate the formation of a buffer layer 23 having a low lattice mismatch. Herein, the combination of the specific materials of the gate contact layer 21, the channel layer 23, the buffer layer 25 and the nucleation layer 27 in the substrate 10 and the semiconductor layer structure 20 can be determined by those skilled in the art, and therefore will not be exemplified. .

In the above, the source electrode S and the drain electrode D are both in contact with the channel layer 23 in the semiconductor layer structure 20. Specifically, both the source electrode S and the drain electrode D may be a titanium/aluminum/gold stacked layer structure and form an ohmic contact with the channel layer 23. The passivation layer 31 is located on the gate contact layer 21 between the source electrode S and the drain electrode D, and has a gate window 32 of length L in the horizontal direction, the length L being substantially equal to the line width of the mask (eg 1.2 μm). The material of the passivation layer 31 may be tantalum nitride, but not limited thereto, and the thickness of the passivation layer 31 is, for example, 30 nm or other suitable thickness. Here, by adjusting the thickness of the passivation layer 31, characteristics such as current gain, breakdown voltage, high frequency cutoff frequency, and output power can be obtained. The 闸-type gate structure 60 includes an integrally formed gate electrode 61 and a field plate 63. A portion of the gate electrode 61 (i.e., the lower portion of the gate electrode of FIG. 2) is located within the gate window 32 and forms a Schottky contact with the gate contact layer 21. The field plate 63 extends from one side of a portion of the gate electrode (i.e., the upper portion of the gate electrode in FIG. 2) 61 outside the gate window 63 to the passivation layer 31. Although the field plate 63 of the present embodiment is located on the side of the gate electrode 61 adjacent to the gate electrode D, the field plate 63 may be located on different sides of the gate electrode 61 depending on various requirements, such as at the gate electrode 61. It is adjacent to one side of the source electrode S. When the second lithography process is performed, the position of the field plate 63 can be determined by controlling the position after the reticle is shifted.

Further, it can be seen from Figure 2, the length of the gate 32 in the horizontal direction of the window L is equal to the sum of the gate electrode 61 in the horizontal direction, the length L _G of the field plate 63 in the horizontal direction of the L _F.

3 is a graph showing a comparison of current-voltage (IV) characteristics of a semiconductor element having a Γ-type gate structure and a conventional semiconductor element having a conventional gate structure in accordance with an embodiment of the present invention. Both of the semiconductor elements used the same mask (line width of 1.2 μm) and lithography process conditions. The gate length L _g of the 闸-type gate structure is 0.6 μm and the field plate length L _f is 0.6 μm. The gate length of the conventional gate structure is 1.2 μm and there is no field plate. V _{GS in} Fig. 3 is the gate-source voltage, and the V _GS difference (step) corresponding to each characteristic curve is -1 volt (V).

It can be clearly seen from the IV characteristic comparison chart that the semiconductor device having the Γ-type gate structure can greatly improve the characteristics of the drain-source current density and the conversion mutual conductance, and at the same time, the surface charge trapping effect is effectively suppressed by the tantalum nitride passivation technique. Reduce the gate leakage current. A conventional semiconductor device having a conventional gate structure has a drain-source saturation current density value of about 286.3 mA/mm (mA/mm), and a semiconductor device having a Γ-type gate structure has a drain-source saturation. The current density value is approximately 363.4 mA/mm. Therefore, compared with the prior art, the semiconductor element having the Γ-type gate structure of the embodiment of the present invention has a gate-source saturation current density value which is greatly improved by 27%.

4 is a view showing a comparison of high frequency characteristics of a semiconductor element having a Γ-type gate structure and a conventional semiconductor element having a conventional gate structure in accordance with an embodiment of the present invention. In Figure 4, MSG is the maximum stable gain, MAG is the maximum available gain, V _GS is the gate-source voltage, and V _DS is the drain-source voltage. In theory, the unit current gain cutoff frequency and the maximum oscillation frequency are proportional to the maximum conversion mutual conductance characteristic of the element, and the Γ-type gate structure of the embodiment of the invention can effectively shorten the gate electrode length and improve the maximum conversion mutual conduction characteristic. Compared with the semiconductor current component having the conventional gate structure, the unit current gain cutoff frequency and the maximum oscillation frequency are 10.1 gigahertz (GHz) and 12 GHz, respectively, and the semiconductor having the germanium gate structure proposed by the embodiment of the present invention The unit current gain cutoff frequency and the maximum oscillation frequency of the component are 13.1 GHz and 16.2 GHz, respectively. In other words, compared with the prior art, the unit current gain cutoff frequency and the maximum oscillation frequency measurement value of the embodiment of the present invention increase by 29.7% and 35%, respectively.

5 is a graph showing comparison of output power characteristics of a semiconductor element having a Γ-type gate structure and a conventional semiconductor element having a conventional gate structure in accordance with an embodiment of the present invention. Since the field plate of the Γ-type gate structure can effectively disperse the electric field and improve the breakdown voltage, and the gate electrode length is shortened, the current/voltage gain can be improved, and the leakage current can be reduced by the tantalum nitride passivation technology, which is expected to be greatly improved. Output power and power gain (or power added efficiency PAE) and other characteristics. When the two semiconductor elements operate at 2.4 GHz, V _DS = 6 V, V _GS = -3.5 V, the output power (Pout) measured by a semiconductor device having a conventional gate structure is 16.9 mW (dBm), PAE It is 23.7%, and the semiconductor element having the Γ-type gate structure proposed by the embodiment of the present invention has Pout=18.4 dBm and PAE=29.5%. In other words, compared with the prior art, the output power of the semiconductor device having the germanium gate structure of the embodiment of the present invention is increased by 6.4%, and the PAE is greatly increased by 24.5%.

In summary, in the method for fabricating the gate structure of the semiconductor device of the present invention, the offset exposure alignment method can effectively reduce the gate electrode at a lower process cost by using a mask having a larger line width. The effect of size. Further, in the gate structure of the semiconductor device of the present invention and the method of fabricating the same, since the passivation layer and the field plate between the gate electrode and the gate electrode are formed, leakage current, amplification and breakdown voltage can be greatly reduced, and the voltage is further increased. Multiple characteristics such as high frequency cutoff frequency and output power gain. The semiconductor component of the present invention can be directly applied to semiconductor integrated circuit industry technologies such as wireless communication and microwave power.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended to be a part of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

10. . . Base

20. . . Semiconductor layer structure

twenty three. . . Channel layer

25. . . The buffer layer

27. . . Nucleation layer

twenty one. . . Gate contact layer

30, 31. . . Passivation layer

40. . . First patterned photoresist layer

41. . . First window

W1. . . Length of the first window

W2. . . Length of the second window

32. . . Gate window

50. . . Second patterned photoresist layer

51. . . Second window

60. . . Γ-type gate structure

61. . . Gate electrode

63. . . Field plate

100. . . Semiconductor component

D. . . Bipolar electrode

S. . . Source electrode

L. . . Length of gate window

Lg. . . Gate electrode length

Lf. . . Field plate length

1A to 1G are flowcharts showing a method of fabricating a gate structure of a semiconductor device according to an embodiment of the present invention.

2 is a schematic structural view of a semiconductor device according to an embodiment of the present invention.

3 is a graph showing a comparison of current-voltage characteristics of a semiconductor element having a Γ-type gate structure and a conventional semiconductor element having a conventional gate structure in accordance with an embodiment of the present invention.

4 is a view showing a comparison of high frequency characteristics of a semiconductor element having a Γ-type gate structure and a conventional semiconductor element having a conventional gate structure in accordance with an embodiment of the present invention.

5 is a graph showing comparison of output power characteristics of a semiconductor element having a Γ-type gate structure and a conventional semiconductor element having a conventional gate structure in accordance with an embodiment of the present invention.

twenty one. . . Gate contact layer

31. . . Passivation layer

32. . . Gate window

60. . . Γ-type gate structure

Claims (22)

A method for fabricating a gate structure of a semiconductor device, comprising: forming a passivation layer on a gate contact layer; performing a first lithography process to form a first patterned photoresist layer on the passivation layer, wherein The first patterned photoresist layer has a first window exposing a portion of the passivation layer; an etching process is performed to remove a portion of the passivation layer exposed to the first window, thereby forming a gate in the passivation layer a first patterned photoresist layer; a second lithography process is performed by offset exposure alignment to form a second patterned photoresist layer on the passivation layer, wherein the second portion The patterned photoresist layer is filled in a portion of the gate window to cover a portion of the gate contact layer, the second patterned photoresist layer has a second window partially overlapping the gate window, and the second window Exposing a portion of the gate contact layer and a portion of the passivation layer and forming a germanium window with the gate window; forming a germanium gate structure in the germanium window; and removing the second patterned photoresist layer . The method for manufacturing a gate structure of a semiconductor device according to claim 1, wherein the first lithography process and the second lithography process use the same photomask, and when the second lithography process is performed The reticle is offset by a distance less than a line width of the reticle. The method of fabricating a gate structure for a semiconductor device according to claim 2, wherein, when the second lithography process is performed, the reticle is offset by a distance of one half of a line width of the reticle. The method of fabricating a gate structure for a semiconductor device according to claim 1, wherein the gate-type gate structure comprises a gate electrode and a field plate, the gate electrode being located at the gate window and the second The window is in contact with the gate contact layer, and the field plate is located in the second window and extends from the gate electrode side to the passivation layer. The method for fabricating a gate structure of a semiconductor device according to claim 1, wherein the material of the gate contact layer comprises germanium, germanium dioxide, antimony telluride, phosphide semiconductor, germanide semiconductor or nitride semiconductor . The method of fabricating a gate structure for a semiconductor device according to claim 1, wherein the step of forming the passivation layer on the gate contact layer comprises forming a tantalum nitride layer on the gate contact layer. The method of fabricating a gate structure for a semiconductor device according to claim 1, wherein the step of forming the passivation layer on the gate contact layer comprises chemical vapor deposition. The method of fabricating a gate structure for a semiconductor device according to claim 1, wherein the etching process is a wet etching process. The method of fabricating a gate structure for a semiconductor device according to claim 1, wherein the etching process is a dry etching process. A semiconductor device manufactured by the manufacturing method of any one of claims 1 to 9, the semiconductor device comprising: a semiconductor layer structure having a gate contact layer; and a passivation layer at the gate contact layer And having a gate window; and a gate structure comprising a gate electrode and a field plate, wherein the gate electrode is located in the gate window and is in contact with the gate contact layer, the field pole The plate extends from a side of the gate electrode outside the gate window to the passivation layer, wherein a length of the gate window in one direction is equal to a length of the gate electrode along the direction and the field plate The sum of the lengths along this direction. The semiconductor component of claim 10, wherein the blunt The material of the layer includes tantalum nitride. The semiconductor device according to claim 10, wherein the material of the gate contact layer comprises germanium, germanium dioxide, germanium telluride, a phosphide semiconductor, a germanide semiconductor or a nitride semiconductor. The semiconductor device of claim 10, further comprising a substrate on which the semiconductor layer structure is formed. The semiconductor device according to claim 13, wherein the material of the substrate comprises ruthenium, ruthenium dioxide, bismuth telluride, gallium arsenide, indium phosphide, tantalum carbide or aluminum oxide. The semiconductor device of claim 13, wherein the semiconductor layer structure further comprises a channel layer between the gate contact layer and the substrate. The semiconductor device according to claim 15, wherein the material of the channel layer comprises germanium, antimony telluride, gallium arsenide, indium gallium arsenide, indium phosphide or nitride semiconductor. The semiconductor device of claim 15, further comprising a source electrode and a drain electrode, all of which are in contact with the channel layer, the passivation layer being located between the source electrode and the drain electrode, The field plate is located on a side of the gate electrode adjacent to the source electrode or the drain electrode. The semiconductor device of claim 15, wherein the semiconductor layer structure further comprises a buffer layer between the channel layer and the substrate. The semiconductor device according to claim 18, wherein the material of the buffer layer comprises germanium, antimony telluride, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium gallium phosphide or a nitride semiconductor. The semiconductor device of claim 18, wherein the semiconductor layer structure further comprises a nucleation layer between the buffer layer and the substrate. A semiconductor device manufactured by the manufacturing method of any one of claims 1 to 9, the semiconductor device comprising: a substrate; a buffer layer; formed on the substrate; and a barrier layer formed on the buffer layer a two-dimensional electron gas channel layer located at the hetero interface of the buffer layer and the barrier layer; a source electrode and a drain electrode are in contact with the two-dimensional electron gas channel layer; a passivation layer is located a barrier window is formed on the barrier layer between the source electrode and the drain electrode; and a gate structure is formed by a gate electrode and a gate electrode to the source electrode side or the gate Forming a field plate extending from the electrode side, the gate electrode is in contact with the gate contact layer through the gate window, and the field plate is spaced apart from the gate contact layer by the passivation layer, wherein the gate window The length in one direction is equal to the sum of the length of the gate electrode in the direction and the length of the field plate in the direction. The semiconductor device of claim 21, further comprising a nucleation layer between the substrate and the buffer layer.