TWI396071B - Standby circuit and method for a display device - Google Patents

Description

Standby circuit and method of display device

The present invention relates to power management, and more particularly to a low power standby circuit and method for a computer liquid crystal display.

The Digital Visual Interface (DVI) is a video interface standard developed by the Digital Display Working Group (DDWG) to enhance the video performance of digital display devices such as computer LCDs. According to this DVI standard, the brightness of a pixel is transmitted to the display as an uncompressed binary data stream.

High-Definition Multimedia Interface (HDMI) is another newer video interface standard that is also transmitted to display devices (such as computer LCDs) in uncompressed binary data streams. Digital TV). Since the DVI signal is electrically compatible with the HDMI signal, HDMI can be backward compatible to DVI.

In recent years, the rapid growth of portable or battery-powered electronic devices has made the growth of device operation time an urgent need. However, as the growth of battery life is slow, reducing power consumption is an alternative to achieving this demand. For next generation or specific energy efficiency specifications, the maximum power consumption of the display control integrated circuit may have to be as small as 0.5 watts (W) when the liquid crystal display is in standby. According to such specifications, the display controller within the display device can only dispense up to 20 milliamps (mA) of current. Usually, a large part, or even half, of this 20 mAh may be wasted.

In view of the fact that conventional display controllers cannot effectively save power to comply with modern energy-saving regulations, there is a need to propose a low-power standby mechanism to substantially save power consumption.

In view of the above, one of the objects of the present invention is to provide a low power standby circuit and method thereof that enable power consumption to be saved when the display controller and display device are in the standby mode.

According to an embodiment of the invention, a detector is used to detect the voltage drop of the first terminating resistor of the positive path of the pulse channel and the voltage drop of the second terminating resistor of the negative path. When a voltage drop is detected, the switch controller controls the positive switch of the positive path and the negative switch of the negative path according to the output of the detector to open or close the positive or negative switch that detects the voltage drop (open) ), thereby saving power consumption in the display device standby mode.

The first figure shows the architecture of the Digital Visual Interface (DVI). Although illustrated herein by the DVI standard, other (previous or future) video standards are also applicable to the present invention. The DVI architecture shown in the first figure includes a transmitter (Tx) 10 for transmitting pixel data/control signals received from a graphics controller 12 via a link 16 to a receiver. Receiver (Rx) 14. In the drawings, link 16 includes, but is not limited to, six data/control channels (channel 0 to channel 5) and one clock channel. Next, the receiver 14 sends the received pixel data/control signal to a display controller (eg, liquid crystal control integrated circuit) 18 of a display device (eg, a computer liquid crystal display). In the present invention, the display device is disposed within, but not limited to, a portable or battery powered limited power electronics. According to the DVI standard, pixel data is transmitted in a transition minimized differential signaling (TMDS) format, which converts 8-bit data into a 10-bit TMDS signal. Each channel is implemented as a twist pair to carry data, control signals, or pulse signals.

The second figure shows a detailed functional block diagram of the receiver (Rx) 14 of the first figure. In the figure, three data channels CH0, CH1, CH2 (ie, RX0+/RX0-, RX1+/RX1-, RX2+/RX2-) and one pulse channel (RXC+/RXC-) are shown. The resistance value of the voltage-controlled resistor (VCR) 141 (for example, 50 ohms (Ω)) can be maintained at a fixed value via control. A phase locked loop (PLL) 142 generates a lock pulse signal based on the received pulse wave signal. Block 144 uses this lock pulse signal to recover the data for each channel so that the phase of each data signal can be locked. Next, block 146 synchronizes the data stream for each block 144 based on the synchronization signal (SYNC) of the blanking period. Finally, the data stream is decoded by decoder 148 for converting the 10-bit TMDS signal back to the 8-bit data for display on the display device. In some embodiments of the invention, the above blocks may be turned off in a standby mode to save power consumption.

Figure 3A shows the TMDS differential pair at the receiver (Rx) 14 end, especially the pulse pair. The transmitter (Tx) 10 transmits a differential signal to the receiver (Rx) 14 via a receptacle 30. The socket 30 and the receiver (Rx) 14 are usually disposed on the same printed circuit board 32. The reference voltage (or supply voltage) AVcc is used to set the high voltage of the differential voltage. A termination resistor R _{T at the} receiver (Rx) 14 end (e.g., a voltage controlled resistor (VCR) 141 of the second figure) is used to match the impedance of the twist pair of the link 16. The differential signal is input to a differential amplifier 34, which is typically used as a pulse wave detection amplifier (or operational amplifier (OP)). When the transmitter (Tx) 10 is in the active mode, it transmits the pulse signal through the pulse channel (RXC+ and RXC-) at the receiver (Rx) terminal 14, so that the positive input terminal (In+) of the differential amplifier 34 or The negative input (In-) has a periodic voltage change that varies between a high voltage (eg, 3.3 volts (V)) and a low voltage (eg, 0 volts).

The third B diagram illustrates the receiver (Rx) 14 pulse wave pair when the display device is in the standby mode. As shown, when in standby mode, the positive input (In+) voltage is 3.3 volts, so no current flows through path 160; the negative input (In-) voltage is 2.8 volts, so 10 mA current is passed Another path 162 flows to the transmitter (Tx) 10. That is, RXC+ = 0 mA, RXC - = 10 mA. It can be seen from this that the display device consumes power even when it is in the standby mode and does not receive any pulse wave. For the next generation or specific energy efficiency specifications, the maximum power consumption of the LCD display may be as small as 0.5 watts when it is in standby. According to such specifications, display controller 18 (first map) can only dispense up to 20 milliamps of current. According to the third B picture, half of this 20 mA out of the receiver (Rx) 14 is wasted.

The third C diagram illustrates another receiver (Rx) 14 pulse pair when the display device is in the standby mode. As shown, when in standby mode, the positive input (In+) voltage is 2.8 volts, so 10 mA current flows through path 160 to transmitter (Tx) 10; negative input (In-) The voltage is 3.3 volts, so no current flows through path 162. That is, RXC+=10 mA, RXC-=0 mA. Compared to the third B-picture, the 10 mA current of the third C-picture passes through the path 160 instead of the path 162 of the third B-picture. Whether it is the third B picture or the third C picture, current flows out of the receiver (Rx) 14 and is wasted.

The third D diagram illustrates yet another receiver (Rx) 14 pulse pair when the display device is in the standby mode. As shown, when in standby mode, the voltage at the positive input (In+) is 3.3 volts, so no current flows through path 160; the voltage at the negative input (In-) is also 3.3 volts, so there is no current through path 162. . That is, RXC+=0 mA, RXC-=0 mA. Compared with the third B diagram and the third C diagram, neither the path 160 nor the path 162 of the third D diagram passes current.

The three cases of the standby mode shown in the above third B to third D are summarized in Table 1 below.

The fourth figure shows the low power standby circuit of the embodiment of the present invention, and the fifth figure shows the flow chart of the low power standby method of the embodiment of the present invention. As described above, when the transmitter (Tx) 10 is in the active mode, it transmits the pulse wave signal through the pulse channel (RXC+ and RXC-) at the receiver (Rx) terminal 14, and thus the differential amplifier 34 The positive input (In+) or negative input (In-) has a periodic voltage change that varies between a high voltage (eg, 3.3 volts) and a low voltage (eg, 0 volts). The periodic variation of the pulse signal can be detected by a detector (such as the illustrated voltage comparator 40) based on the voltage at the positive input (In+) and the negative input (In-) (step 50). In another embodiment, voltage comparator 40 is detected based on the voltages of terminals A and B. The output 401 of the detector 40 controls a multiplexer (MUX) 42 such that the positive input (In+) voltage or the negative input (In-) voltage is passed to the pulse-detection amplifier (or operational amplifier (OP)). 44 (for example, the differential amplifier 34 in the third A diagram). The output of the pulse wave sense amplifier 44 can be fed back to a wake up generator 45. When the pulse wave signal is detected, the wake-up generator 45 outputs a wake-up signal.

When the transmitter (Tx) 10 is in the inactive mode, it no longer transmits the pulse signal through the pulse channel (RXC+ and RXC-) at the receiver (Rx) 14 end, so the detector 40 is positive. The input (In+) or negative input (In-) detects no periodic voltage change, indicating that it is in standby mode. The three scenarios of standby mode are discussed below.

Situation (1)

When the detector 40 detects that the positive input (In+) voltage is 3.3 volts and the negative input (In-) voltage is 2.8 volts, the output 402 of the detector 40 controls a switch controller 46 to close (close) The first switch SW_In+ and the second switch SW_In- is turned on (step 51). The outputs 401 and 402 of the aforementioned detector 40 may be the same or different signals. In the present embodiment, the switch controller 46 can be implemented using a multiplexer. Thereby, the current of 10 mA originally flowing through the path 162 can be avoided, thereby substantially saving power consumption. Therefore, the detector 40 can detect the active/inactive state of the transmitter (Tx) 10 through the path 160, and the signal of the positive input terminal (In+) can be fed to the pulse wave detecting amplifier 44 via the multiplexer 42. .

Situation (2)

When the detector 40 detects that the positive input (In+) voltage is 2.8 volts and the negative input (In-) voltage is 3.3 volts, the output 402 of the detector 40 controls the switch controller 46 to open (open) The first switch SW_In+ and closes the second switch SW_In- (step 52). Thereby, the current of 10 mA originally flowing through the path 160 can be avoided, thereby substantially saving power consumption. Therefore, the detector 40 can detect the active/inactive state of the transmitter (Tx) 10 through the path 162, and the signal of the negative input terminal (In-) can be fed to the pulse wave detecting amplifier via the multiplexer 42. 44.

Situation (3)

When the detector 40 detects that both the positive input (In+) and the negative input (In-) voltages are 3.3 volts, the output 402 of the detector 40 controls the switch controller 46 to open the first One of the switch SW_In+, the second switch SW_In-, and another switch is closed (step 53). Therefore, the detector 40 can detect the active/inactive state of the transmitter (Tx) 10 by one of the paths 160/162, and the signal of the positive input (In+) or the negative input (In-) can be The multiplexer 42 is fed to the pulse wave detecting amplifier 44.

The first switch SW_In+ or the second switch SW_In- will remain in an open state until a positive voltage change is detected at the positive input (In+) or negative input (In-), indicating that the transmitter (Tx) 10 enters Active state. At this time, the detector 40 will close the first switch SW_In+ and the second switch SW_In- (step 54), and the wake-up generator 45 will generate a wake-up signal to activate the receiver (Rx) 14 (step 55). ).

According to an embodiment of the invention, in the standby mode, one of the pulse paths of the twisted pair is disconnected, thereby substantially saving power consumption; while the other path continues to detect the presence of the pulse signal. When the pulse signal is detected, the interrupt path is restored.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

10. . . Transmitter (Tx)

12. . . Graphics controller

14. . . Receiver (Rx)

141. . . Voltage controlled resistor (VCR)

142. . . Phase-locked loop (PLL)

144. . . Data reply

146. . . Channel synchronization (SYNC)

148. . . decoder

16. . . link

18. . . Display controller

30. . . socket

32. . . A printed circuit board

34. . . Differential amplifier

40. . . Detector (voltage comparator)

42. . . Multiplexer

44. . . Pulse wave detection amplifier

45. . . Wake generator

46. . . Switch controller

50-55. . . Low power standby method

160. . . Path to the positive input

162. . . Path to the negative input

401, 402. . . Detector output

RX0+/RX0-, RX1+/RX1-, RX2+/RX2-. . . Data channel

RXC+/RXC-. . . Pulse channel

SYNC0, SYNC1, SYNC2. . . Synchronization signal

AVcc. . . Reference voltage

R _T . . . Terminating resistor

In+/In-. . . Positive/negative input of the differential amplifier

SW_In+. . . First switch

SW_In-. . . Second switch

A, B. . . End point

The first figure shows the architecture of the Digital Video Interface (DVI).

The second figure shows a detailed functional block diagram of the receiver (Rx) of the first figure.

Figure 3A shows the TMDS differential pair at the receiver (Rx) side.

The third B diagram illustrates the receiver (Rx) pulse wave pair (RXC + = 0 mA, RXC - = 10 mA) when the display device is in the standby mode.

The third C diagram illustrates another receiver (Rx) pulse wave pair (RXC+=10 mA, RXC-=0 mA) when the display device is in the standby mode.

The third D diagram illustrates yet another receiver (Rx) pulse pair (RXC + = 0 mA, RXC - 0 mA) when the display device is in the standby mode.

The fourth figure shows a low power standby circuit in accordance with an embodiment of the present invention.

The fifth diagram shows a flow chart of the low power standby method of the embodiment of the present invention.

40. . . Detector (voltage comparator)

42. . . Multiplexer

44. . . Pulse wave detection amplifier

45. . . Wake generator

46. . . Switch controller

160. . . Path to the positive input

162. . . Path to the negative input

401, 402. . . Detector output

RXC+/RXC-. . . Pulse channel

AVcc. . . Reference voltage

R _T . . . Terminating resistor

In+/In-. . . Positive/negative input of the differential amplifier

SW_In+. . . First switch

SW_In-. . . Second switch

A, B. . . End point

Claims (15)

A standby circuit for a display device, comprising: a positive switch connected between a first terminal resistor and a positive path of the pulse channel; and a negative switch connected between the second terminal resistor and a negative path of the pulse channel; a detector for detecting whether the pulse channel has a periodic change to determine whether the display device enters a standby state, and detecting a voltage drop of the first and second terminal resistors to output an output signal And a switch controller that controls the positive switch and the negative switch according to the output signal; wherein when the detector determines that the display device enters a standby state, the detector outputs the output signal to control the switch control The positive or negative switch that detects the voltage drop is opened, and one of the positive or negative switches is turned off when neither of the first and second terminating resistors generates a voltage drop. The standby circuit of the display device according to claim 1, further comprising a multiplexer that passes the signal of one of the positive path and the negative path according to the output of the detector. The standby circuit of the display device according to claim 2, further comprising a pulse wave detecting amplifier that receives the output of the multiplexer. The standby circuit of the display device according to claim 3, further comprising a wake-up generator, wherein when the pulse wave detecting amplifier detects the pulse wave signal, the wake-up generator generates a wake-up signal. The standby circuit of the display device of claim 1, wherein the detector comprises a voltage comparator. The standby circuit of the display device according to claim 5, wherein the voltage comparator is a differential amplifier. The standby circuit of the display device according to claim 1, wherein the switch controller comprises a multiplexer. The standby circuit of the display device according to claim 1, wherein the standby circuit conforms to a digital video interface (DVI) specification or a high resolution multimedia interface (HDMI) specification. A standby method for a display device includes: detecting whether a pulse channel has a periodic voltage change to determine whether the display device enters a standby state, and detecting a first terminating resistor connected to a positive path of the pulse channel a voltage drop, and a voltage drop of the second terminating resistor connected to the negative path of the pulse channel; and when the display device is determined to enter a standby state and a voltage drop is detected, the disconnect and the detecting voltage drop are The associated positive or negative path thereby saves power consumption in the display device standby mode and interrupts one of the positive or negative paths when no voltage drop is detected. The standby method of the display device according to claim 9, further comprising a multiplexing step of allowing a signal of one of the positive path and the negative path to pass according to the result of the detecting. The standby method of the display device according to claim 10, further comprising a step of detecting a pulse wave signal of the multiplexed signal. The standby method of the display device according to claim 11, further comprising a step of generating a wake-up signal when the pulse wave signal is detected. The standby method of the display device according to claim 11, further comprising a step of connecting the positive path and the negative path when the pulse wave signal is detected. The standby method of the display device according to claim 9, wherein the detecting step comprises comparing a voltage drop between the first terminal resistance and the second terminal resistance. The standby method of the display device according to claim 9, wherein the standby method conforms to a digital video interface (DVI) specification or a high resolution multimedia interface (HDMI) specification.