TWI395096B - Power management method and related chipset and computer system - Google Patents

Description

Power management method and related chipset and computer system

The present invention relates to a power management method and related management apparatus and chipset thereof, and more particularly to a power management method based on a processor power state of an Advanced Configuration and Power Interface (ACPI). Used to control the operation of a phase-locked loop in a computer system.

In order to provide power management, current computer systems such as personal computers or portable computers use Advanced Configuration and Power Interface (ACPI) to effectively monitor and distribute the supplied energy to the computer system. Each component in it. ACPI defines five states, such as S0, S1, S3, S4, and S5. However, only the state S0 is the state in which the computer system is operating normally, and the remaining S1 to S5 states, the computer system is in a sleep state. In addition, ACPI further defines the central processor power saving state at state S0.

Figure 1 is a schematic diagram showing the power state of the central processor defined by ACPI. ACPI defines that the central processor operates normally in the full running state (C0 state), such as executing various instructions and operations. If the computer system is idle for more than a predetermined period of time, the operating system will cause the central processor to enter a power saving state such as the C1-C4 state. The operating system determines which power saving state the central processor enters based on the Bus Master activity status on the computer system. The central processor power saving state defined in the ACPI standard includes a first (C1), a second (C2), a third (C3) power saving state, and a fourth (C4) power saving state that is more power efficient than the C3 state. The C2 state saves power compared to the C1 state, the C3 state saves power compared to the C2 state, and the C4 state saves power compared to the C3 state. Therefore, the fourth power saving state (C4) is also referred to as the lowest power consumption state. In the C2 state, the central processor does not execute any instructions, but can snoop on the access actions of the bus master control component (Bus Master), where the busbar master control component refers to the component having the busbar mastership in the computer system. For example, a USB controller, a PCI controller, and the like. At this time, if an interrupt event occurs such that an interrupt occurs, or when the central processing unit is requested to execute an instruction, the central processor returns from the C2 state to the C0 state. In the C3 or C4 state (hereinafter referred to as the C3/C4 state), the CPU stops the clock and cannot snoop the access action of the bus master. The C4 state is in a deeper sleep state than the C3 state. Therefore, C4 is the low power state in all power saving states of the processor, that is, the energy with the least loss.

When the operating system in the computer system detects that the computer system has not acted for more than a predetermined period of time, it will cause the central processing unit to enter the C3/C4 state, thereby making the computer system more efficient in saving power.

In a computer system, a phase lock loop (PLL) is used to generate clock signals of various frequencies, which are generated according to a received low frequency source clock signal to generate high frequency signals of different frequencies. The output is for internal use by the computer system. Phase-locked loops are integrated into most integrated wafers to produce a variety of different high frequency clock sources. However, the action of the phase-locked loop will cause a large amount of power loss. Therefore, how to effectively control the phase-locked loop becomes one of the important topics to reduce power loss.

Conventionally, the phase-locked loop is controlled according to the ACPI system state, such as the S1 state, and in the normal operating state S0 of the computer system, the phase-locked loop generally remains free running and is not controlled. In other words, when the computer system is operating normally, the power loss is not effectively reduced because the phase-locked loop is more power-hungry.

In addition, the computer system generally does not automatically enter the sleep state S1-S5 frequently, but the operating system often sends instructions to set the processor state to the power-saving state C3/C4 state. Therefore, the processor is in the power saving state C3/C4 state for a much longer time than the computer system in the sleep state S1 or other sleep state.

Therefore, there is a need for a phase-locked loop control method and apparatus that can be used when the processor state is set to a power-saving state (C3/C4 state).

In view of this, the present invention provides a power management method suitable for a computer system, wherein the computer system has a processing unit, a power management module (PMU), and a phase locked loop (PLL) circuit, and the power management module is coupled. A plurality of peripheral modules, and the computer system and the processing unit are respectively operable in a working state and a plurality of power saving states. The method comprises: when the computer system is operating in a working state and the processing unit enters one of the lowest power consumption states in the power saving state, detecting the state of the peripheral module to determine whether a specific condition is met; and when the peripheral module When the state meets certain conditions, according to a control state setting, the processing unit enters a control state to control the operation of the phase locked loop.

The embodiment of the present invention further provides a chip set coupled to a clock generator and a processor, including a phase lock loop, a gate control unit, a plurality of peripheral modules, and a power management module. The phase locked loop is configured to generate at least one second clock signal according to the first clock signal generated by the clock generator. The gate control unit is coupled to the phase locked loop for controlling the output of the second clock signal generated by the phase locked loop. Each peripheral module has a low power consumption state. The power management module is coupled to the gate control unit, the peripheral module, and the phase locked loop. When the processing unit enters one of the lowest power consumption states in the power saving state, the power management module detects the state of the peripheral module to determine whether a specific condition is met, and when the state of the peripheral module meets a specific condition According to a control state setting, the processing unit is caused to enter a control state to control the operation of the phase locked loop.

Another embodiment of the present invention provides a computer system including a clock generator, a processing unit, and a chip set. The clock generator is configured to generate a first clock signal. The chipset is coupled to the clock generator and the processing unit, and includes a phase lock loop, a gate control unit, a plurality of peripheral modules, and a power management module. The phase locked loop generates at least one second clock signal according to the first clock signal. The gate control unit is coupled to the phase locked loop for controlling the output of the second clock signal generated by the phase locked loop. Each peripheral module has a low power consumption state. The power management module is coupled to the gate control unit, the peripheral module, and the phase locked loop. Wherein, when the computer system is operating in a working state and the processing unit enters one of the lowest power consumption states in the control state, the power management module detects the state of the peripheral module to determine whether a specific condition is met, and When the state of the module meets certain conditions, according to a control state setting, the processing unit enters a control state to control the operation of the phase locked loop.

The above method of the present invention can be recorded in physical media through code. When the code is loaded and executed by the machine, the machine becomes the means for practicing the invention.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Figure 2 shows a computer system 200 in accordance with an embodiment of the present invention. The computer system 200 can operate in a working state (such as ACPI state S0) and a plurality of power saving states (such as ACPI states S1-S5). Only when operating in the working state, the computer system 200 is in a normal operating state, and the rest. The power saving state is in a sleep state. As shown in FIG. 2, the computer system 200 includes at least a processing unit 210, a clock generator 220, and a chipset 230. The clock generator 220 is configured to generate a first clock signal. The chip set 230 is coupled to the processing unit 210 and the clock generator 220. The chip set 230 includes a phase locked loop 232, a gate control unit 234, a power management module 236, and a plurality of peripheral modules 238. The peripheral module 238 is a bus master or a variety of input and output device controllers. For example, the peripheral module 238 can include a DRAM controller, a PCIe controller, an HDAC controller, an SMBus controller, an LPC controller, an instant clock generator (RTC), an interrupt controller (8259), an APIC, and a PCI control. , but not limited to, SPI & SPI flash memory, SDIO and memory card interface controller, keyboard mouse controller, graphics control chip (GFX), USB controller and SATA controller. Each of the peripheral modules 238 has an operating state and a plurality of power saving states, wherein the most power saving mode in the power saving state is referred to as a low power consumption mode. For example, if the peripheral module 238 is a memory controller, its low power consumption mode operates in a self-refresh mode; if the peripheral module 238 is a graphics control chip, its low power The power saving mode is in the snapshot mode; if the peripheral module 238 is a USB controller, the low power consumption mode is to set the USB device to work in the D3 mode: if the peripheral module 238 is For SATA controllers, the low-power mode saves the SATA device to work in partial/slumber mode.

The phase-locked loop 232 receives the first clock signal generated by the clock generator 220, and generates at least one second clock signal according to the first clock signal, wherein the second clock signal generally has a first time The frequency at which the pulse signal is high. The thyristor 234 is coupled to the phase-locked loop 232 for controlling the output of the second clock signal generated by the phase-locked loop 232. In an embodiment, the thyristor 234 is further coupled to the power management module 236, which determines whether to gag the phase-locked loop according to a control signal PLLG (first control signal) of the power management module 236. The output of the second clock signal of 232, that is, whether to stop the output of the second clock signal. The phase-locked loop 232 is coupled to the power management module 236, which determines whether to shut down the phase-locked loop 232 according to a control signal PLLD (second control signal) of the power management module 236.

The power management module 236 is coupled to the thyristor unit 234 and all of the peripheral modules 238 for performing a power management method according to an embodiment of the present invention for controlling the phase locked loop 232 according to the power saving state of the processing unit 210. operating.

Figure 3 shows a flow chart of a power management method in accordance with an embodiment of the present invention. As described above, the power management method according to an embodiment of the present invention can be performed by the power management module 236 as shown in FIG. 2. Please also refer to Figure 2. First, when the computer system 200 is in the working state and the processing unit 210 enters one of the lowest power consumption states C4 in the control state, the power management module 236 detects the state of all the peripheral modules 238 to determine the state in step S310. Whether or not a specific condition is met (step S320). Please note that the power management module 236 detects the status of the peripheral module 238 (eg, the power state) to determine whether the particular condition is consistent with all of the peripheral modules 238 being idle for a predetermined period of time before making a determination. Since each peripheral module 238 has a low power consumption mode, the power management module 236 detects the status of the peripheral module 238 to determine whether the specific condition is consistent with whether the predetermined peripheral module in the peripheral module is in the Corresponding low power saving mode. In an embodiment, the predetermined peripheral module may include, but is not limited to, a memory controller, a graphics controller, a USB controller, and a SATA controller, and the specific conditions are determined to be met when the following conditions are met. :

(1) The memory controller works in a self-updating mode;

(2) The drawing controller works in snapshot mode;

(3) USB controller sets the USB device to work in D3 mode:

(4) The SATA controller sets the SATA device to work in partial/slumber mode.

In other words, the power management module 236 determines that the specific condition is met only if the above conditions (1)-(4) are met, otherwise it is determined that the specific condition is not met. As described above, since the above determination is performed after all the peripheral modules 238 are idle for a predetermined period of time, in addition to the conditions of the predetermined peripheral modules that need to meet the above conditions (1)-(4), other peripheral modules are Idle state.

When the state of the peripheral module does not meet the specific condition (No in step S320), for example, if the above conditions (1)-(4) do not match or any defined wake-up event occurs, no special processing is performed, and the flow ends.

When the state of the peripheral module meets the specific condition (Yes in step S320), the power management module 236 is configured according to a preset control state, causing the processing unit 210 to enter a phase locked loop control state to control the phase locked loop 232. Operation (step S330). For example, in one embodiment, a control state setting option can be provided in a basic input/output system (BIOS) (not shown) of the computer system to set a control state after entering the phase locked loop control state. In this embodiment, the phase locked loop control state has two control state setting values: a first control state (C4PG) and a second control state (C4PD). The set value will be stored in a register (not shown), for example, the set value 1 indicates the first control state, and the set value 0 indicates the second control state. Referring to FIG. 4, there is shown a schematic diagram of a power state of a central processing unit in accordance with an embodiment of the present invention. As shown in FIG. 4, the power state of the central processing unit has a working state C0, a first power saving state C1, a second power saving state C2, a third power saving state C3, a minimum power consumption state C4, and two possibilities. The phase locked loop controls the state C4PG (first control state) and C4PD (second control state). Among them, the states C0 to C4 are similar to the corresponding states in FIG. 1, and the phase-locked loop control states C4PG and C4PD are selectively entered according to the set values in the register. For example, when the processing unit 210 enters the lowest power consumption state C4, if the set value in the register is 1, the processing unit 210 will enter the first control state (C4PG). Conversely, when the processing unit 210 enters the lowest power consumption state C4, if the set value in the register is 0, the processing unit 210 will enter the second control state (C4PD). After the processing unit 210 enters the first or second control state, if any wake-up event is detected, the power management module 236 performs a recovery procedure to restore the processing unit 210 to the lowest power consumption state C4.

In step S330, when the control state is set to the first control state, the power management module 236 sends a control signal PLLG to the gate control unit 234 to stop the clock output of the phase locked loop 232 through the gate control unit 234. At this time, the clock output of the phase locked loop 232 is blocked, but the phase locked loop 232 is not powered down, and the power remains. When the control state is set to the second control state, the power management module 236 sends the control signal PLLD to the phase locked loop 232. After the phase locked loop 232 receives the control signal PLLD, the phase locked loop 232 will be completely turned off. In an embodiment, when the control state is set to the second control state, the power management module 236 sends the control signal PLLD and the control signal C4PSTOP (third control signal) to the phase-locked loop 232 and the clock outside the chip set 230, respectively. The generator 220 (the source clock generating unit corresponding to the phase locked loop 232). After the phase locked loop 232 receives the control signal PLLD, the phase locked loop 232 will be fully closed. After the clock generator 220 receives the control signal C4PSTOP, the clock generator 220 will stop outputting the clock signal to the phase locked loop 232.

After the processing unit 210 enters the phase locked loop control state, if a wakeup event is detected, the power management module 236 will perform a recovery procedure to cause the processing unit to return to the lowest power consumption state C4.

Figure 5 shows a flow chart of a recovery procedure in accordance with an embodiment of the present invention. As described above, the power management method in accordance with an embodiment of the present invention can be performed by the power management module 236 as shown in Figure 2.

As shown in FIG. 5, referring to FIG. 4, in step S510, the power management module 236 first determines whether the processing unit 210 is in the first or second control state by the set value of the register. For example, in an embodiment, when the set value of the register is 1 or 0, it can be determined that the processing unit 210 is in the first or second control state, respectively. If it is in the first control state, it indicates that the processing unit 210 is to return from the first control state to the C4 state, and vice versa, that the processing unit 210 is to return from the second control state to the C4 state. When it is determined by the set value of the register that the processing unit 210 is in the first control state, as in step S520, since the phase locked loop 232 is not turned off, only the clock output thereof is blocked by the gate control unit 234, so the recovery procedure is directly The blocking phase-locked loop 232 is stopped by the gate control unit 234, and then step S560 is performed. When it is determined by the setting value of the register that the processing unit 210 is in the second control state, it is determined in step S530 whether the clock generator 220 receives the control signal C4PSTOP, and if not, it indicates that the clock generator 220 does not stop outputting. The pulse signal, on the other hand, indicates that the clock generator 220 stops outputting the clock signal. When the pulse generator 220 receives the control signal C4PSTOP (YES in step S530), since the phase locked loop 232 is turned off and the output of the external clock generator is stopped, the recovery program executes steps S540 and S550 to resume the stopped time. Pulse and start phase locked loop 232. In step S540, the recovery program first starts the output of the source clock generation unit (also the immediate pulse generator 220) corresponding to the phase-locked loop 232, and after the source clock generation unit is started, in step S550, the phase-locked loop is started. 232, then step S560 is performed. The clock generator 220 does not receive the control signal C4PSTOP (NO in step S530), because the clock generator 220 does not stop outputting the clock signal, so the recovery program directly executes step S550 to start the phase-locked loop 232, and then performs the steps. S560. In step S560, after the recovery program waits for the phase-locked loop 232 to start stable, finally, the power state of the processing unit 210 is restored to the lowest power-saving state C4.

The following examples are provided to further illustrate the power management method of the present invention, but are not intended to limit the present invention.

In this embodiment, it is assumed that the processing unit 210 has entered the lowest power consumption state C4 due to a period of inactivity and the set value of the register is zero. After all the peripheral modules 238 are idle for a predetermined time, the power management module 236 detects the status of the peripheral module 238 to determine whether the specific conditions are met, that is, whether the foregoing conditions (1)-(4) are satisfied. Assuming that conditions (1)-(4) are satisfied, indicating that the specific conditions are met, the power management module 236 is set according to the preset control state, causing the processing unit 210 to enter a phase-locked loop control state to control the operation of the phase-locked loop 232. . Since the set value of the register is 0, indicating that the second control state is to be entered, the power management module 236 sends the control signal PLLD phase-locked loop 232. After the phase-locked loop 232 receives the control signal PLLD, the phase-locked loop 232 will shut down.

In one embodiment, the set value of the register is 0, indicating that the second control state is to be entered, and the power management module 236 sends the control signal PLLD and the control signal C4PSTOP to the phase-locked loop 232 and the clock outside the chip set 230, respectively. Generator 220. After the phase locked loop 232 receives the control signal PLLD, the phase locked loop 232 will be fully closed. After the clock generator 220 receives the control signal C4PSTOP, the clock generator 220 will stop outputting the clock signal to the phase locked loop 232. Therefore, the processing unit 210 enters the second control state and the phase locked loop 232 is turned off and the output of the external clock generator is stopped. Thereafter, if a wake-up event is detected, the power management module 236 will perform a recovery procedure, since the clock generator 220 receives the control signal C4PSTOP, indicating that the phase-locked loop 232 is turned off and the output of the external clock generator is output. It is stopped, so the recovery program first starts the clock generator 220 to restore the output, and after the clock generator 220 is started, causes the processing unit 210 to return to the lowest power consumption state C4.

In summary, the power management method and related chipset and computer system according to the present invention can control the state through a new phase-locked loop to provide a state in which the processing unit enters the lowest power consumption state (ie, state C4). The phase-locked loop control, because the processing unit will often be in the lowest power consumption state during normal execution, can more effectively reduce the power loss of the entire computer system, and achieve the purpose of power control.

The method of the present invention, or a specific type or part thereof, may be included in a physical medium such as a floppy disk, a compact disc, a hard disk, or any other machine (for example, a computer readable computer). A storage medium in which, when the code is loaded and executed by a machine, such as a computer, the machine becomes a device for participating in the present invention. The method and apparatus of the present invention can also be transmitted in a code format through some transmission medium such as a wire or cable, an optical fiber, or any transmission type, wherein the code is received, loaded, and executed by a machine such as a computer. At this time, the machine becomes a device for participating in the present invention. When implemented in a general purpose processor, the code in conjunction with the processor provides a unique means of operation similar to application specific logic.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

C0-C4, C4PD, C4PG. . . status

200. . . computer system

210. . . Processing unit

220. . . Clock generator

230. . . Chipset

232. . . Phase-locked loop

234. . . Gating unit

236. . . Power management module

238. . . Peripheral module

C4PSTOP, PLLD, PLLG. . . Control signal

S310-S330. . . Steps

S510-S560. . . Steps

Figure 1 is a schematic diagram showing the power state of a conventional ACPI-defined central processor.

Figure 2 shows a computer system in accordance with an embodiment of the present invention.

Figure 3 is a flow chart showing a power management method in accordance with an embodiment of the present invention.

Figure 4 is a diagram showing the power state of a central processing unit in accordance with an embodiment of the present invention.

Figure 5 is a flow chart showing a recovery procedure in accordance with an embodiment of the present invention.

200. . . computer system

210. . . Processing unit

220. . . Clock generator

230. . . Chipset

232. . . Phase-locked loop

234. . . Gating unit

236. . . Power management module

238. . . Peripheral module

C4PSTOP, PLLD, PLLG. . . Control signal

Claims (21)

A power management method is applicable to a computer system, wherein the computer system has a processing unit, a power management module, and a phase locked loop (PLL) circuit, wherein the power management module is coupled to the plurality of peripheral modules, and the The computer system and the processing unit are respectively operable in a working state and a plurality of power saving states, the method comprising: when the computer system operates in the working state and the processing unit enters one of the power saving states In the electrical state, detecting the state of the peripheral modules to determine whether a particular condition is met; and when the states of the peripheral modules meet the specific condition, setting the control unit according to a control state, causing the processing unit to enter a control a state to control the phase locked loop, wherein each of the peripheral modules has a low power consumption mode and the state of the peripheral modules is detected to determine whether the specific condition is consistent with determining the peripheral modules Whether the predetermined peripheral module is in the corresponding low power consumption mode. The power management method of claim 1, wherein the step of causing the processing unit to enter the control state to control the phase locked loop according to the control state setting further comprises: when the control state is set to a first When the state is controlled, a first control signal is sent to interrupt the clock output of the phase locked loop; and when the control state is set to a second control state, a second control signal is sent to close the phase locked loop. The power management method according to claim 1, wherein the processing unit is configured to cause the processing unit to enter the control state. The step of controlling the phase-locked loop further includes: when the control state is set to a second control state, respectively sending a second control signal and a third control signal to close the phase-locked loop and the phase-locked loop corresponding to the phase-locked loop The output of a source clock generation unit. The power management method according to claim 1, further comprising: providing a control state setting option in the basic input/output system (BIOS) to set the control state. The power management method of claim 1, wherein the predetermined peripheral modules comprise a memory controller, a graphics controller, a USB controller, and a SATA controller, and when the following conditions are met, The power management module determines that the specific condition is consistent: the memory controller operates in a self-refresh mode; the graphics controller operates in a snapshot mode; and the USB controller sets the USB device to work. In D3 mode: and SATA controllers set the SATA device to work in partial/slumber mode. The power management method of claim 1, wherein the detecting the status of the peripheral modules to determine whether the specific condition is consistent after the peripheral modules are idle for a predetermined time. The power management method of claim 2, wherein when a wakeup event is detected in the control state, a recovery procedure is executed, causing the processing unit to return to the lowest power consumption state, and When the control state is set to the first control state, the recovery program stops interrupting the output of the phase locked loop. The power management method of claim 2, wherein when a wakeup event is detected in the control state, a recovery procedure is executed, causing the processing unit to return to the lowest power consumption state, and The recovery procedure initiates the phase locked loop when the control state is set to the second control state. The power management method of claim 3, wherein when a wakeup event is detected in the control state, a recovery procedure is executed, causing the processing unit to return to the lowest power consumption state, and When the control state is set to the second control state and the third control signal is sent, the recovery program starts the output of the source clock generation unit corresponding to the phase-locked loop, and starts after the source clock generation unit is started. The phase locked loop. A chip set coupled to a clock generator and a processor, comprising: a phase locked loop for generating at least one second clock signal according to the first clock signal generated by the clock generator; a gate control unit coupled to the phase lock loop for controlling an output of the second clock signal generated by the phase lock loop; a plurality of peripheral modules, each of the peripheral modules respectively having a low power consumption And a power management module coupled to the gate control unit, the peripheral modules, and the phase locked loop; wherein when the processing unit enters one of the lowest power consumption states of the power saving states, The power management module detects the status of the peripheral modules to determine whether a specific condition is met, and when the peripheral modules are When the state meets the specific condition, according to a control state setting, the processing unit enters a control state to control the phase-locked loop and each of the peripheral modules respectively has a low-power power-saving mode and the power management The module further determines whether the predetermined peripheral module in the peripheral modules is in the corresponding low power consumption mode to determine whether the specific condition is met. The chip set of claim 10, wherein when the control state is set to a first control state, the power management module sends a first control signal to the gating unit to gating The second clock signal of the phase locked loop is output, and when the control state is set to a second control state, the power management module sends a second control signal to close the phase locked loop. The chip set of claim 10, wherein when the control state is set to a second control state, the power management module respectively sends a second control signal and a third control signal to the phase locked loop. And the clock generator to turn off the phase locked loop and the output of the clock generator corresponding to the phase locked loop. The chip set of claim 10, wherein the predetermined peripheral modules comprise a memory controller, a graphics controller, a USB controller, and a SATA controller, and the power management is performed when the following conditions are met. The module determines that the specific condition is consistent: the memory controller operates in a self-refresh mode; the drawing controller operates in a snapshot mode; the USB controller sets the USB device to operate D3 mode: and SATA controllers set SATA devices to work in partial/sleep (partial/slumber). The chip set of claim 10, wherein the power management module detects the status of the peripheral modules to determine whether the specific condition is consistent after the peripheral modules are idle for a predetermined time. The chip set of claim 11, wherein when a wake-up event is detected in the control state, the power management module performs a recovery process to cause the processing unit to return to the lowest power consumption province. In an electrical state, when the control state is set to the first control state, the recovery procedure stops interrupting the output of the phase locked loop through the gating unit. The chip set of claim 11, wherein when a wake-up event is detected in the control state, the power management module performs a recovery process to cause the processing unit to return to the lowest power consumption province. The electrical state, when the control state is set to the second control state, the recovery program starts the output of the clock generator corresponding to the phase locked loop. The chip set of claim 12, wherein when a wakeup event is detected in the control state, the power management module performs a recovery procedure to cause the processing unit to return to the lowest power consumption province. The electrical state, when the control state is set to the second control state, the recovery program starts the output of the clock generator corresponding to the phase locked loop, and starts the phase locked loop after the clock generator is started. A computer system comprising: a clock generator for generating a first clock signal; a processing unit; and a chip set coupled to the clock generator and the processing unit, comprising: a phase-locked loop for generating at least one second clock signal according to the first clock signal; a gate control unit coupled to the phase-locked loop for controlling the second time generated by the phase-locked loop An output of the pulse signal; a plurality of peripheral modules, each of the peripheral modules respectively having a low power consumption mode; and a power management module coupled to the gate control unit, the peripheral modules, and the lock a phase loop; wherein when the computer system is operating in a working state and the processing unit enters one of the lowest power consumption states of the power saving states, the power management module detects the states of the peripheral modules, Determining whether a specific condition is met, and when the state of the peripheral modules meets the specific condition, according to a control state setting, causing the processing unit to enter a control state to control the phase-locked loop, and each of the peripherals The modules respectively have a low power consumption mode, and the power management module further determines whether the predetermined peripheral modules in the peripheral modules are in the corresponding low power consumption mode to determine whether the specific conditions are met. The computer system of claim 18, wherein when the control state is set to a first control state, the power management module sends a first control signal to the gating unit to block the phase lock. The second clock signal of the loop is output, and when the control state is set to a second control state, the power management module sends a second control signal to close the phase locked loop. For example, the computer system described in claim 18, wherein When the control state is set to a second control state, the power management module respectively sends a second control signal and a third control signal to the phase locked loop and the clock generator to close the phase locked loop and the The phase-locked loop corresponds to the output of the clock generator. The computer system of claim 18, wherein the predetermined peripheral modules comprise a memory controller, a graphics controller, a USB controller, and a SATA controller, and the power management is performed when the following conditions are met. The module determines that the specific condition is consistent: the memory controller operates in a self-refresh mode; the drawing controller operates in a snapshot mode; the USB controller sets the USB device to operate D3 mode: And the SATA controller sets the SATA device to work in partial/slumber.