TWI391940B - Non-volatile memory system with soft bit data transmission for error correction control and method of reading the same - Google Patents

Description

Non-volatile memory system with soft bit data transmission with error correction control and reading method thereof

Embodiments of the present disclosure are directed to non-volatile memory technology.

This application is related to the non-volatile memory system with soft bit data transmission with error correction control and its reading method (Soft Bit) US Patent Application Serial No. 11/694,947, the disclosure of which is incorporated herein by reference.

Semiconductor memory has become increasingly popular in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Among the most popular non-volatile semiconductor memories are electrically erasable programmable read-only memories (EEPROM) and flash memory. In the case of flash memory (also a type of EEPROM), the contents of the entire memory array or the contents of a portion of the memory can be erased in one step compared to conventional full-featured EEPROMs.

Both conventional EEPROM and flash memory utilize a floating gate that is positioned above and insulated from the channel region in the semiconductor substrate. The floating gate is positioned between the source region and the drain region. The control gate is provided above the floating gate and insulated from the floating gate. The threshold voltage (V _TH ) of the thus formed transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the charge level on the floating gate. Another type of memory cell that can be used in a flash EEPROM system utilizes a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner.

Some EEPROM and flash memory devices have floating gates for storing two ranges of charge, and thus, the memory elements can be stylized/wiped between two states (eg, erased state and stylized state). except. Such flash memory devices are sometimes referred to as binary flash memory devices because each memory element can store a data bit.

A polymorphic (also known as multi-level) flash memory device is implemented by identifying a plurality of distinct allowed/effectively programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value encoded in a set of data bits in the memory device. For example, when each memory component can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges, the component can store two data bits.

Typically, the stylized voltage V _PGM applied to the control gate during the stylization operation is applied in the form of a series of pulses that increase in magnitude over time. In one possible approach, the magnitude of the pulse is increased by a predetermined step size, for example, 0.2 to 0.4 V, with each successive pulse. V _PGM can be applied to the control gate of the flash memory component. The verification operation is performed during the period between the stylized pulses. That is, the stylized level of each of a group of elements is programmed in parallel between consecutive stylized pulses to determine whether it is equal to or greater than the verify level to which the element is programmed. For a multi-state flash memory device array, a verification step can be performed on each state of the component to determine if the component has reached its data association verification level. For example, a polymorphic memory component capable of storing data in four states may need to perform a verify operation on three comparison points.

In addition, when programming an EEPROM or flash memory device (such as a NAND flash memory device in a NAND string), V _PGM is typically applied to the control gate and the bit line is grounded so that it will come from a cell or Electrons of the channels of the memory elements (eg, storage elements) are injected into the floating gates. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory element rises such that the memory element is considered to be in a stylized state. This can be found in US Patent Application Publication No. 2005/0024939, entitled "Detecting Over Programmed Memory", entitled "Source Side Self Boosting Technique For Non-Volatile Memory", US Patent No. 6,859,397, issued Feb. 3, 2005. More information on stylization; these patents are hereby incorporated by reference in their entirety.

Once the non-volatile storage element has been programmed, it is important to be able to read back its stylized state with high reliability. However, the sensed stylized state may sometimes differ from the desired stylized state due to factors including noise and the tendency of the device to tend to be charge neutral over time.

Therefore, erroneous or corrupted data bits are often encountered when reading non-volatile memory. Typically, some form of error correction control (ECC) is applied to correct erroneous or corrupted material. An ordinary control stores additional parity bits to set the parity of a group of data bits to the desired logic when writing data Value. The information and the parity bits form the code words stored during the writing process. The ECC decodes the bits by calculating the parity of the group of bits while reading the data to detect any corrupted or erroneous data.

The data stored in the non-volatile memory is decoded using repeated probability decoding. Error correction codes such as low density parity check codes can be used. In one approach, an initial reliability metric, such as a log likelihood ratio, is used to decode the sensed state of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metric of the bits in the codeword representing the sensed state. If the decoding fails to converge, the soft data bit can be read from the memory. When receiving more information, different initial reliability metrics are provided after receiving hard read results and after different stages of soft bit operation. In one embodiment, the second soft bit is read from the memory using a plurality of subsets of soft bit comparison levels. When reading is performed under the second subset of comparison levels, decoding can be performed based on the first subset of material. In an embodiment, different subsets of the read comparison levels of the second soft bit read may be intelligently selected based on characteristics of different states of the memory cells. For example, an individual memory system or group of systems can be characterized to determine the nature of the offset of the apparent or actual charge level of the memory unit after stylization.

In one embodiment, a method of reading a non-volatile memory is provided, comprising: reading user data from a set of non-volatile storage elements using a first plurality of read comparison points, wherein each comparison point corresponds to a programmable state in one of the storage elements; using a second plurality of read comparison points having a greater number of read comparison points than the first plurality of read comparison points Reading a set of soft data from the set of storage elements at a high bit resolution of the user data; and using the first child of the soft data while reading to determine a second subset of the soft data Set to decode the user data.

Another method of reading a non-volatile storage device includes providing a set of read comparison points for a plurality of non-volatile storage elements as part of the error correction control process while reading the first set of data from the storage element. The set of read comparison points includes a first subset of read compare points having a read compare point corresponding to each of the programmable states of the storage elements, and having a corresponding one of the storage elements The second subset of the comparison comparison points is read by the read point of the programmable state. The first subset is provided prior to the second subset. The method further includes determining a second set of data based on reading the first subset of comparison points, and using the second while providing the second subset of read comparison points for the plurality of non-volatile storage elements The group data is used to repeatedly decode the first set of data.

The method of an embodiment provides a first log likelihood table to repeatedly decode a set of data from a plurality of non-volatile storage elements using the first set of comparison points, providing a second log likelihood table for use Decoding the first set of data by using the second set of data read from the storage elements using the second set of comparison points, providing a third log likelihood table to use the second set of data and And the third set of data read by the storage component to repeatedly decode the first set of data, and provide a fourth log likelihood table to use the second set of data, the third set of data, and read from the storage elements The fourth set of data is taken to repeatedly decode the first set of data.

An exemplary embodiment includes a set of non-volatile storage elements and The volatile storage element communicates with one or more management circuits. The one or more management circuits can perform the above method. In one embodiment, the management circuit uses the error correction control to perform reading by reading user data from the set of non-volatile storage elements using the first plurality of read comparison points, each comparison point. Corresponding to a programmable state of one of the storage elements; using a second plurality of read comparison points having a greater number of read comparison points than the first plurality of read comparison points to be higher than the user profile Reading a set of soft data from the set of storage elements at a bit resolution; and decoding the use using a first subset of the soft data while reading to determine a second subset of the soft data Information.

One example of a flash memory system uses a NAND structure that includes a plurality of transistors arranged in series between two select gates. The tandem transistors and the select gates are referred to as NAND strings. FIG. 1 is a top plan view showing a NAND string 30. Figure 2 is its equivalent circuit. The NAND string depicted in Figures 1 and 2 includes four transistors 10, 12, 14 and 16 arranged in series between a first select gate 12 and a second select gate 22. Select gate 12 connects the NAND string to bit line 26. Select gate 22 connects the NAND string to bit line 28. The selection gate 12 is controlled by applying an appropriate voltage to the control gate 20CG via the selection line SGD. The selection gate 22 is controlled by applying an appropriate voltage to the control gate 22CG via the selection line SGS. Each of the transistors 10, 12, 14 and 16 includes a control gate and a floating gate, both of which form a gate element of the memory cell. For example, the transistor 10 includes a control gate 10CG and a floating gate 10FG. The transistor 12 includes a control gate 12CG and float The gate is 12FG. The transistor 14 includes a control gate 14CG and a floating gate 14FG. The transistor 16 includes a control gate 16CG and a floating gate 16FG. The control gate 10CG is connected to the word line WL3, the control gate 12CG is connected to the word line WL2, the control gate 14CG is connected to the word line WL1, and the control gate 16CG is connected to the word line WL0.

Note that although Figures 1 and 2 show four memory cells in the NAND string, the use of four transistors is provided as an example only. A NAND string can have fewer than four memory cells or more than four memory cells. For example, some NAND strings include 8 memory cells, 16 memory cells, 32 memory cells, and the like. The discussion herein is not limited to any particular number of memory cells in a NAND string. NAND-type flash memory and related examples of its operation are provided in the following U.S. Patent Application Serial No. 5,570,315; U.S. Patent No. 5,774,397; U.S. Patent No. 6,046,935 No. 5,386,422; U.S. Patent No. 6,456,528; and U.S. Patent Application Serial No. 09/893,277, the disclosure of which is incorporated herein by reference. Other types of non-volatile memory other than NAND flash memory can also be used, depending on the embodiment.

A typical architecture for flash memory using NAND structures includes many NAND strings. FIG. 3 illustrates an exemplary array 100 of NAND strings, such as the NAND strings shown in FIGS. 1-2. The memory cell array 100 is divided into a plurality of memory cell blocks. As common to flash EEPROM systems, the block is an erase unit and may be referred to as an erase block or a physical block. Each block can contain the smallest number of memory cells that are erased together, but can be wiped simultaneously Except for multiple blocks. In some embodiments, fewer memory cells can be erased together.

Each block of the memory cell includes a group of bit lines forming a row and a group of word lines forming a column. Each block is usually divided into a number of pages. A page is usually the smallest unit of stylization or reading, but can be programmed or read more than one page in a single operation. In another embodiment, individual pages may be divided into segments, and the segments may contain a minimum number of cells that are written once during a basic stylized operation. One or more pages of data are typically stored in a list of memory cells. A page can store data for one or more sectors, the size of which is typically defined by the host system. One sector includes user data and additional item data. The additional item data usually includes an error correction code (ECC) calculated from the user data of the sector. One portion of the controller (described below) calculates the ECC when the data is programmed into the array, and also checks the data as it is read from the array. Alternatively, the ECC and/or other additional item data may be stored in a different page or block than the page or even the block to which the user profile belongs. The user data for a sector is typically 512 bytes, which corresponds to the size of the sector commonly used in disk drives. The additional item data is usually an additional 16 to 20 bytes. A large number of pages form a block, the number being between 8 pages (for example) up to 32, 64 or more pages. In some embodiments, a column of NAND strings includes a block.

Although four cells are included in each NAND string of FIG. 4, more or less than four cells (eg, 16, 32, or another number) may be used. One terminal of the NAND string is connected to the corresponding bit line (connected to the selected gate drain line SGD) via the first selection gate, and the other terminal is selected via the second The gate is connected to a common source line c-source (connected to the select gate source line SGS). In each block of this example, there are 8,512 rows divided into even rows and odd rows. The bit lines are divided into even bit lines (BLe) and odd bit lines (BLo). In an odd/even bit line architecture, memory cells along a common word line and connected to odd bit lines are programmed at one time, while stylized along a common word line and connected to even bits at another time. The memory unit of the meta line. In this example, the data of 532 bytes can be read or programmed simultaneously and form a logical page. Therefore, a block can store at least eight pages. When two data bits are stored in each memory unit, one block will store 16 pages. Blocks and pages of other sizes may also be used, and in accordance with the present disclosure, an architecture other than the architecture of Figures 1-3 may be used.

In other embodiments, the bit lines are not divided into odd bit lines and even bit lines. These architectures are often referred to as full bit line architectures. In a full bit line architecture, all bit lines of a block are simultaneously selected during read and program operations. At the same time, the memory cells along the common word line and connected to any bit line are programmed. In other embodiments, bit lines or blocks may be classified into other groups (eg, left and right, more than two groups, etc.).

4 illustrates a memory device 110 having read/write circuits for reading and programming one page of memory cells in parallel. Memory device 110 can include one or more memory dies or wafers 112. The memory die 112 includes a two-dimensional memory cell array 100, a control circuit 120, and read/write circuits 130A and 130B. In the embodiment of FIG. 4, access to the memory array 100 by various peripheral circuits is performed symmetrically on opposite sides of the array such that the density of access lines and circuitry on each side is halved. In other embodiments Various peripheral circuits are provided in an asymmetric manner on one side of the array. The read/write circuits 130A and 130B include a plurality of sensing blocks 200 that allow one page of memory cells to be read or programmed in parallel. Memory array 100 can be addressed by word lines via column decoders 140A and 140B and can be addressed by bit lines via row decoders 142A and 142B. In the exemplary embodiment, controller 144 and the one or more memory dies 112 are included in the same memory device 110 (eg, a removable memory card or kit). Commands and data are transferred between the host and controller 144 via line 132 and between the controller and the one or more memory dies 112 via line 134.

Control circuit 120 cooperates with read/write circuits 130A and 130B to perform a memory operation on memory array 100. Control circuit 120 includes state machine 122, on-chip address decoder 124, and power control module 126. State machine 122 provides wafer level control of memory operations. The on-chip address decoder 124 provides an address interface between the address used by the host or memory controller and the hardware address used by the decoders 140A, 140B, 142A, and 142B. Power control module 126 controls the power and voltage supplied to the word lines and bit lines during memory operation.

FIG. 5 is a block diagram of an individual sensing block 200 divided into a core portion (referred to as sensing module 210) and a common portion 220. In an embodiment, each bit line has an independent sensing module 210, and a plurality of sensing modules 210 have a common portion 220. In one example, a sensing block will include a common portion 220 and eight sensing modules 210. Each of the sensing modules in a group will communicate with the associated common portion via data bus 216. For more details, please refer to the US special application filed on December 29, 2004. No. 11/026,536, "Non-Volatile Memory & Method with Shared Processing for an Aggregate of Sense Amplifiers", which is incorporated herein in its entirety by reference.

The sensing module 210 includes a sensing circuit 214 that determines whether the conductive current in the connected bit line is above or below a predetermined threshold level. The sensing module 210 also includes a bit line latch 212 for setting a voltage condition on the connected bit line. For example, the predetermined state latched in the bit line latch 212 will cause the connected bit line to be pulled to a state that specifies a stylization inhibit (eg, V _DD ).

The common portion 220 includes a processor 222, a set of data latches 224, and an I/O interface 226 coupled between the set of data latches 224 and the data bus 230. Processor 222 performs the calculations. For example, one of its functions is to determine the data stored in the sensed memory unit and store the determined data in the set of data latches. The set of data latches 224 is used to store the data bits determined by the processor 222 during a read operation. It is also used to store data bits entered from the data bus 230 during stylized operations. The input data bits represent the data to be programmed into the memory. The data read from a unit is stored in the set of data latches prior to being combined with the additional data and sent to the controller via I/O interface 226.

During reading or sensing, the operation of the system is under the control of state machine 122, which controls the supply of different control gate voltages to the addressed unit. As it progressively debugs various predetermined control gate voltages corresponding to various memory states supported by the memory, the sensing module 210 can trip at one of the voltages and will pass through the busbar 216. An output self-sensing Module 210 is provided to processor 222. At this time, the processor 222 determines the resulting memory state by considering the tripping event of the sensing module and the information about the control gate voltage applied from the state machine via the input line 228. It then computes the binary code of the memory state and stores the resulting data bit into data latch 224. In another embodiment of the core portion, the bit line latch 212 is used for dual purposes, both as a latch for latching the output of the sense module 210 and also as a bit line latch as described above. .

During stylization or verification, the data to be programmed from the data bus 230 is stored in the set of data latches 224. The stylized operation under state machine control includes a series of stylized voltage pulses applied to the control gates of the addressed memory cells. Each stylized pulse is followed by a read back (verification) to determine if the unit has been programmed to the desired memory state. Processor 222 monitors the read back memory state relative to the desired memory state. When the two agree, the processor 222 sets the bit line latch 212 to cause the bit line to be pulled to the specified stylized inhibit state. This unit, which is prohibited from being coupled to the bit line, is further programmed, even if a stylized pulse appears on its control gate. In other embodiments, the processor initially loads the bit line latch 212 and the sensing circuit sets it to a disable value during the verification process.

The data latch stack 224 includes a stack of data latches corresponding to the sense modules. In one embodiment, each sensing module 210 has at least four data latches to store four data bits for/from a unit. In some embodiments (but not necessarily), the data latch is implemented as a shift register such that parallel data stored therein is converted to a data bus 230 serial data, and the serial data stored therein is converted into parallel data for data bus 230. In a preferred embodiment, all of the data latches corresponding to the read/write blocks having m memory cells can be linked together to form a block shift register so that it can be transmitted by serial And input or output data blocks. In particular, a group of r read/write modules is adapted such that each of its data latch groups sequentially shifts data into or out of the data bus as if it were an entire read/write The part of the block shift register.

Additional information regarding the structure and/or operation of various embodiments of non-volatile storage devices can be found in the following documents: (1) U.S. Patent Application Publication No. 2004/0057287, issued March 25, 2004, to -Volatile Memory And Method With Reduced Source Line Bias Errors"; (2) US Patent Application Publication No. 2004/0109357, published on Jun. 10, 2004, "Non-Volatile Memory And Method with Improved Sensing"; (3) U.S. Patent Application Serial No. 11/015,199, entitled "Improved Memory Sensing Circuit And Method For Low Voltage Operation", filed on December 16, 2004 by Raul-Adrian Cernea; (4) Inventor Jian Chen, 2005 U.S. Patent Application Serial No. 11/099,133, entitled "Compensating for Coupling During Read Operations of Non-Volatile Memory", filed on April 5, 2005; and (5) Inventor Siu Lung Chan and Raul-Adrian Cernea, 2005 U.S. Patent Application Serial No. 11/321,953, entitled "Reference Sense Amplifier For Non-Volatile Memory", filed on the 28th. All five patent documents just listed above The manner of citation is incorporated herein in its entirety.

6 is a graph depicting an exemplary threshold voltage distribution of a population of memory cells as each memory cell stores four data bits. The 16 distinct threshold voltage ranges are defined as 16 memory states of 0 to 15. A first threshold voltage distribution is designated as state 0 and includes an erased memory cell having a threshold voltage of less than 0 volts. The remaining threshold voltage distributions are designated as states 1 through 15, and include memory cells that are programmed into one of the threshold voltage ranges. In some embodiments, the additional ones of states 1 through 15 may also correspond to a negative threshold voltage range. For example, some embodiments may adjust the source and body bias to provide a positive voltage operating range when in a lower state.

Each of the distinct threshold voltage ranges of Figure 6 corresponds to a predetermined value for the set of data bits. The specific relationship between the data programmed into a memory cell and the corresponding threshold voltage level of the cell depends on the data encoding scheme employed. For example, Gray code assignments are typically used to assign data values to different threshold voltage ranges such that if the threshold voltage of the floating gate is erroneously shifted to the neighboring entity state, only one bit is affected. However, in other embodiments, the Gray code is not used. Figure 6 illustrates an example of assigning data bits to different threshold voltage ranges when storing 4 data bits per memory cell. In Figure 6, the different bits are uniquely identified as top, higher, high or low, with the lower bit being the most significant bit and the top bit being the least significant bit. This representation is merely exemplary. Moreover, while FIG. 6 shows 16 states, other structures and configurations can be used in accordance with the present disclosure, including structures and configurations that include more or less than four states.

The distribution chart states below the encoded data bits corresponding to each state. State 0 stores 1 for each bit position (including top, upper, high, and low bits). State 1 stores 0 for the top bit position and 1 for each of the remaining bit positions. As mentioned previously, a data bit represented by a stylized state of a storage element can be considered a codeword. For example, in the case of 16 states, a code word of four bits can be used.

When reading non-volatile memory, at least one reference threshold voltage level is typically established between each state to divide the threshold voltage memory window of the memory cell into a certain number of ranges used. The threshold voltage of a unit and each reference level (also referred to as a comparison point) can be compared to determine the memory state of the unit. A predetermined, fixed voltage (eg, a read reference voltage) corresponding to the reference threshold voltage level can be applied to the gate of a cell, and its source/drain conductive state by the conductive and a breakpoint A reference or reference current is established for comparison.

Figure 6 shows 15 read comparison points V1 through V15 for reading data from a memory cell. By testing whether the threshold voltage of a given memory cell is above or below each comparison point, the system can determine what state the memory cell is in. If a memory cell conducts while V1 is applied to its control gate, the memory cell is in state 0. If a memory cell is conducting at V2 instead of at V1, the memory cell is in state 1. If the memory cell is conducting at V3 instead of at V2, the memory cell is in state 2. If the memory cell is conducting at V4 instead of at V3, the memory cell is in state 3. If the memory cell is conducting at V5 instead of at V4, the memory cell is in state 4. If the memory unit is at V6 instead of under V5 Conductive, then the memory cell is in state 5. If the memory cell is conducting at V7 instead of at V6, the memory cell is in state 6. If the memory cell is conducting at V8 instead of at V7, the memory cell is in state 7. If the memory cell is conducting at V9 instead of at V8, the memory cell is in state 8. If the memory cell is conducting at V10 instead of at V9, the memory cell is in state 9. If the memory cell is conducting at V11 instead of at V10, the memory cell is in state 10. If the memory cell is conducting at V12 instead of at V11, the memory cell is in state 11. If the memory cell is conducting at V13 instead of at V12, the memory cell is in state 12. If the memory cell is conducting at V14 instead of at V13, the memory cell is in state 13. If the memory cell is conducting at V15 instead of at V14, the memory cell is in state 14. The memory cell is in state 15 if the memory cell is not conducting under any of the comparison voltage levels.

Figure 6 also shows 15 verification comparison points Vv1-Vv15. When the memory cells are programmed to state 1, the system tests whether their memory cells have a threshold voltage greater than or equal to Vv1. When the memory cells are programmed to state 2, the system tests whether the memory cells have a threshold voltage greater than or equal to Vv2, and so on.

7 is a timing diagram depicting the behavior of various signals during one of an exemplary read or verification process. Each of the processes of Figure 7 represents a single sensing operation for each unit of memory. If the memory unit is a binary memory unit, the process of Figure 7 can be performed once. If the memory cell is a polymorphic memory cell having four states (eg, 0, 1, 2, and 3), then For each memory unit, the process can be performed (usually in parallel) three times (three sensing operations).

During a read and verify operation, the selected word line (eg, WL2 of FIG. 3) is typically connected to the read reference voltage Vcgr, specifying the level of the read reference voltage for each read and verify operation to determine the associated memory. Whether the threshold voltage of the body unit has reached this level. Raising a selected gate of a selected block to one or more select voltages and raising an unselected word line of the selected block (eg, WL0, WL1, and WL3 of FIG. 3) to a read turn-on voltage Vread (eg, 4.5 volts) causes the transistor to act as a pass gate. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on in response to a voltage applied to the word line. If the measured conduction current is greater than a specific value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the measured conduction current is greater than the specific value, it is assumed that the memory cell is not turned on, and the voltage applied to the word line is not greater than the threshold voltage of the memory cell.

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of the memory cell is measured based on the rate at which the memory cell discharges the dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string including the memory cell to discharge to the bit line. The charge on the bit line is measured after a period of time to see if it has been discharged.

Figure 7 shows signals SGD, WL_unsel, WLn+1, WLn, SGS, selected BL, BLCLAMP, and Source starting at _Vss (about 0 volts). SGD is the gate selection line for the gate selection of the drain side. SGS is the gate selection line for the gate side of the source side. WLn is the word line selected for reading/verification. WLn+1 is an unselected word line adjacent to the drain side word line of WLn. WL_unsel represents an unselected word line except for the adjacent side of the drain side of the word line. The selected BL is a bit line selected for reading/verification. Source is the source line of the memory unit (see Figure 3). BLCLAMP is an analog signal that sets the value of the bit line when it is charged from the sense amplifier.

In FIG. 7, the sensing circuit measures the conduction current of the memory cell by determining whether the bit line has been discharged. At time t1, SGD rises to V _DD (eg, about 3.5 volts), unselected word line (WL_unsel) rises to Vread (eg, about 5.5 volts), and selected word line WLn is in the case of a read operation Raise to Vcgr (eg, V1, V2...V15) or rise to verify level Vcgv (eg, Vv1, Vv2...Vv15) with verify operation, and BLCLAMP rises to precharge voltage to The selected bit line selects the BL precharge (for example, to about 0.7 V). The voltage Vread acts as a turn-on voltage, turning the unselected memory cells on regardless of the physical state or threshold voltage and acting as a turn-on gate. At time t2, BLCLAMP is lowered to _Vss such that the NAND string can control the bit line. Also at time t2, the source side selection gate is turned on by raising SGS to V _DD . This provides a path to dissipate the charge on the bit line. As depicted by signal line 260, if the threshold voltage of the memory cell selected for reading is greater than Vcgr or Vcgv applied to the selected word line WLn, the selected memory cell will not be turned on, and the bit is not turned on. The line will not discharge. As depicted by curve 262, if the threshold voltage of the memory cell selected for reading is lower than Vcgr or Vcgv applied to the selected word line WLn, the memory cell selected for reading will be turned on. (Conductive) and the bit line voltage will be dissipated. At some point after time t2 and before time t3 (as determined by the particular embodiment), the sense amplifier will determine if the bit line has been dissipated a sufficient amount. Between t2 and t3, BLCLAMP(B) is raised to cause the sense amplifier to measure the evaluated BL voltage and then decrease. At time t3, the depicted signal will be reduced to V _SS (or reduced to another value in the case of standby or recovery). Note that in other embodiments, the timing of some of the signals may be changed (eg, the applied signal is offset to a neighbor).

Figure 8 is a flow chart depicting one embodiment of reading data from a non-volatile memory unit. Figure 8 provides a system level read process. At step 300, a request to read the data is received. At step 302, a read operation is performed on a particular page in response to the request to read the data. In one embodiment, when staging a page of data, the system will also create additional bits for the error correction code (ECC) and write them along with the page data to their ECC bits. When reading data from a page, the ECC bits will be used to determine if there are any errors in the data at step 304. This ECC process can be performed by the controller, the state machine, or elsewhere in the system. If there is no error in the data, the data is reported to the user at step 306. If an error is found at step 304, then at step 308 it is determined if the error is correctable. This error can be due to floating gate to floating gate coupling or other reasons. Various ECC methods have the ability to correct a predetermined number of errors in a set of data. If the ECC process can correct the data, the ECC process is used to correct the data at step 310, and the corrected data is reported to the user at step 312. If the data cannot be corrected by the ECC process, then at step 314 Perform data recovery processing. In some embodiments, ECC processing can be performed after step 314. After the data is restored, the data is reported to the host at step 316. When reporting data to the host, the process can be continued by reading additional pages as necessary.

9 depicts a system that can be used to encode and decode data for non-volatile storage, in accordance with an embodiment. Error correction controls are used to detect and correct the reading of erroneous or corrupted data in non-volatile memory arrays. In general, some additional ECC or parity bits are calculated from the input data according to a coding scheme and stored in the memory array. When reading, the input data and ECC bits are read, and the decoder uses the two to detect the presence of an error and, in some cases, to detect which bit(s) the error occurred in.

In an embodiment, the error correction control system of FIG. 9 may be implemented as part of controller 144, although different systems and architectures may be used. The system of FIG. 9 includes an encoder 472, a memory array 474, a log likelihood ratio (LLR) table 476, and a decoder 478. Encoder 472 receives user data (also referred to as information bits) to be stored in memory array 474. These information bits are represented by a matrix i=[10]. Encoder 472 implements an error correction encoding process in which co-located bits are added to the information bits to provide data represented by a matrix or codeword v = [1010] indicating that two co-located bits have been appended to the information Data bit. Other techniques for mapping input data to output data in a more sophisticated manner may be used, such as the techniques discussed below. A low density parity check (LDPC) code (also known as a Gallager code) can be used. In practice, these codes are typically applied to multiple pages encoded across many storage elements. Further information on LDPC can be found in Chapter 47 of "Information Theory, Inference and Learning Algorithms" by D. MacKay, published by Cambridge University Press, 2003. The data bits can then be mapped to a logical page and stored in a non-volatile storage element by stylizing it to a stylized state corresponding to v (eg, X=12). In the volatile reservoir 474. In the case of the four-bit data matrix v, 16 stylized states can be used. Typically, no parity bits are used for each individual unit.

In a possible embodiment, a repetitive probability decoding method is implemented that implements error correction decoding corresponding to the encoding implemented at encoder 472. More details on the repetitive probability decoding can be found in the original D. MacKay text above. The inverse probability decoding attempts to decode the codeword by assigning an initial probability metric to each bit in a codeword. These probability metrics indicate the reliability of each bit, that is, the likelihood that there is no error in the bit. In one method, the probability metrics are the log likelihood ratio LLRs obtained from the LLR table 476. The LLR value is a measure by which the reliability of the values of the bins read from the storage element is known.

One yuan LLR by Given that P(v=0∣Y) is the probability that a bit is 0 under the condition that the read state is Y, and P(v=1∣Y) is the condition that the read state is Y. The next one is a chance of 1. Therefore, LLR>0 indicates that a bit is more likely to be 0 instead of 1, and LLR<0 indicates that a bit is more likely to be 1 instead of 0 to satisfy one or more parity checks of the error correction code. In addition, a larger magnitude indicates a greater probability or reliability. Therefore, the bit of LLR=63 is more likely to be 0 than the bit of LLR=5, and the bit of LLR=-63 is more likely to be 1 than the bit of LLR=-5. LLR=0 indicates that the probability that the bit is 0 or is equal is equal.

An LLR value can be provided for each of the four bit positions in codeword y1. For example, LLRs of 4.5, 5.2, -5.9, and 6.6 are assigned to bits 0, 0, 1, and 0 of y1, respectively. In addition, the LLR table can take into account multiple read results such that LLRs with larger magnitudes are used when bit values are consistent across different codewords.

The decoder 478 receives the codewords y1 and LLR. As explained below (see, for example, Figures 11 and 12), decoder 478 repeats in successive iterations, where it determines if the parity check of the error encoding process has been satisfied. If all parity checks have been met, the decoding process has converged and the codeword has been incorrectly corrected. If one or more parity checks have not been met, the decoder will adjust the LLR of one or more of the bits that are inconsistent with the parity check, and then reapply the peer check or the next check in the process to determine if it has Satisfy. For example, the magnitude and/or polarity of the LLR can be adjusted. If the co-location check is still not met, the LLR can be adjusted again in another iteration. In some but not all cases, adjusting the LLR may result in the inversion of the bit (eg, from 0 to 1 or from 1 to 0). In an embodiment, another parity check is applied to the codeword as soon as practicable once the parity check has been satisfied. In other cases, the process moves to the next parity check and returns to the failed check later. The process continues to attempt to satisfy all co-location checks. Therefore, the decoding process of y1 is completed to obtain decoded information including the parity bit v and the decoded information bit i.

Figure 10 is a diagram of each bit position of the different states of the device as illustrated in Figure 6. The initial LLR value table (where M3 > M2 > M1). A positive LLR value indicates a logical zero of the corresponding bit, and a negative LLR indicates a logical one of the corresponding bit. A larger magnitude indicates a greater reliability or probability that the bit is in a logical state. For example, the lower bits in states 0 through 5 have LLR = -M3, indicating that these bits have a high probability of being one. The situation can be seen visually from Figure 6, because the probability of reading a cell in state Y1 is small, the cell is actually in a stylized state that is far from enough to change the bit from 0 to 1. Therefore, the LLR of the lower bit in state 5 is -M3 (higher correct probability) because the read state must deviate from the stylized state by at least three states, for example, state 8 (where the lower bit is 0 instead of 1). However, the LLR of the lower bit in state 6 is -M2 (intermediate correct probability) because the read state will have to deviate from the two states for the bit that will be in error. Similarly, the LLR of the lower bit in state 7 is -M1 (lower correct probability) because the read state will have to deviate from only one state for the bit that will be in error. Similar reasoning applies to other bit positions. For example, the LLR of the top bit indicates a relatively low probability of correctness, since only one state error will result in the bit being incorrect.

Figure 11 depicts a sparse parity check matrix. As mentioned previously, the memory stores data representing information bits and parity bits (or ECC bits), wherein the parity bits are provided in accordance with error correction coding processing. This process involves adding a parity bit to the information bit. In one possible approach, a low density parity check (LDPC) code can be used. In practice, these codes are typically applied to a plurality of codewords that are encoded across a plurality of storage elements (ie, not each unit stores parity bits, and inspections are distributed across multiple units). LDPC The code is ideal because it incurs a relatively low cost of indirect connection. In addition, the LDPC code exhibits the performance of the Shannon limit under the repeated message passing decoding algorithm. However, this is merely an example embodiment as any type of error correction code can be used. For example, other linear block codes can be used.

The LDPC code is a linear block code that is characterized by a sparse parity check matrix, for example as depicted by matrix 520. The matrix includes K information bits and M co-located bits, and the code length is N=K+M. Additionally, the equivalent bit is defined such that M parity check equations are satisfied, wherein each column of the matrix represents a parity check equation. In particular, the matrix is identified by check nodes cn1 through cn10, and the rows are identified by variables v1 through v13, which indicate the data stored in the storage element, for example, codeword bits. Based on the following equation, this information includes the information bit i and the parity bit p: Where H is a sparse parity check matrix, v is a data matrix, i is an information bit matrix, and p is a parity matrix. The data matrix v can be determined by solving the above equation. In addition, if the matrix H is a lower triangular matrix, this solution can be efficiently performed using a Gaussian elimination procedure.

Figure 12 depicts a sparse diffractogram corresponding to the sparse parity check matrix of Figure 11. Graph 530 indicates in more detail how the LDPC code operates. The variable nodes v1 to v13 represent codeword bits, and the check nodes cn1 to cn10 represent the parity check constraint for the equal bits.

During decoding, the decoder attempts to satisfy the parity check. In this example, there are ten parity checks, as indicated by check nodes cn1 through cn10. For the sake of simplicity, the following discussion is provided with respect to binary bits, which may take the value 0 or 1. For practical embodiments, the bits may be LLR values, where a positive LLR represents a binary one and a negative LLR represents a binary zero. Furthermore, "soft XOR" can be used in embodiments instead of using typical XOR logic operations. A soft XOR operation is performed on the analog LLR value and a type of ratio is returned. If the positive LLR value is reduced to binary 0 and the negative LLR value is reduced to binary 1, the soft XOR operation on the LLR value is simplified to a logical XOR operation on the binary bit.

The first parity check at cn1 determines whether v2 V4 V11 V13=0, where Represents a mutually exclusive or (XOR) logical operation. This check is satisfied if there are even "1" bits in v2, v4, v11, and v13. This check is represented by the fact that the arrows from nodes v2, v4, v11, and v13 point to node cn1 in chart 1300. The second parity check at cn2 determines whether v1 V7 V12=0, if there are an odd number of "1" bits, the check is satisfied. The third parity check at cn3 determines whether v3 V5 V6 V9 V10=0, if there are an odd number of "1" bits, the check is satisfied. Similarly, the fourth parity check at cn4 determines whether v2 V8 V11=0, the fifth check at cn5 determines whether v4 V7 V12=0, the sixth parity check at cn6 determines whether v1 V5 V6 V9=0, the seventh parity check at cn7 determines whether v2 V8 V10 V13=0, the eighth parity check at cn8 determines whether v4 V7 V11 V12=0, the ninth parity check at cn9 determines whether v1 V3 V5 V13=0, and the tenth parity check at cn10 determines whether v7 V8 V9 V10=0.

The decoding method for LDPC is a repetitive probability decoding method called repeated message delivery decoding. Repeating involves continuously traversing the inspection node and updating the LLR values of the bits involved based on each parity check. In one method, an attempt is made to satisfy the first parity check of cn1. Once the peer check is satisfied, an attempt is made to satisfy the first parity check of cn2, and so on. In another embodiment, after the attempt at cn1 is unsuccessful, the process moves to cn2 and returns to cn1. If necessary, adjust the LLR value for each iteration in a manner known to those skilled in the art. This repeated algorithm is in the form of one of belief propagation.

To improve the convergence time, high order bit level information can be obtained from the memory unit during the error correction control process. This additional information may be referred to as a "soft bit" and the corresponding operation is referred to as a soft bit read operation at the soft bit comparison point. The "soft bit" is collected by reading the memory unit at the adjusted comparison level to provide more data than can be used by the correction engine to speed up or otherwise contribute to the convergence process. For example, in one embodiment, each of the comparison points used during a normal "hard" read operation may be incremented by 0.5 V to provide a soft bit comparison level. By reading at the soft bit comparison level, more data can be used for error correction control processing, which improves convergence performance.

Figure 13 illustrates the use of soft data bits in accordance with an embodiment as part of error correction control processing. The states 6, 7, and 8 of the 16-state device shown in Figure 6 are shown. For the sake of clarity, only a portion of the total threshold voltage distribution is depicted. The normal or "hard bit" read comparison points V6, V7, V8, and V9 are depicted along with various soft bit read comparison levels. By reading the level in the first set of soft bits Reads are performed under Sa6, Sa7, and Sa8 to determine the first soft bit of each cell. These comparison points bisect their corresponding threshold distributions. These bisectors may appear exactly at the peak of the distribution, but may not be the case for different memory devices. In other embodiments, the read levels can be placed at different locations. Similar reference levels will also be provided in each of the other states shown in FIG. The read operation is performed using the information of the report to the controller that is used to adjust the comparison level and to be used as part of the error correction control process.

The first soft bit divides each threshold voltage distribution into two parts to further divide the information known to each unit. The soft bit increases the resolution by which the state of the memory cell is known by specifying that any individual memory cell may be in distribution. For example, the state 6 can be used to report the unit that is conducting at the soft bit read level Sa7 instead of Sa6 to the controller. If the unit was previously read in state 6, the controller can determine that it is in the upper half of the voltage distribution of state 6.

The second soft bit of each cell is determined by reading at a second set of read levels. Figure 13 depicts second soft bit levels Sb6L, Sb6H, Sb7L, Sb7H, Sb8L, and Sb8H. The second soft bit level is between the first soft bit level and the hard bit comparison level. The low level of the second soft bit (eg, Sb6L) is between the first soft bit compare level (eg, Sa6) and the corresponding hard compare level (eg, V6). The higher level is between the first soft bit level and the hard comparison level. Similar reference levels will also be provided in each of the other states shown in FIG. The read operation is performed using the information of each of the adjusted comparison levels and the report to the controller to be used for the correction control.

The second soft bit under each state level is divided into two partial soft bits. As illustrated in Figure 6, there are two comparison points for each state of the second soft bit. The first subset of soft bits are determined using a first subset of comparison levels (each state includes one quasi) and a second subset of comparison levels (each state includes one quasi) to determine the second soft bit yuan. Because the memory array can be configured to read at four-bit resolution, the comparison points of the two subsets are applied at different time intervals. In a device using 16 states, data can be read from each cell at four-bit resolution. In most cases, data is provided between the memory array and the controller at this resolution. For example, the host can issue a request for one or more pages to the controller. The memory array can provide one page of data to the controller at a time while reading the next request page. To accommodate reading at two comparison levels for each state of the second soft bit, the comparison level is divided into two subsets. For example, the first subset can include low comparison levels (eg, Sb6L, Sb7L, etc.), and the second subset can include higher comparison levels (eg, Sb6H, Sb7H, etc.). The memory can be read at the first set of levels and reported to the controller at four-bit resolution, and then read at the second set of levels and report the data at four-bit resolution To the controller. The controller can use the data from the two subsets of the second soft bit level to divide the state determination of each memory cell to be within a quartile of the state. This information can be used with information from the hard comparison level and the first soft bit to provide a high level of resolution.

An initial LLR value table with the first soft bit data is depicted in FIG. Figure 14 includes only the portions of the table corresponding to states 6, 7, and 8 shown in Figure 13. The complete table of 16-state devices will include two rows for each state. The first soft bit LLR table includes entries that are twice as large as those accessed after the hard bit is read. An entry for the LLR value table. A read determination is made at a first soft bit comparison level relative to a threshold voltage of each memory cell of the adjusted comparison point. By combining the data read from the hard bit with the data read from the first soft data bit, the controller can determine which half of the corresponding state distribution the memory cell is in.

The table includes two rows for each state, each row representing one and a half of the corresponding distribution. For example, row 6(0) corresponds to the memory cells in the lower half of the state 6 distribution, and row 6(1) corresponds to the memory cells in the upper half of the state 6 distribution. . Similarly, row 7(0) corresponds to the memory cells in the lower half of the state 7 distribution, and row 7(1) corresponds to the memory cells in the upper half of the state 7 distribution, 8(0) corresponds to their memory cells in the lower half of the state 8 distribution, and row 8(1) corresponds to their memory cells in the upper half of the state 8 distribution. Each row includes an LLR value, which in this embodiment is shown as an adjustment to the LLR value of the hard bit LLR value from FIG. The LLR value in each row reflects the certainty of the increase or decrease in the value of the bit based on additional information from the first soft bit. In other embodiments, the LLR values may be defined in different aspects, such as in absolute measurements rather than adjustments to hard bit data LLR values.

An initial LLR value table with the second soft bit data is depicted in FIG. Again, for clarity purposes, the table includes only portions of the table that correspond to states 6, 7, and 8 shown in FIG. In addition, the table lists only the adjustments made to the LLR values depicted in Figure 10 to save space in the table. As is the case with the values in Figure 14, it is possible to define new LLR values in different ways, such as in absolute values rather than adjustments to hard data LLR values. 16 The complete table of state devices will include four rows for each state. The second soft bit table includes four rows for each state, each row representing a quarter of the corresponding distribution of the states. For example, row 6 (00) represents the memory cells in the lowest quarter of the state 6 distribution, and 6 (01) represents the memory in the lower quarter of the state 6 distribution. Body unit, row 6 (10) represents the memory cells in the second quarter of the state 6 distribution, and row 6 (11) represents the memory in the top quarter of the state 6 distribution. unit. Similar rows are provided for states 7 and 8, using the symbols 00, 01, 10, 11 to identify cells in the lowest, second, second, and upper quartile regions of the respective distribution.

According to an embodiment, an additional LLR table is provided for repeatedly decoding based on data from the first portion of the soft bits of the second soft bit operation prior to receiving the second portion of the soft bit data of the second soft bit. In this manner, additional information from the first subset of the comparison levels of the second soft bit can be applied prior to completion of the reading of the second subset of comparison bits. In some cases, the decoding process may converge before the second portion of the soft bit reading is completed, thus reducing the total time of reading.

An initial LLR value table for data from a first subset of second soft bit comparison levels in accordance with an embodiment is depicted in FIG. The portion of the table corresponding to states 6, 7, and 8 shown in Fig. 6 is again depicted. The complete table of 16-state devices will include rows corresponding to each state (3 rows per state). Again, the LLR values are described relative to the hard bit LLR values, but may be defined in different ways, such as by non-correlated numbers, and the like.

Separating the set of comparison levels for the second soft bit read as described above The two groups were adapted to read at two comparison levels in each state. This enables the memory to operate under normal reading conditions, thereby transferring four data bits per cell between the memory and the controller. Of course, other embodiments, such as embodiments having different numbers of states, may require different numbers of comparison levels. An example was described earlier in which the first subset of reads is performed at a low comparison level followed by a second subset executed at a high comparison level. In Figure 16, the low and high levels are selected based on the characteristics of each individual state. In other embodiments, the divisions described earlier may also be used. The first subset of comparison levels for the second soft bit read includes Sb6L of state 6, Sb7H of state 7, and Sb8L of state 8. The second subset includes Sb6H, Sb7L, and Sb8H. In this example, the first subset of levels may include low levels because their state distributions are determined to drift in the negative threshold voltage direction and state 7 is determined to drift in the positive direction. According to various embodiments, any number and any type of partitioning of the comparison level of the second soft bit may be used. It should be noted that the disclosed principles can be extended to higher levels of soft bit reading.

For state 6, row 6 (00) corresponds to the cell in the lowest quarter of the threshold voltage range of state 6. Row 6 (01) corresponds to the cell in the lower quarter, and row 6 (1) corresponds to all cells in the upper half of the threshold voltage range of state 6. An individual row corresponding to a quarter of the upper half of the threshold voltage distribution of state 6 is not provided. The second portion of the soft bit operation will be used to perform the Sb6H level that provides a distinction for the information. For state 7, row 7 (0) corresponds to all cells in the lower half of the threshold distribution of state 7, and row 7 (01) corresponds to a quarter of the lower half of the state 7 distribution. unit, And row 7 (11) corresponds to the cell in the uppermost quarter of the state 7 distribution. Individual rows are not provided for a quarter of the state 7 distribution because the Sb7H comparison level is applied to the first subset. For state 8, row 8 (00) corresponds to the cell in the lowest quarter of the threshold voltage range of state 8. Row 8 (01) corresponds to the cell in the lower quarter, and row 8 (1) corresponds to all cells in the upper half of the threshold voltage range of state 8. An individual row corresponding to a quarter of the upper half of the threshold voltage distribution of state 8 is not provided because the read operation at Vb8H has not been performed.

The LLR values in the table of Figure 16 are based on additional information gathered from the first portion of the soft bits of the second soft bit read operation to indicate the reliability of the increase or decrease with respect to individual bits of a cell. For example, the LLR value of the top bit in row 6 (00) is M1 + 7 instead of M1 + 5 provided for row 6 (0) in the first soft bit LLR table. If a cell is determined to be in the lower portion of the lower half of the state 6 distribution, the top bit can be considered more reliable because the neighboring state in the other direction has the same logical value for the top bit. The LLR value of the top bit in row 6 (01) is M1 + 5, which is the same value provided for row 6 (0) in the first soft bit table. This indication has no more reliability with respect to the value of the top bit. However, in another embodiment, based on re-reading the unit in state 6, for example, the LLR value may be increased (eg, to M1+6) by the first soft bit value of row 6(0) to indicate Increased reliability. In an embodiment, based on being in the middle of the lower half, the LLR value may be reduced as needed to indicate reduced reliability.

17A and 17B depict a flow chart describing a method for reading a non-volatile storage, in accordance with an embodiment. The reading technique includes as an error The part of the correction control process is repeatedly decoded using the LLR value. The first initial LLR value table is used to decode the data based on the reading at the hard comparison level. The first and second soft bit data are also read from the memory to improve convergence. The second initial LLR value table is used to decode the data based on the readings at the hard comparison level and the first soft bit level. The third initial LLR value table is used to decode the data based on the readings under the first subset of the hard comparison level, the first soft bit level, and the second soft bit comparison level. Using a fourth initial LLR value table to base a second subset of the first subset of the hard comparison level, the first soft bit level, the second soft bit comparison level, and the second soft bit comparison level Read it to decode the data.

At step 500, a hard read compare level is used to distinguish one or more pages of data from the memory array by the plurality of states that the unit can be programmed to. Other data units can be read in accordance with the disclosed principles. By way of example, a page of data may include each of four bits from each of a group of cells. Other examples of pages may include a particular bit from each of a group of cells. For example, the cells can be grouped according to the word line or by the type of word line or word line. Depending on the nature of the operations performed at step 500 and the coding scheme employed, various hard comparison levels can be applied. For example, reading each bit from a cell may have to apply each comparison level, while reading a lower bit may only be achieved by applying V8 to compare the levels. At step 502, the data of the read unit is provided from the memory chip to the controller. For example, in one embodiment, a continuous page of material is provided. At step 504, the data is decoded based on the encoding technique used in writing the data. For example, step 504 can include performing one or more co-locations on the data. an examination. If no error is detected at step 506, the read operation is completed at step 508. However, if one or more errors are detected, then at step 510, error correction is performed on the erroneous data. Error correction can be performed on various portions of the material read in step 500. Depending on the level of error in the correction scheme, the data of different sizes can be subjected to repeated probability decoding.

At step 510, an initial probability metric is assigned to each of the bits in each data unit in which the error was detected. For example, a metric can be assigned to each bit in many error correction pages with detected errors. In an embodiment, the metric assigned to each bit is the initial LLR value determined from the first LLR table. At step 512, the repeated decoding of the data begins. The parity at the first inspection node can be evaluated, and if the parity is not satisfied, the initial LLR value is adjusted. If necessary, the process can continue to the second inspection node and perform a parity check. As described earlier, during the repetitive processing that results in co-location, the co-location of the selected bit eventually changes. As long as an error is detected in at least one of the data units in step 514, and it is determined at step 516 that the counter i does not exceed the maximum number of repetitions DC_max, then the repeat decoding process continues at step 512. If all errors are corrected, the read operation is completed at step 508.

If all errors are not corrected at the end, then the first soft bit read operation begins at step 518. The first soft bit read can apply a set of adjusted compare levels to provide higher resolution decoding of the data. For example, as shown in FIG. 6, a single read comparison point that bisects the corresponding threshold voltage distribution for that state can be applied for each state. While reading the first soft bit, continue to be based on The initial LLR value is used to repeatedly decode the data. This is indicated by the inspection at 520.

Upon completion of reading the first soft bit at step 520, the data is received at the controller at step 522. The newly received data can be used with the data received during the hard read operation to double the resolution of the threshold voltage by which the unit is known. For example, the controller can determine which half of the distribution a cell is in when the soft bit read system is executing at the midpoint of the distribution. Using the data collected from the hard and soft data, the controller can assign a new initial LLR value to each bit in the data unit containing the error. In an embodiment, step 524 includes accessing a second initial LLR value table. This table may include entries that are twice the first table to provide LLR values that depend not only on the state of the cell, but also on which half of the distribution of the cell the cell is in.

In Figure 17B, at step 526, the data is repeatedly decoded using the new starting LLR value. As described earlier, the LLR values can be adjusted repeatedly based on one or more inspection nodes or parity checks. If the erroneous data is corrected, the operation is completed at step 528. As long as the error persists and the counter i is below the maximum number of repetitions DC_max, the repeated decoding process continues, attempting to reach parity at each of the inspection nodes. The maximum number of repetitions DC_max permitted at step 532 may or may not be the same as the maximum number of repetitions used at step 516. In addition, the counter can be reset after starting the first soft bit reading.

When the maximum number of repetitions is reached, the reading at the first partial soft bit comparison level begins at step 536. As described earlier, the second soft bit operation provides twice the resolution of the first soft bit and the hard level read. degree. Use two comparison points for each state. The comparison levels are divided into two subsets to provide data from the wafer to the controller in two separate units. While performing the reading under the first subset of the comparison levels, the repeated decoding process based on the hard comparison level and the first soft bit comparison level continues (step 526), hoping that the process will be acquiring the second The soft bit data converges before. If all errors have not been corrected and the first subset of reads of the second soft bit is complete, then at step 538 the controller receives data from the first subset of the second soft bits. In the embodiment of Figures 13A-13B, after receiving the data of the first subset of levels, reading at a second subset of the levels of the second soft bits begins at step 540. In other embodiments, a number of iterations of decoding may be performed after the first subset of data is received, prior to reading at the second subset of levels.

At step 542, an initial probability metric is assigned to each of the pages containing the error based on the first subset of the hard comparison level data, the first soft comparison level data, and the second soft bit comparison level data. yuan. At step 544, the reverse decoding process begins again. At step 546, one or more error checks are performed. If no error is detected, then at step 548 the read operation is completed. If the error persists and the second subset of reads of the second soft read operation has not been completed, then at step 544 the repeat decoding process continues. Once the reading under the second subset of the second soft bit level is complete, the data from the second subset of reads is received at the controller at step 552. At step 554, the initial probability metric is again assigned to each bit in the data unit containing the error. The metric assigned at step 554 is based on two subsets from the hard comparison level read, the first soft bit data, and the second soft bit data. data of. For example, an embodiment includes accessing an initial LLR value table for each potential state including for each bit location based on four different quartiles of a threshold voltage distribution in which a cell may be located Four initial LLR values. In an embodiment, a table such as the one described in FIG. 15 is accessed to determine an initial LLR value for decoding user data.

At step 556, a repeated decoding of the user data based on the new initial LLR value is initiated. The values are adjusted as the decoding process continues, and some of the bit positions eventually transition to the same position. If it is determined at step 558 that all errors have been corrected, then at step 560 the read operation is completed. If all errors have not been corrected and it is determined at step 562 that the maximum number of repetitions has been performed, then at step 564 it is determined that the read failed.

18 and 19 depict smart packets for comparison levels of the first and second subsets of the second soft bit read operation. Figure 18 again depicts the threshold voltage distribution of the programmed memory cells of one of the four data bits. In Figure 18, the initial threshold distribution that existed immediately after the data was programmed into the memory unit is illustrated by the solid line. The dashed lines illustrate the same group of memory cells after a lapse of time. As illustrated, the threshold voltages of some of the memory cells have shifted over time, shifting the distribution of threshold voltages for each memory state. As described, this offset of the threshold voltage can result in a read error that necessitates the use of error correction control. For example, it can be seen that the memory cell at the edge below the state 15 distribution (distribution after the elapsed time period) has a threshold voltage at state 15 hard read comparison level V15. It can be seen that each state distribution widens due to the threshold voltage shifting with time. Looking closely at Figure 18, it can be further seen that states 0 through 4 each demonstrate Portions of the cell have a tendency to have a threshold voltage that is offset over time. On the other hand, states 7 through 15 tend to exhibit a negative offset of the threshold voltage over time. By adjusting the first and second portions of the second soft bit reading based on this information, improved convergence performance can be obtained.

When reading in states that tend to drift in the positive threshold voltage direction over time, it is more likely to provide useful information about the greater resolution of the cell position on the upper end of the distribution within the state. When reading in states that tend to drift in the negative threshold voltage direction over time, it is more likely to provide useful information about the greater resolution of the cell position at the lower end of the distribution within the state. The first subset of comparison levels may include low comparison levels for those states that tend to drift in the negative threshold voltage direction. The first subset may further include a higher comparison level for the second soft bit read for states that tend to drift in the positive threshold voltage direction. The higher level of the second soft bit is included in the second set of sub-reads for those states that tend to drift in the negative threshold voltage direction, and includes the second soft for those states that tend to drift in the positive direction. The low level of the bit.

19 is a table of an exemplary segmentation of a subset of comparison levels of a second soft bit read operation. The segmentation is based on the distribution depicted in Figure 18. Each of the states in Figure 19 is listed at the top of the line. Each column corresponds to a different operation performed as part of the reading process. The first column states the hard read comparison level for each state. These comparison levels are used to sense the state of the selected memory unit during the normal read process. State 1 includes the V1 reference level, State 2 includes the V2 reference level, and so on. The second column states the comparison level for the first soft bit operation. These comparison levels are selected to be at the peak level The corresponding distribution is equally divided to divide the distribution into two parts. State 1 includes the Sa1 reference level, State 2 includes the Sa2 reference level, and so on. The third column states the first subset of the comparison levels of the second soft bit operation. States 0 to 4 include higher read comparison levels Sb0H, Sb1H, Sb2H, Sb3H, Sb4H, and states 5 to 15 include low read comparison levels Sb5H, Sb6H, Sb7H, Sb8L, Sb9L, Sb10L, Sb11L, Sb12L, Sb13L, Sb14L, Sb15L. The fourth column states the second subset of the comparison levels of the second soft bit operation. States 0 to 4 include low read comparison levels Sb0L, Sb1L, Sb2L, Sb3L, Sb4L, and states 5 to 15 include higher read comparison levels Sb5L, Sb6L, Sb7L, Sb8H, Sb9H, Sb10H, Sb11H, Sb12H, Sb13H, Sb14H and Sb15H. This configuration of comparison levels in the subsets provides improved performance by first extracting from the second soft-bit read operation and using the most useful information. In many cases, it can be expected that information from the first subset of comparison levels will be sufficient to achieve convergence.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen to best explain the principles of the invention and the application of the invention, . It is intended that the scope of the invention be defined by the scope of the appended claims.

10‧‧‧Optoelectronics

10CG‧‧‧Control gate

10FG‧‧‧Floating gate

12‧‧‧First choice gate/transistor

12CG‧‧‧Control gate

12FG‧‧‧ Floating Gate

14‧‧‧Optoelectronics

14CG‧‧‧Control gate

14FG‧‧‧Floating gate

16‧‧‧Optoelectronics

16CG‧‧‧Control gate

16FG‧‧‧Floating gate

20CG‧‧‧Control gate

22‧‧‧Second selection gate

22CG‧‧‧Control gate

26‧‧‧ bit line

28‧‧‧ bit line

30‧‧‧NAND strings

100‧‧‧Memory Cell Array

110‧‧‧ memory devices

112‧‧‧Memory dies/wafers

120‧‧‧Control circuit

122‧‧‧ state machine

124‧‧‧ on-chip address decoder

126‧‧‧Power Control Module

130A‧‧‧Read/Write Circuit

130B‧‧‧Read/Write Circuit

132‧‧‧ line

134‧‧‧ line

140A‧‧‧ column decoder

140B‧‧‧ column decoder

142A‧‧ ‧ decoder

142B‧‧‧ row decoder

144‧‧‧ Controller

200‧‧‧Sensing block

210‧‧‧Sense Module

212‧‧‧ bit line latch

214‧‧‧Sensor circuit

216‧‧‧ data bus

220‧‧‧Common part

222‧‧‧ processor

224‧‧‧data latch

226‧‧‧I/O interface

228‧‧‧Input line

230‧‧‧ data bus

260‧‧‧ signal line

262‧‧‧ Curve

472‧‧‧Encoder

474‧‧‧Memory array

476‧‧‧ Log Likelihood Ratio (LLR) Table

478‧‧‧Decoder

520‧‧‧Matrix

530‧‧‧ Chart

BLCLAMP‧‧‧ signal

Ble‧‧‧ even bit line

Blo‧‧‧ odd bit line

Cn1-cn10‧‧‧Check node

C-source‧‧‧Common source line

Sa6‧‧‧Soft bit read level

Sa7‧‧‧Soft bit read level

Sa8‧‧‧Soft bit read level

Sb6H‧‧‧ second soft bit level

Sb6L‧‧‧ second soft bit level

Sb7H‧‧‧ second soft bit level

Sb7L‧‧‧ second soft bit level

Sb8H‧‧‧ second soft bit level

Sb8L‧‧‧ second soft bit level

SGD‧‧‧Selected gate bungee line

SGS‧‧‧Selected gate source line

Source‧‧‧Source line

V1-v13‧‧‧Variable node

V1-V15‧‧‧Read comparison point

Vcgr‧‧‧Read reference voltage

Vcgv‧‧‧ verification level

Vread‧‧‧ read turn-on voltage

Vv1-Vv15‧‧‧Verification comparison point

WL0-WL3‧‧‧ word line

WL-unsel‧‧‧Unselected word line

1 is a top plan view of an exemplary NAND string.

2 is an equivalent circuit diagram of the NAND string of FIG. 1.

3 is a block diagram of an exemplary array of NAND flash memory elements.

4 is a block diagram of a non-volatile memory system in accordance with an embodiment.

Figure 5 is a block diagram of a sensing block in accordance with an embodiment.

6 is a graph depicting an exemplary distribution of threshold voltages for a group of memory cells, each memory cell storing four data bits.

Figure 7 is a timing diagram illustrating the behavior of certain signals during a read/verify operation.

Figure 8 is a flow chart depicting one embodiment of a process for reading non-volatile memory.

9 is a block diagram of an error correction control system in accordance with an embodiment.

10 is a table providing exemplary initial LLR values for each bit or data unit of a codeword based on a hard read result.

Figure 11 depicts an exemplary sparse parity check matrix.

Figure 12 depicts a sparse diffractogram corresponding to the sparse parity check matrix of Figure 11.

Figure 13 is a graph of a portion of the threshold voltage distribution of Figure 6, illustrating the soft bit comparison level.

14 is a table providing exemplary initial LLR values for each bit or data unit of a codeword based on a hard read result and a first soft bit read result.

15 is a table providing exemplary initial LLR values for each bit or data unit of a codeword based on a hard read result, a first soft bit read result, and a second soft bit read result.

16 is an exemplary initial LLR for each bit or data unit of a codeword based on a hard read result, a first soft bit read result, and a first soft bit read result of the second soft bit read. A table of values.

17A-17B contain flowcharts depicting the process of providing error correction control, including acting on a portion of the soft bit data.

Figure 18 is a graph of an exemplary distribution of threshold voltages for a four bit memory system, including representations of the distribution after a threshold voltage shift.

19 is a table containing exemplary wisdom partitioning of a first subset and a second subset of read comparison levels for a second soft bit operation.

(no component symbol description)

Claims (15)

A method of reading a non-volatile memory, comprising: reading user data from a set of non-volatile storage elements using a first plurality of read comparison points, each comparison point corresponding to one of the storage elements a stylized state; using a second plurality of read comparison points having a greater number of read comparison points than the first plurality of read comparison points to be from the group at a higher bit resolution than the user data The storage element reads a set of soft data; and uses the first subset of the set of soft data to decode the user data while reading to determine a second subset of the set of soft data. The method of claim 1, further comprising: decoding the user data without the set of soft data before reading the set of soft materials from the set of storage elements; wherein reading the set of soft data is in response to Executed without a decision of the unsuccessful decoding in the case of the soft data. The method of claim 2, further comprising: decoding the user using the first subset of the set of soft data and the second subset after reading to determine the second subset of the set of soft data data. The method of claim 3, wherein: reading is performed to determine that the second subset of soft data is executed in response to determining that one of the first subset is unsuccessful in decoding. The method of claim 3, wherein: the soft data of the group is a second set of soft materials; The method further includes: reading a first set of soft data from the set of storage elements using the third plurality of read compare points before reading the second set of soft data, and decoding the user using the first set of soft data And performing a reading of the second set of soft data in response to determining that one of the decoding of the first set of soft data is unsuccessful. The method of claim 5, wherein: decoding the user profile without the first set of soft data comprises accessing a first reliability metric table; and decoding the user profile using the first set of soft data comprises storing Taking a second reliability metric table; using the first subset of the second set of soft data to decode the user data comprises accessing a third reliability metric table; using the first of the second set of soft data The subset and the second subset to decode the user profile includes accessing a fourth reliability metric table. The method of claim 1, wherein: the second plurality of read comparison points includes a first subset of one of the read comparison points for determining the first subset of the data and for using the first subset Determining a second subset of the read comparison points of the second subset of data; the first subset of the read comparison points includes one or more associated with a threshold voltage portion of one of the respective programmable states Reading a comparison point and one or more read comparison points associated with a threshold voltage portion of one of its corresponding stylizable states; reading the second subset of comparison points includes a corresponding stylable state thereof One or more read compare points associated with the threshold voltage portion and one or more read compare points associated with the threshold voltage portion of one of the respective programmable states. The method of claim 1, wherein: the second plurality of read comparison points includes a first subset of one of the read comparison points for determining the first subset of the data and for using the first subset Determining a second subset of the read comparison points of the second subset of data; each read comparison point of the first subset is associated with a threshold voltage portion of one of the respective programmable states; and the Each read compare point in the two subsets is associated with a threshold voltage portion of one of its corresponding stylizable states. A non-volatile memory system comprising: a plurality of non-volatile storage elements; and a management circuit in communication with the plurality of non-volatile storage elements, the management circuit performing one or more operations, the one or more operations The method includes: providing a set of read comparison points for the plurality of non-volatile storage elements as part of an error correction control process while reading a first set of data from the storage elements, the set of read comparison points including a first subset of read comparison points having a read compare point corresponding to each of the programmable states of the storage elements and having a readout corresponding to each of the programmable elements Comparing a second subset of the comparison point of the comparison point, wherein providing includes providing the first subset prior to the second subset, determining a second group based on the first subset of the read comparison points And using the second set of data to repeatedly decode the first set of data while providing the second subset of read comparison points for the plurality of non-volatile storage elements. The non-volatile memory system of claim 9, wherein the one or more read operations further comprise: determining a third set of data based on the second subset of read comparison points; and using the third set of data And the second set of data to repeatedly decode the first set of data. The non-volatile memory system of claim 10, wherein the set of read comparison points is a second set of read comparison points, the one or more operations further comprising: before providing the second set of read comparison points The plurality of non-volatile storage elements provide a first set of read comparison points; and determining the first set of data based on the first set of read comparison points. The non-volatile memory system of claim 11, wherein the one or more operations further comprises: providing each of the programmable elements corresponding to the storage elements prior to providing the second set of read comparison points a third set of read points of the single read comparison point of the state; determining a fourth set of data based on the third set of read comparison points; providing the first subset of the read comparison points to the storage The component simultaneously decodes the first set of data based on the fourth set of data. The non-volatile memory system of claim 11, wherein the one or more operations further comprise: The first set of data is repeatedly decoded prior to providing the second set of read comparison points; wherein the providing the second set of read comparison points is performed in response to one of determining that the first set of data was unsuccessful. The non-volatile memory system of claim 9, wherein: repeatedly decoding the first set of data using the second set of data comprises accessing a reliability metric based on the first set of data and the second set of data. A non-volatile memory system as claimed in claim 14, wherein: the reliability metrics comprise a log likelihood ratio.