TWI388043B - Circuit board and method thereof - Google Patents

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board having a recess and a method of fabricating the same.

Due to the market demand for electronic products that are light, thin, and portable, the assembly thickness of electronic components and circuit boards in electronic products will be toward a thinner direction.

The conventional technique reduces the assembly thickness of the electronic component and the wiring board by forming a recess in the wiring board and disposing an electronic component such as a chip package structure in the recess. 1 is a cross-sectional view of a conventional circuit board. Referring to FIG. 1 , the circuit board 100 has a core layer 110 and a line structure 120 and a line structure 130 respectively disposed on the upper and lower sides of the core layer 110. The core layer 110 has a core dielectric layer 112 and is respectively disposed on the core layer. Two circuit layers 114, 116 on the upper and lower sides of the electrical layer 112. The recess R1 extends through the wiring structure 120 and the core dielectric layer 112 and exposes the wiring layer 116.

Since the process of the conventional circuit board 100 is layered from the upper and lower sides of the core layer 110 to form the line structure 120 and the line structure 130, then part of the line structure 120 and part of the core dielectric layer 112 are removed. The circuit layer 116 is exposed. Therefore, the wiring layer 116 is buried in the dielectric layer 132 of the wiring structure 130.

The present invention provides a wiring board having two core layers stacked on each other.

The invention provides a method for manufacturing a circuit board, which can produce a circuit board having two core layers stacked on each other.

The invention provides a circuit board having a recess, the circuit board comprising a first core layer, a second core layer and a central dielectric layer. The first core layer includes a core dielectric layer and a core circuit layer, and the core circuit layer is disposed on the core dielectric layer. The second core layer is disposed on the first core layer. The central dielectric layer is disposed between the first core layer and the second core layer. The recess extends through the second core layer and the central dielectric layer and exposes a portion of the core wiring layer.

In one embodiment of the invention, the core circuit layer protrudes from the surface of the core dielectric layer.

In an embodiment of the invention, the circuit board further includes a first line structure and a second line structure. The first line structure is disposed on a side of the first core layer away from the central dielectric layer. The second line structure is disposed on a side of the second core layer away from the central dielectric layer, and the groove extends through the second line structure.

In an embodiment of the invention, the first circuit structure includes a first dielectric layer and a first circuit layer, the first dielectric layer is disposed on the first core layer, and the first circuit layer is disposed on the first dielectric layer. On the floor.

In an embodiment of the invention, the second circuit structure includes a second dielectric layer and a second circuit layer, the second dielectric layer is disposed on the second core layer, and the second circuit layer is disposed on the second dielectric layer. On the floor.

In one embodiment of the invention, the core circuit layer has a laser blocking pattern on the edge of the portion of the core dielectric layer that is exposed by the recess.

In one embodiment of the invention, the central dielectric layer covers a portion of the laser blocking pattern and the recess exposes another portion of the laser blocking pattern.

The present invention provides a method of fabricating a circuit board as follows. First, a first core layer, a second core material layer and a central dielectric material layer are provided. The first core layer includes a core dielectric layer and a core circuit layer, the core circuit layer is disposed on the core dielectric layer, and the core circuit layer is a non-embedded circuit layer, and the second core material layer is disposed on the first core layer. On the layer, a central dielectric material layer is disposed between the first core layer and the second core material layer. Then, the first core layer, the second core material layer and the central dielectric material layer are pressed together to form a composite circuit structure, the composite circuit structure has a pre-removal zone, and at least part of the core circuit layer is located in the pre-removal zone. . Then, the portion of the central dielectric material layer at the edge of the pre-removal region and the portion of the second core material layer at the edge of the pre-removal region are removed. Thereafter, a portion of the central dielectric material layer in the pre-removal zone and a portion of the second core material layer in the pre-removal zone are removed to form a central dielectric layer and a second core layer.

In an embodiment of the invention, when the first core layer, the second core material layer and the central dielectric material layer are pressed together, the following process is further included. First, a first dielectric material layer and a first conductive layer are pressed onto the first core layer, wherein the first dielectric material layer is located between the first core layer and the first conductive layer, and is pressed into a second a layer of dielectric material and a second conductive layer to the second core layer, wherein the second layer of dielectric material is between the second core layer and the second conductive layer. Then, the first conductive layer and the second conductive layer are patterned to form a first circuit layer and a second circuit layer.

In an embodiment of the present invention, the method of fabricating the circuit board further includes: when removing a portion of the central dielectric material layer at the edge of the pre-removal region and a portion of the second core material layer at the edge of the pre-removal region, Removing a portion of the second layer of dielectric material at the edge of the pre-removal region, and removing a portion of the central dielectric material layer within the pre-removal region and the second core material layer within the pre-removal region In part, the portion of the second dielectric material layer in the pre-removal zone is removed to form a second dielectric layer.

In one embodiment of the invention, a method of removing a portion of the central dielectric material layer at the edge of the pre-removal region and a portion of the second core material layer at the edge of the pre-removal region comprises laser etching.

In an embodiment of the invention, the core circuit layer has a laser blocking pattern, and the laser blocking pattern is located at the edge of the pre-removal zone.

In one embodiment of the invention, the method of removing the portion of the central dielectric material layer that is located within the pre-removal zone and the portion of the second core material layer that is located within the pre-removal zone comprises stripping.

In an embodiment of the invention, the first core layer further includes a protective layer covering a portion of the core circuit layer located within the pre-removal zone.

In an embodiment of the present invention, the method of fabricating the circuit board further includes: after removing a portion of the central dielectric material layer located in the pre-removal region and a portion of the second core material layer located within the pre-removal region, Remove the protective layer.

The invention provides a circuit board having a recess, the circuit board comprising a multi-layer core structure comprising a plurality of core layers and a plurality of central dielectric layers alternately stacked, the recess penetrating a part of the core layer of the multi-layer core structure and At least a portion of the central dielectric layer, and one of the core layers is located at the bottom of the recess, the recess exposing a core circuit layer of the core layer at the bottom of the recess.

In an embodiment of the invention, the circuit board further includes a first line structure and a second line structure. The first line structure is disposed on a first side of the multilayer core structure. The second line structure is disposed on a second side of the multilayer core structure, wherein the first side is opposite the second side and the recess extends through the second line structure.

In an embodiment of the invention, the first wiring structure includes a first dielectric layer and a first wiring layer. The first dielectric layer is disposed on the first side of the multilayer core structure. The first circuit layer is disposed on the first dielectric layer.

In an embodiment of the invention, the second wiring structure includes a second dielectric layer and a second wiring layer. The second dielectric layer is disposed on the second side of the multilayer core structure. The second circuit layer is disposed on the second dielectric layer.

Based on the above, since the circuit board of the present invention has a plurality of core layers and a plurality of central dielectric layers alternately stacked, when the grooves penetrate the number of layers of one or more than half of the total dielectric layers, the grooves may penetrate through the partial core The layer is with at least a portion of the central dielectric layer and exposes a core circuit layer of the core layer at the bottom of the recess.

The above described features and advantages of the present invention will be more apparent from the following description.

2A is a cross-sectional view of a wiring board according to an embodiment of the present invention, and FIG. 2B is a variation of the wiring board of FIG. 2A. Referring to FIG. 2A, the circuit board 200 of the embodiment has a recess R. The circuit board 200 includes a first core layer 210, a second core layer 220, a central dielectric layer 230, and a first line structure 240. A second line structure 250.

The first core layer 210 includes a core dielectric layer 212 and two core circuit layers 214 and 216 respectively disposed on the lower surface 212a, 212b of the core dielectric layer 212 and electrically connected to each other. The core circuit layers 214, 216 protrude from the surfaces 212a, 212b of the core dielectric layer 212, respectively.

The second core layer 220 is disposed on the first core layer 210. The second core layer 220 can include a core dielectric layer 222 and two core circuit layers 224 and 226 respectively disposed on the lower two surfaces 222a and 222b of the core dielectric layer 222 and electrically connected to each other. The central dielectric layer 230 is disposed between the first core layer 210 and the second core layer 220.

The first line structure 240 is disposed on a side 218 of the first core layer 210 that is remote from the central dielectric layer 230. In the present embodiment, the first line structure 240 includes two dielectric layers 242, 246 and two circuit layers 244, 248 stacked on each other. The dielectric layer 242 is disposed on the first core layer 210. The circuit layer 244 is disposed on the dielectric layer 242 and located between the dielectric layers 242 and 246. The circuit layer 248 is disposed on the dielectric layer 246 away from the circuit layer 244. side. Of course, the embodiment does not limit the number of circuit layers and dielectric layers of the first line structure 240. In other words, the number of circuit layers or dielectric layers may be one or more.

The second line structure 250 is disposed on a side 228 of the second core layer 220 that is remote from the central dielectric layer 230. In this embodiment, the second circuit structure 250 includes two dielectric layers 252, 256 and two circuit layers 254, 258 stacked on each other, wherein the dielectric layer 252 is disposed on the second core layer 220, and the circuit layer 254 is disposed on the interface layer 254. The electrical layer 252 is located between the dielectric layers 252, 256, and the wiring layer 258 is disposed on the side of the dielectric layer 256 that is remote from the wiring layer 254. Of course, this embodiment does not limit the number of circuit layers and dielectric layers of the second circuit structure 250. In other words, the number of circuit layers or dielectric layers may be one or more.

The recess R of the circuit board 200 penetrates the second core layer 220, the central dielectric layer 230, and the second wiring structure 250 and exposes a portion of the core wiring layer 214. It should be noted that, in this embodiment, the total number of dielectric layers (including the central dielectric layer 230, the core dielectric layer 222 and the dielectric layers 252, 256) penetrated by the recess R is greater than the total number of the recesses R that are not penetrated. The number of dielectric layers (including core dielectric layer 212 and dielectric layers 242, 246). In other words, the groove R can penetrate the number of layers of more than one-half of the total number of dielectric layers (of the wiring board 200). Of course, in other embodiments not shown, the groove R may penetrate the number of layers below one-half of the total number of dielectric layers. Since the circuit board 200 of the present embodiment has the first and second core layers 210 and 220 stacked on each other, the recess R can penetrate through the second when the recess R penetrates the number of layers of one or more than half of the total dielectric layer. The core layer 220 exposes the core circuit layer 214 of the first core layer 210.

It should be noted that, in this embodiment, the number of core layers is not limited, in other words, the number of core layers may be three or more, and the recess may penetrate part of the core layer and at least part of the central dielectric layer. One of the core layers is located at the bottom of the recess and the recess exposes a core circuit layer of the core layer at the bottom of the recess. For example, referring to FIG. 2B, the circuit board 200a of the present embodiment includes a multi-layer core structure M having a first core layer 210, a second core layer 220, and a third core layer 270. A central dielectric layer 230 disposed between the first and second core layers 210, 220 and a central dielectric layer 280 disposed between the second and third core layers 220, 270. The recess R extends through the second and third core layers 220, 270 and the central dielectric layers 230, 280 and exposes a core wiring layer 214 of the first core layer 210 at the bottom of the recess R. It should be noted that this embodiment is not used to limit the number of core layers of the multi-layer core structure M penetrated by the groove R and the number of core layers not penetrated by the groove R. In other words, the groove R may only penetrate the third core. Layer 270.

Referring again to FIG. 2A, in the present embodiment, the core circuit layer 214 has a laser blocking pattern 214a that is located at the edge of the core dielectric layer 212 exposed by the recess R. The central dielectric layer 230 may cover a portion of the laser blocking pattern 214a, and the recess R may expose another portion of the laser blocking pattern 214a. In addition, in the embodiment, a solder mask layer 260 may be formed on the first line structure 240, the second line structure 250 and the first core layer 210 to cover and protect part of the circuit layers 248, 258 and the core line. Layer 214.

One of the manufacturing methods of the circuit board 200 of the present embodiment will be described in detail below.

3A to 3E are cross-sectional views showing a process of a circuit board according to an embodiment of the present invention.

First, referring to FIG. 3A, a first core layer 210, a second core material layer 220a, a central dielectric material layer 230a, a dielectric layer 242, a conductive layer 244a, a dielectric material layer 252a and a Conductive layer 254a.

The structure of the first core layer 210 is the same as that of the first core layer 210 of FIG. 2A. The second core material layer 220a is disposed on the first core layer 210, and the central dielectric material layer 230a is disposed between the first core layer 210 and the second core material layer 220a. The dielectric layer 242 is disposed on a side of the first core layer 210 away from the central dielectric material layer 230a and between the first core layer 210 and the conductive layer 244a. The dielectric material layer 252a is disposed on a side of the second core material layer 220a away from the central dielectric material layer 230a and between the conductive layer 254a and the second core material layer 220a.

Next, referring to FIG. 3B, the first core layer 210, the second core material layer 220a, the central dielectric material layer 230a, the dielectric layer 242, the conductive layer 244a, the dielectric material layer 252a, and the conductive layer 254a are laminated to form A composite circuit structure C having a pre-removed area P and a portion of the core line layer 214 is located in the pre-removed area P. Thereafter, the conductive layer 244a and the conductive layer 254a may be separately patterned to form a circuit layer 244 and a circuit layer 254, and a plurality of conductive paths V1, V2 are formed to electrically connect the circuit layer 244 and the circuit layer 254 to the circuit layer 254, respectively. The first core layer 210 and the second core material layer 220a.

3C, a dielectric layer 242, a wiring layer 244, a dielectric material layer 252a and a wiring layer 254 may be formed, and a dielectric layer 246 and a wiring layer 248 are selectively formed on the dielectric layer 242. A dielectric material layer 256a and a wiring layer 258 are formed on the dielectric material layer 252a.

Then, referring to FIG. 3D, the central dielectric material layer 230a, the second core material layer 220a, and the dielectric material layers 252a, 256a located at the edge of the pre-removed region P are removed by laser etching, for example, to form A slit G penetrating through the aforementioned material layers 230a, 220a, 252a, 256a. In this embodiment, the core circuit layer 214 may have a laser blocking pattern 214a at the edge of the pre-removed area P to protect the core dielectric layer 212 from laser etch. In addition, the first core layer 210 may have a protective layer A covering a portion of the core wiring layer 214 located within the pre-removed region P to protect the core wiring layer 214 in a subsequent removal process. Additionally, the protective layer A can be a release layer that can aid in the removal of the central dielectric material layer 230a located within the region P to be removed.

Thereafter, referring to FIG. 3E, the central dielectric material layer 230a, the second core material layer 220a and the dielectric material layers 252a, 256a located in the pre-removed area P are removed by, for example, stripping to form a central dielectric layer. 230, a second core layer 220, dielectric layers 252, 256, and a recess R. The dielectric layers 252, 256 and the circuit layers 254, 258 form a second wiring structure 250 that extends through the second wiring structure 250, the second core layer 220, and the central dielectric layer 230. Next, the protective layer A is removed. In other embodiments, the protective layer A and the central dielectric material layer 230a, the second core material layer 220a, and the dielectric material layers 252a, 256a located within the pre-removed region P may be simultaneously removed. Then, in the embodiment, a solder mask layer 260 may be formed on the first line structure 240, the second line structure 250 and the first core layer 210 to cover and protect part of the circuit layers 248, 258 and the core line. Layer 214.

In summary, since the circuit board of the present invention has a plurality of core layers and a plurality of central dielectric layers which are alternately stacked, when the grooves penetrate the number of layers of one or more than half of the total dielectric layers, the grooves can penetrate A portion of the core layer and at least a portion of the central dielectric layer expose the core circuit layer of the core layer at the bottom of the recess.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 200a. . . circuit board

110. . . Core layer

112, 212, 222. . . Core dielectric layer

114, 116, 132, 244, 248, 254, 258. . . Circuit layer

120, 130. . . Line structure

132, 242, 246, 252, 256. . . Dielectric layer

210. . . First core layer

212a, 212b, 222a, 222b. . . surface

214, 216, 224, 226. . . Core circuit layer

214a. . . Laser blocking pattern

218, 228. . . One side

220. . . Second core layer

220a. . . Second core material layer

230, 280. . . Central dielectric layer

230a. . . Central dielectric material layer

240. . . First line structure

244a, 254a. . . Conductive layer

250. . . Second line structure

252a, 256a. . . Dielectric material layer

260. . . Welding mask

270. . . Third core layer

A. . . The protective layer

C. . . Composite circuit structure

G. . . Slit

M. . . Multi-layer core structure

P. . . Pre-removal zone

R. . . Groove

V1, V2. . . Conductive channel

1 is a cross-sectional view of a conventional circuit board.

2A is a cross-sectional view of a wiring board according to an embodiment of the present invention.

Figure 2B is a variation of the circuit board of Figure 2A.

3A to 3E are cross-sectional views showing a process of a circuit board according to an embodiment of the present invention.

200. . . circuit board

210. . . First core layer

212, 222. . . Core dielectric layer

212a, 212b, 222a, 222b. . . surface

214, 216, 224, 226. . . Core circuit layer

214a. . . Laser blocking pattern

218, 228. . . One side

220. . . Second core layer

230. . . Central dielectric layer

240. . . First line structure

242, 246, 252, 256. . . Dielectric layer

244, 248, 254, 258. . . Circuit layer

250. . . Second line structure

260. . . Welding mask

R. . . Groove

Claims (11)

A circuit board having a recess, the circuit board comprising: a first core layer comprising a core dielectric layer and a core circuit layer, the core circuit layer being disposed on the core dielectric layer, wherein the core circuit layer Having a laser blocking pattern on an edge of a portion of the core dielectric layer exposed by the recess; a second core layer disposed on the first core layer; and a central portion a dielectric layer disposed between the first core layer and the second core layer, wherein the recess extends through the second core layer and the central dielectric layer and exposes a portion of the core circuit layer. The circuit board of claim 1, further comprising: a first circuit structure disposed on a side of the first core layer away from the central dielectric layer; and a second circuit structure disposed on the circuit board The second core layer is away from the side of the central dielectric layer, and the recess extends through the second line structure. The circuit board of claim 2, wherein the first circuit structure comprises: a first dielectric layer disposed on the first core layer; and a first circuit layer disposed on the first interface On the electrical layer. The circuit board of claim 2, wherein the second circuit structure comprises: a second dielectric layer disposed on the second core layer; and a second circuit layer disposed on the second layer On the electrical layer. The circuit board of claim 1, wherein the central board The dielectric layer covers a portion of the laser blocking pattern that exposes another portion of the laser blocking pattern. A method for manufacturing a circuit board, comprising: providing a first core layer, a second core material layer and a central dielectric material layer, the first core layer comprising a core dielectric layer and a core circuit layer, the core circuit a layer is disposed on the core dielectric layer, the second core material layer is disposed on the first core layer, and the central dielectric material layer is disposed between the first core layer and the second core material layer, where The core circuit layer has a laser blocking pattern; pressing the first core layer, the second core material layer and the central dielectric material layer to form a composite circuit structure, the composite circuit structure having a pre-removal area, And at least part of the core circuit layer is located in the pre-removal zone, wherein the laser blocking pattern is located at an edge of the pre-removal zone; performing a laser etching to remove the central dielectric material layer in the pre-removal zone a portion of the edge and a portion of the second core material layer at an edge of the pre-removal region; and a portion of the central dielectric material layer that is removed within the pre-removal region and the second core material layer is located Pre-shift Part region, center to form a second dielectric layer and a core layer. The method for manufacturing a circuit board according to claim 6, wherein when the first core layer, the second core material layer and the central dielectric material layer are pressed together, the method further comprises: pressing a first medium. And a first conductive layer on the first core layer, wherein the first dielectric material layer is located on the first core layer and the first Between a conductive layer; pressing a second dielectric material layer and a second conductive layer to the second core layer, wherein the second dielectric material layer is located between the second core layer and the second conductive layer And patterning the first conductive layer and the second conductive layer to form a first circuit layer and a second circuit layer. The method for fabricating a circuit board according to claim 7, further comprising: removing a portion of the central dielectric material layer at an edge of the pre-removal region and the second core material layer at the pre-shifting Removing a portion of the second layer of dielectric material at an edge of the pre-removal region in addition to a portion of the edge of the region; and removing a portion of the central dielectric material layer within the pre-removal region and the portion When the portion of the second core material layer is located in the pre-removal region, the portion of the second dielectric material layer located in the pre-removal region is removed to form a second dielectric layer. The method for fabricating a circuit board according to claim 6, wherein the portion of the central dielectric material layer in the pre-removal zone and the second core material layer are located in the pre-removal zone. Part of the method includes stripping. The method for fabricating a circuit board according to claim 6, wherein the first core layer further comprises: a protective layer covering a portion of the core circuit layer located in the pre-removal zone. The method for manufacturing a circuit board according to claim 10, further comprising: removing the portion of the central dielectric material layer located in the pre-removal region and the second core material layer at the pre-shifting The protective layer is removed at the same time as or after the portion of the zone.