TWI387093B - High-voltage-tolerant esd clamp circuit with low leakage current fabricated by low-voltage cmos process - Google Patents

Description

Low-leakage high-voltage power supply electrostatic discharge protection using low-voltage components Circuit

The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to a low leakage high voltage power supply electrostatic discharge protection circuit implemented by a low voltage component.

A general ESD protection circuit is disposed between the power supply end and the ground end of the electronic system. The ideal ESD protection circuit must be completely turned off during normal operation of the electronic system and there should be no leakage. If an ESD pulse occurs, the ESD protection circuit must be turned on to introduce an ESD pulse from the power supply to the ground to protect the electronic system.

In the nanoscale complementary metal oxide semiconductor (CMOS) process, the gate oxide becomes thinner with the evolution of the process technology, and the operating voltage also decreases. However, in an electronic system, there are often multiple subsystems operating at different operating voltages. In order to be compatible with different operating voltages, the conventional method can be manufactured with a thicker gate oxide layer to withstand higher voltages. Subsystem, thereby avoiding the problem of excessive electrical stress (EOS) of the gate oxide layer. However, adding an additional mask to the manufacturing process to create a thick gate oxide layer increases process complexity, product yield may decrease, and overall production costs increase.

In order to reduce the production cost, it is a hot research topic to use only the low-voltage components of the thin gate oxide layer to realize a circuit that can withstand high operating voltage, and the electrostatic discharge protection circuit is no exception.

1 is a circuit diagram of a conventional electrostatic discharge protection circuit. The ESD protection circuits of Figure 1 all use low-voltage components. Assuming that these low-voltage components can only withstand the VDD operating voltage, the circuit of Figure 1 can withstand twice the VDD operating voltage. That is to say, the operating voltage Hi-Vcc provided by the power supply terminal 210 is twice that of VDD.

The ESD protection circuit of FIG. 1 is divided into three parts: a discharge path 202, a control circuit 204, and a P-channel metal oxide semiconductor field effect transistor (PMOS) 302 and 304. Voltage divider circuit. Both PMOS transistors 302 and 304 are diode-connected. The voltage dividing circuit described above divides the operating voltage Hi-Vcc into two equal parts such that the voltage across the power supply terminal 210 and the node 303 is equal to VDD, and the voltage across the node 303 and the ground is also equal to VDD. This allows each of the low voltage components of the circuit of Figure 1 to operate normally without suffering from excessive electrical stress.

Control circuit 204 turns off PMOS transistors 206 and 208 when the electronic system is operating normally, causing discharge path 202 to be turned off. If an electrostatic discharge pulse occurs at the power supply terminal 210, the control circuit 204 turns on the PMOS transistors 206 and 208 to turn on the discharge path 202 and direct the electrostatic discharge pulse to the ground to protect the electronic system.

2 is a circuit diagram of another conventional electrostatic discharge protection circuit. The electrostatic discharge protection circuit of Figures 2 and 1 has the same operational principle, with the difference that the control circuit 204 of Figure 2 is relatively simplified.

In the traditional process, the leakage of circuit components is very slight. Taking the circuit of FIG. 1 and FIG. 2 as an example, the leakage current of the control circuit 204 and the discharge path 202 is not obvious, so the voltage dividing circuit does not need to provide too much driving current, and the overall leakage of the electrostatic discharge protection circuit is not serious.

However, in the current nano-scale advanced process, since the dimensions of various aspects of the low-voltage component are reduced, the leakage of the control circuit 204 and the discharge path 202 is significantly increased, so the voltage-dividing circuit must provide a large driving current to maintain The correct partial voltage, for example, maintains the voltage at node 303 at VDD. Since the voltage dividing circuit must provide a large current, and the voltage dividing circuit itself is also composed of low voltage components, the leakage of the voltage dividing circuit is more serious, accounting for most of the leakage current of the entire electrostatic discharge protection circuit. In addition, the circuit layout area occupied by the voltage divider circuit cannot be reduced. Due to the leakage problem, the use of the ESD protection circuit shown in Figures 1 and 2 in advanced processes has not met the considerations of energy conservation and cost reduction.

3 is a circuit diagram of another conventional electrostatic discharge protection circuit. The ESD protection circuit of Figure 3 also uses low voltage components. Assuming that these low voltage components can only withstand the VDD operating voltage, the circuit of Figure 3 can withstand three times the VDD operating voltage.

The electrostatic discharge protection circuit of FIG. 3 has the same operation principle as the electrostatic discharge protection circuit of FIGS. 1 and 2. The ESD protection circuit of FIG. 3 includes a discharge path 110, a control circuit 120, and a voltage dividing circuit 130, wherein the discharge path 110 includes a silicon-controlled rectifier (SCR) 115. The voltage dividing circuit 130 divides the operating voltage of the triple VDD into three equal parts by using six serially connected PMOS transistors Md1-Md6 in a diode manner to ensure that each low voltage component in the circuit of FIG. 3 is not Will suffer from excessive electrical stress. The control circuit 120 outputs a trigger current I_trig when the electrostatic discharge pulse occurs, turns on the discharge path 110, and introduces the electrostatic discharge pulse to the ground.

Since the working principle is the same as the electrostatic discharge protection circuit of FIG. 1 and FIG. 2, the electrostatic discharge protection circuit of FIG. 3 also has a serious leakage problem under the advanced process.

The invention provides an electrostatic discharge protection circuit, which is composed of a low voltage component, can withstand a high voltage power supply, and can solve the leakage problem of the conventional circuit in an advanced process, and is suitable for an electronic system having multiple working voltages.

The invention provides an electrostatic discharge protection circuit, which comprises a plurality of identical modular circuits. The power supply end of the first module circuit is coupled to the power supply end of the electrostatic discharge protection circuit, and the power supply ends of each of the other module circuits are coupled. The ground end of the last module circuit, the ground end of the last module circuit is coupled to the ground of the ESD protection circuit. Each of the above module circuits includes a conduction path and a detection circuit. The conduction path is coupled to the power terminal of the module circuit. The detecting circuit is coupled to the power terminal, the ground terminal and the conductive path of the module circuit. If the voltage rise speed of the power supply terminal of the module circuit exceeds a critical value, the detection circuit turns on the conduction path.

In an embodiment of the present invention, a conduction path of each of the module circuits is coupled between a power terminal and a ground terminal of the module circuit, and an electrostatic discharge pulse is transmitted from a power terminal of the module circuit to the module circuit. Ground terminal.

In an embodiment of the invention, the electrostatic discharge protection circuit further includes a discharge path. The discharge path is coupled between the power supply end of the ESD protection circuit and the ground end, and an electrostatic discharge pulse is introduced from the power supply end to the ground end. The conduction path of the last module circuit is coupled to the discharge path, and outputs a trigger signal to turn on the discharge path. The conduction path of each of the other module circuits is coupled between the power terminal and the ground terminal of the module circuit to transmit the trigger signal.

In an embodiment of the invention, each of the detecting circuits includes a PMOS transistor, a resistor, a capacitor, and three inverters. The PMOS transistor is coupled between the power terminal of the module circuit and the first node. The resistor is coupled between the first node and the second node. The capacitor is coupled between the second node and the ground of the associated module circuit. The first inverter is coupled to the second node and receives the voltage of the second node. The second inverter is coupled to the first inverter and receives the output of the first inverter. The third inverter is coupled to the first node and the second inverter to receive the voltage of the first node. The output of the third inverter turns the corresponding conduction path on or off.

In an embodiment of the invention, the high voltage ends of the first inverter and the second inverter are coupled to the first node. The low voltage terminals of the first inverter and the second inverter are coupled to the ground terminal of the module circuit. The high voltage end of the third inverter is coupled to the power terminal of the module circuit. The low voltage end of the third inverter is coupled to the output of the second inverter.

In an embodiment of the invention, the electrostatic discharge protection circuit further includes a voltage dividing circuit. The voltage dividing circuit is coupled between the power terminal and the ground end of the electrostatic discharge protection circuit, and is coupled to the power terminal and the ground terminal of each of the module circuits. The voltage dividing circuit divides the voltage across the power supply end and the ground end of the ESD protection circuit equally, so that the voltage across the power supply end and the ground end of each of the module circuits is equal.

The invention further provides an electrostatic discharge protection circuit comprising a PMOS transistor, a capacitor, a resistor, three inverters, and a conduction path. The PMOS transistor is coupled between the power terminal and the first node. The resistor is coupled between the first node and the second node. The capacitor is coupled between the second node and the ground. The first inverter is coupled to the second node and receives the voltage of the second node. The second inverter is coupled to the first inverter and receives the output of the first inverter. The third inverter is coupled to the first node and the second inverter to receive the voltage of the first node. The conduction path is coupled to the power supply terminal and is turned on or off according to the output of the third inverter.

The invention further provides an electrostatic discharge protection circuit comprising a PMOS transistor, a reaction circuit, an inverter, and a conduction path. The PMOS transistor is coupled between the power terminal and a first node. The reaction circuit is coupled to the first node, and can detect the electrostatic discharge pulse of the power terminal, and reflect the detection result to a second node and the first node. The inverter is coupled to the first node and receives the voltage of the first node to output according to the voltage of the first node and the second node. The conduction path is coupled to the power supply terminal and is turned on or off according to the output of the inverter.

The electrostatic discharge protection circuit of the invention achieves self-dividing with a completely symmetrical modular circuit, and divides the higher operating voltage into a range that the low-voltage component can withstand, so that it can be completely composed of low-voltage components. An additional mask that does not require a thick gate oxide layer during the process simplifies the process, improves product yield, and reduces cost. The electrostatic discharge protection circuit of the invention does not require an additional voltage dividing circuit, so that the leakage problem of the conventional circuit in the advanced process can be greatly improved, and each module circuit also has a design for reducing leakage.

The above described features and advantages of the present invention will be more apparent from the following description.

4 is a schematic diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention, and FIG. 6 is a circuit diagram of the electrostatic discharge protection circuit of FIG. 4. Please refer to FIG. 4 and FIG. 6 for the following description.

The ESD protection circuit of this embodiment includes a plurality of identical module circuits, such as the module circuits 410 and 430 illustrated in FIG. 4, which are coupled in series; each module circuit has the same circuit. Architecture, component combination and configuration configuration. Each module circuit has a power terminal and a ground terminal. For example, the module circuit 410 has a power terminal 412 and a ground terminal 414. Among the module circuits, the power supply end of the first module circuit is coupled to the power supply end 450 of the ESD protection circuit, and the power supply end of each of the other module circuits is coupled to the ground end of the previous module circuit, and the last mode The ground terminal of the group circuit is coupled to the ground terminal 455 of the electrostatic discharge protection circuit.

The electrostatic discharge protection circuit of this embodiment can be composed entirely of low voltage components. Because there are a plurality of identical module circuits connected in series between the power terminal 450 and the ground terminal 455 of the ESD protection circuit, the module circuits themselves have a voltage dividing function, and the working voltage provided by the power terminal 450 can be equally divided. To the extent that the low voltage component can withstand. For example, assuming that the operating voltage of each low-voltage component is VDD, and the operating voltage of the ESD protection circuit is n times VDD, n is a positive integer of 2 or more, the ESD protection circuit may include n module circuits, The voltage across each module circuit is divided into VDD. This allows each low voltage component to operate normally without suffering from excessive electrical stress.

Since the module circuit itself has a voltage dividing function, the electrostatic discharge protection circuit of the present embodiment does not require a conventional voltage dividing circuit such as 202 of FIG. 1, FIG. 2, and FIG. The conventional voltage dividing circuit is omitted, and the serious leakage and large area of the conventional voltage dividing circuit are removed, so that the leakage problem of the entire electrostatic discharge protection circuit can be greatly improved, and the circuit area can also be reduced.

Each module circuit includes a conduction path and a detection circuit. For example, the module circuit 410 of FIG. 6 includes a conduction path formed by the detection circuit 420 and the PMOS transistor P2. The PMOS transistor P2 is turned on or off according to the output of the detecting circuit 420. The detection circuit 420 is coupled to the power terminal 412, the ground terminal 414, and the conduction path P2 of the module circuit 410. The function of the detecting circuit 420 is to detect the electrostatic discharge pulse. If the voltage rising speed of the power terminal 412 exceeds a preset threshold, indicating that there is an electrostatic discharge pulse, the detecting circuit 420 turns on the PMOS transistor P2 to turn on the conduction path.

As shown in FIG. 4, the conduction path P2 of each module circuit is coupled between the power terminal and the ground terminal of the module circuit. If an electrostatic discharge pulse occurs at the power terminal 450 of the ESD protection circuit, the detection circuit of each module circuit turns on the corresponding conduction path, and the ESD pulse is transmitted from the power terminal of the module circuit to the module circuit to which it belongs. Ground terminal. In this way, the electrostatic discharge pulse is introduced from the power supply terminal 450 to the ground terminal 455 to protect the electronic system.

In order to reduce leakage, the present invention can appropriately limit the size of the above-described PMOS transistor P2, although this may reduce the conductivity of the conduction path, the present invention may use the enhanced design as shown in FIGS. 5 and 7. FIG. 5 is a schematic diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention, and FIG. 7 is a circuit diagram of the electrostatic discharge protection circuit of FIG. 5. The ESD protection circuit of Figure 5 adds a discharge path 470. The discharge path 470 is coupled between the power terminal 450 and the ground terminal 455 of the ESD protection circuit. In addition to the last module circuit, the conduction path P2 of each module circuit is coupled between the power terminal and the ground terminal of the module circuit, as shown by the module circuit 410. The conduction path P2 of the last module circuit is coupled between the power terminal of the module circuit and the discharge path 470, as shown by the module circuit 430. Please note that the module circuit 430 and each module circuit 410 can still be the same circuit, with the same circuit architecture and component combination.

When an electrostatic discharge pulse occurs at the power terminal 450 of the ESD protection circuit, the detection circuit in each module circuit turns on the corresponding conduction path. The electrostatic discharge pulse generates a trigger signal, and the trigger signal is transmitted along the conduction path of each module circuit to the discharge path 470, so that the discharge path 470 is turned on, and the electrostatic discharge pulse is introduced into the electrostatic discharge from the power terminal 450 of the electrostatic discharge protection circuit. The ground terminal 455 of the protection circuit. The trigger signal described above may be a current signal or a voltage signal. The discharge path 470 can be composed of a component such as a controlled voltage rectifier (SCR) or a field-oxide device (FOD). If the discharge path 470 uses an element that does not contain an oxide layer, such as a controlled rectifier, its leakage current is negligible, and it can both improve the conductivity and reduce the leakage.

The details of the detection circuit and the operation principle thereof will be described below with reference to FIG. 8 to FIG. FIG. 8 is a circuit diagram of an electrostatic discharge protection circuit in accordance with an embodiment of the present invention. For the sake of brevity, the ESD protection circuit of FIG. 8 includes only one module circuit 810. The module circuit 810 includes a conduction path formed by the detection circuit 820 and the PMOS transistor P2. 850 is the common power supply end of the ESD protection circuit and the module circuit 810 of FIG. 8, and 855 is the common ground end of the ESD protection circuit and the module circuit 810 of FIG.

The detecting circuit 820 includes a PMOS transistor P1, a resistor R1, a capacitor C1, and three inverters I1, I2, and I3. Each inverter has four terminals, an input terminal, an output terminal, a high voltage terminal, and a low voltage terminal. Wherein, the high voltage end is the source of the PMOS transistor of the inverter, and the low voltage end is the N-channel metal oxide semiconductor field effect transistor (NMOS). The source of the crystal). The PMOS transistor P1 is coupled between the power terminal 850 and the node 801. The resistor R1 is coupled between the node 801 and the node 802. The capacitor C1 is coupled between the node 802 and the ground 855. The resistor R1 and the capacitor C1 can form a reaction circuit, and the nodes 801 and 802 can be regarded as a first node and a second node, respectively. The high voltage terminal of the inverter I1 is coupled to the node 801, the low voltage terminal is coupled to the ground terminal 855, the input terminal is coupled to the node 802, the voltage of the node 802 is received, and the output terminal is coupled to the node 803 to provide the voltage of the node 803. The high voltage terminal of the inverter I2 is also coupled to the node 801. The low voltage terminal is also coupled to the ground terminal 855. The input terminal is coupled to the node 803, and receives the voltage of the node 803. The output terminal is coupled to the node 804 to provide the voltage of the node 804. The inverters I1 and I2 can be regarded as a combined circuit. The high voltage terminal of the inverter I3 is coupled to the power terminal 850, the low voltage terminal is coupled to the node 804, the input terminal is coupled to the node 801, the voltage of the node 801 is received, and the output terminal is coupled to the node 805 to provide the voltage of the node 805. The voltage at node 805 is also the gate voltage of PMOS transistor P2. Therefore, the output of the inverter I3 can turn on or off the conduction path P2.

The detecting circuit 820 uses the charging speed of the capacitor C1 to distinguish the normal working voltage from the sudden electrostatic discharge pulse; equivalently, according to the charging speed, a critical value can be defined for the voltage rising speed of the power terminal (critical speed). According to an embodiment of a typical parameter, FIG. 9 illustrates the operating voltage VDD, the voltages of the nodes 801 to 805, and the leakage current of the module circuit 810 of the ESD protection circuit of FIG. 8 during normal startup. During normal startup, the operating voltage VDD provided by the power supply terminal 850 rises from 0V to 1V (that is, the rated voltage value of VDD) in about 100 microseconds, and the rise of VDD turns on the PMOS transistor P1. At this time, the rising speed of VDD is lower than the preset critical speed at the time of design, and the charging speed of the capacitor C1 can keep up, so the voltages of the nodes 801 and 802 rise synchronously. For inverters I1 and I2, the voltage at node 801 is a logic high and the voltage at node 802 is also a logic high. Therefore, inverter I1 receives the logic high of node 802, outputs a logic low of node 803, and inverter I2 receives the logic low of node 803, outputting a logic high of node 804. However, for inverter I3, the operating voltage VDD of the power supply terminal 850 is a logic high, and the voltages of the nodes 801 and 804 are only 0.2V, which is a logic low potential. Therefore, the NMOS transistor of the inverter I3 is turned off, and the PMOS transistor is turned on, so that the voltage of the node 805 is equal to (or is close to) the operating voltage VDD, thereby turning off the PMOS transistor P2 of the conduction path, so that the trigger current is not sent. The discharge path 870 is turned on.

The PMOS transistor P1 is a low leakage design of the detection circuit 820 itself. During normal startup, the voltage of the node 805 gradually rises, and finally the PMOS transistor P1 is turned off and does not conduct, so that the capacitor C1 is no longer charged. As shown in FIG. 9, the capacitor C1 is only charged to 0.2V, and is not much compared with the operating voltage VDD of 1V, which can reduce the leakage of the capacitor C1 and the entire module circuit 810. As shown in FIG. 9, the leakage current of the module circuit 810 does not exceed 0.15 microamperes (μA). Because of this, the capacitor C1 does not have to use a thick oxide layer in order to reduce leakage, and the circuit area can be reduced.

FIG. 10 illustrates the operating voltage VDD, the voltages of the nodes 801 to 805, and the trigger current output by the conduction path P2 of the electrostatic discharge protection circuit of FIG. 8 when subjected to an electrostatic discharge pulse. The electrostatic discharge pulse causes the operating voltage VDD to rise from 0V to 2V within 10 nanoseconds, and the rise of VDD turns on the PMOS transistor P1. At this time, the rising speed of VDD is higher than the preset critical speed at the time of design, and the charging speed of the capacitor C1 cannot keep up, so the voltage of the node 801 and the operating voltage VDD rise synchronously, and the voltage of the node 802 cannot rise synchronously. For inverters I1 and I2, the voltage at node 801 (2V) is a logic high and the voltage at node 802 becomes a logic low. Therefore, the inverter I1 receives the logic low of the node 802, the logic high of the output node 803, and the inverter I2 receives the logic high of the node 803 and the logic low of the output node 804. For inverter I3, the voltages at power supply terminal 850 and node 801 are both logic high and the voltage at node 804 is logic low. Therefore, the PMOS transistor of the inverter I3 is turned off, and the NMOS transistor is turned on, the voltage of the node 805 is pulled down, and the PMOS transistor P2 of the conduction path is turned on, and the trigger current is sent to further turn on the discharge path 870.

FIG. 11 illustrates the operating voltage VDD, the voltages of the nodes 801 to 805, and the trigger current output by the conduction path P2 of the electrostatic discharge protection circuit of FIG. 8 when encountering another stronger electrostatic discharge pulse. The electrostatic discharge pulse of Figure 11 causes the operating voltage VDD to rise from 0V to 5V within 10 nanoseconds. The situation in Fig. 11 and Fig. 10 is very similar and will not be described again.

As shown in FIG. 12, in some conventional ESD protection circuits, after the noise/surge occurs at the operating voltage VDD, the trigger voltage for turning on the discharge path does not return to 0V, but a latch phenomenon occurs. Maintained at a non-zero voltage (in the example of Figure 12, it is maintained at around 1V). Such a latching phenomenon can cause a continuous leakage of the circuit, which is not ideal. On the other hand, the embodiment of the invention of Fig. 8 does not have the aforementioned latching problem. As shown in Figure 13, the noise of the operating voltage VDD turns on the PMOS transistors P1 and P2 to provide a trigger voltage (i.e., the voltage across the resistor R2). However, because of the discharge path of the resistor R1 and the capacitor C1, the voltage of each node is returned to the voltage level before the noise occurs after the discharge, and the PMOS transistors P1 and P2 are turned off after the noise is dissipated, so that the trigger voltage returns to 0V.

The electrostatic discharge protection circuit of the above embodiment can be divided by itself, and does not require an additional voltage dividing circuit. However, even if a voltage dividing circuit is added, the operation of the electrostatic discharge protection circuit of the above embodiment will not be affected. For example, in the embodiment of Figures 4 and 5, a voltage divider circuit (not shown) can be added next to the plurality of module circuits to provide current for driving the various module circuits. The voltage dividing circuit can be coupled between the power terminal 450 and the grounding terminal 455 of the ESD protection circuit, and coupled to the power terminal and the ground terminal of each module circuit, for example, the power terminal 412 of the module circuit 410. And ground terminal 414. As described above, the voltage dividing circuit can equally divide the voltage across the power supply end and the ground of the ESD protection circuit, further ensuring that the voltage across the power supply terminal and the ground terminal of each module circuit is equal. For example, if there are n module circuits 410 applied to an electronic system of n times VDD, the voltage dividing circuit may include n identical voltage dividing elements (such as resistors, diodes or transistors). The two ends of each voltage dividing component connected in series are respectively connected to a power terminal and a ground terminal of a corresponding module circuit 410. Since the module circuit of the above embodiment can be divided by itself, the above-mentioned voltage dividing circuit does not need a large driving capability, does not have a serious leakage problem, and does not need to occupy a large layout area.

In summary, the electrostatic discharge protection circuit of the present invention is completely composed of a low voltage component, and can withstand a high voltage power supply without subjecting the components therein to excessive electrical stress, and is suitable for an electronic system having multiple operating voltages. Since the low voltage component is completely used, the electrostatic discharge protection circuit of the present invention does not require an additional mask of a thick gate oxide layer, which simplifies the process, improves product yield, and reduces cost. The electrostatic discharge protection circuit of the present invention does not require a conventional voltage dividing circuit, thereby reducing leakage and reducing circuit area. In addition, the module circuit of the electrostatic discharge protection circuit of the present invention also has a design for reducing leakage and reducing area. In addition, the modular design concept of the present invention enables the present invention to enable modular circuits of the same design to be applied to different electronic systems of different operating voltages. In the embodiment of FIG. 4 and FIG. 5, if necessary, a circuit may be disposed between the module circuit 430 and the ground terminal 455; and the power terminal 412 of the first module circuit 410 and the power terminal 450 are also visible. Need to set the relevant circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

110. . . Discharge path

115. . . Voltage controlled rectifier

120. . . Control circuit

130. . . Voltage dividing circuit

202. . . Discharge path

204. . . Control circuit

210, 303, 315, 346. . . Circuit node

300. . . Electrostatic discharge protection circuit

206, 208, 302, 304, 306, 318, 340, 344, 348. . . PMOS transistor

312, 316, 322, 342. . . NMOS transistor

307. . . resistance

308, 324, 326, 345. . . capacitance

410, 430. . . Module circuit

420. . . Detection circuit

412, 450. . . Power terminal

414, 455. . . Ground terminal

470. . . Discharge path

801-805. . . Circuit node

810. . . Module circuit

820‧‧‧Detection circuit

850‧‧‧Power terminal

855‧‧‧ Grounding terminal

870‧‧‧discharge path

A-v‧‧‧circuit node

C1‧‧‧ capacitor

D1, D2‧‧‧ diode

I_trig‧‧‧current signal

I1, I2, I3‧‧‧ inverter

M1-M4, M6, Md1-Md6, Mp1-Mp5‧‧‧ PMOS transistors

M5, Mn1‧‧‧ NMOS transistor

Mc1‧‧‧ capacitor

P1, P2‧‧‧ PMOS transistor

R1, R2‧‧‧ resistance

Hi-Vcc, VDD‧‧‧ working voltage

VSS‧‧‧ Grounding voltage

1 to 3 are circuit diagrams of three conventional ESD protection circuits.

4 is a schematic diagram of an electrostatic discharge protection circuit in accordance with an embodiment of the present invention.

FIG. 5 is a schematic diagram of an electrostatic discharge protection circuit in accordance with another embodiment of the present invention.

Fig. 6 is a circuit diagram of the electrostatic discharge protection circuit of Fig. 4.

Fig. 7 is a circuit diagram of the electrostatic discharge protection circuit of Fig. 5.

FIG. 8 is a circuit diagram of an electrostatic discharge protection circuit in accordance with another embodiment of the present invention.

FIG. 9 is a diagram showing voltages and leakage currents of respective nodes of the ESD protection circuit of FIG. 8 during normal startup.

10 and 11 illustrate voltages and trigger currents of respective nodes when the electrostatic discharge protection circuit of FIG. 8 encounters an electrostatic discharge pulse.

FIG. 12 illustrates an operating voltage and a trigger voltage of a conventional electrostatic discharge protection circuit that encounters power supply noise.

FIG. 13 is a diagram showing the operating voltage and the trigger voltage of the ESD protection circuit of FIG. 8 when power supply noise is encountered.

410‧‧‧Modular Circuit

420‧‧‧Detection circuit

412, 450‧‧‧ power supply end

414, 455‧‧‧ Grounding

P2‧‧‧ PMOS transistor

VDD‧‧‧ working voltage

VSS‧‧‧ Grounding voltage

Claims (14)

An ESD protection circuit includes: a plurality of module circuits identical to each other, wherein a power supply end of the first module circuit is coupled to a power supply end of the ESD protection circuit, and a power supply end of each of the other module circuits is coupled a ground end of the module circuit, the ground end of the last module circuit is coupled to the ground end of the ESD protection circuit, each of the module circuits includes: a conductive path coupled to the power end of the module circuit; a detecting circuit coupled to the power terminal, the grounding end and the conducting path of the module circuit; if the voltage rising speed of the power terminal of the module circuit exceeds a critical value, the detecting circuit turns on the conducting path, wherein Each of the detecting circuits includes: a PMOS transistor coupled between the power terminal of the module circuit and a first node; and a resistor coupled between the first node and a second node; a capacitor coupled between the second node and a ground terminal of the module circuit; a first inverter coupled to the second node to receive the voltage of the second node; a second inverter coupled Pick up the first An inverter receiving an output of the first inverter; and a third inverter coupled to the first node and the second inverter to receive a voltage of the first node, the third inversion The output of the device turns the corresponding conduction path on or off. The ESD protection circuit of claim 1, wherein the conduction path comprises a PMOS transistor, and the PMOS transistor is turned on or off according to an output of the detection circuit. The electrostatic discharge protection circuit of claim 1, wherein a conduction path of each of the module circuits is coupled between a power supply end and a ground end of the module circuit, and an electrostatic discharge pulse is applied from the module. The power supply terminal of the circuit is conducted to the ground terminal of the module circuit. The electrostatic discharge protection circuit of claim 1, further comprising: a discharge path coupled between the power supply end and the ground end of the electrostatic discharge protection circuit, and an electrostatic discharge pulse from the electrostatic discharge protection circuit The power supply end is connected to the ground end of the ESD protection circuit; the conduction path of the last module circuit is coupled to the discharge path, and a trigger signal is output to make the discharge path conductive; the conduction path coupling of each of the remaining module circuits is coupled The trigger signal is transmitted between the power terminal and the ground terminal of the module circuit. The ESD protection circuit of claim 1, wherein the high voltage terminals of the first inverter and the second inverter are coupled to the first node, the first inverter and the second The low voltage end of the inverter is coupled to the ground end of the module circuit, the high voltage end of the third inverter is coupled to the power end of the module circuit, and the low voltage end of the third inverter is coupled to the second end. The output of the inverter. The electrostatic discharge protection circuit of claim 1, further comprising: a voltage dividing circuit is coupled between the power end of the ESD protection circuit and the ground end, and is coupled to the power end and the ground end of each of the module circuits, and the power end of the ESD protection circuit is grounded The voltage across the terminals is evenly divided so that the voltage across the power supply terminal and the ground terminal of each of the above module circuits is equal. An ESD protection circuit includes: a first PMOS transistor coupled between a power terminal and a first node; a resistor coupled between the first node and a second node; a capacitor, The first inverter is coupled to the second node and coupled to the second node to receive the voltage of the second node; a second inverter coupled to the first inverting Receiving the output of the first inverter; a third inverter coupled to the first node and the second inverter to receive the voltage of the first node; and a conductive path coupled to the power supply The terminal is turned on or off according to the output of the third inverter. The ESD protection circuit of claim 7, wherein the conduction path comprises a second PMOS transistor, the second PMOS transistor being turned on or off according to an output of the third inverter. The ESD protection circuit of claim 7, wherein the conduction path is coupled between the power terminal and the ground, and an electrostatic discharge pulse is transmitted from the power terminal to the ground. The electrostatic discharge protection circuit of claim 7, further comprising: a discharge path coupled to the conduction path and the ground end to introduce an electrostatic discharge pulse to the ground end, wherein the conduction path outputs a trigger signal , the discharge path is turned on. The ESD protection circuit of claim 7, wherein the high voltage terminals of the first inverter and the second inverter are coupled to the first node, the first inverter and the second The low-voltage end of the inverter is coupled to the ground, the high-voltage end of the third inverter is coupled to the power terminal, and the low-voltage end of the third inverter is coupled to the output of the second inverter. An ESD protection circuit includes: a first PMOS transistor coupled between a power terminal and a first node; a reaction circuit coupled to the first node; the reaction circuit can detect the power terminal The electrostatic discharge pulse reflects the detection result to a second node and the first node; an inverter coupled to the first node, receiving the voltage of the first node, according to the first node and the first The voltage of the two nodes is a corresponding output; and a conductive path is coupled to the power supply terminal, and is turned on or off according to an output of the inverter, wherein the inverter is coupled to the second node via a combination circuit; When the reaction circuit detects an electrostatic discharge pulse, the reaction circuit can provide a voltage difference between the first node and the second node to enable the combination circuit to receive a logic high potential input; when the reaction circuit is not detected To static electricity When the pulse is discharged, the reaction circuit causes the combination circuit to receive a logic low input. The electrostatic discharge protection circuit of claim 12, wherein the reaction circuit comprises: a resistor coupled between the first node and the second node; and a capacitor coupled to the second node Between a ground and a ground. The electrostatic discharge protection circuit of claim 12, wherein the combination circuit comprises: a first inverter coupled to the second node to receive a voltage of the second node; and a second inverter The first inverter is coupled to receive the output of the first inverter.