TWI369504B - Methods of locating a fault within an array of integrated circuits, methods of testing an array of interconnect modules, and speed fault test vehicles for locating a fault within an array of interconnect modules - Google Patents

Methods of locating a fault within an array of integrated circuits, methods of testing an array of interconnect modules, and speed fault test vehicles for locating a fault within an array of interconnect modules

Info

Publication number
TWI369504B
TWI369504B TW094119790A TW94119790A TWI369504B TW I369504 B TWI369504 B TW I369504B TW 094119790 A TW094119790 A TW 094119790A TW 94119790 A TW94119790 A TW 94119790A TW I369504 B TWI369504 B TW I369504B
Authority
TW
Taiwan
Prior art keywords
array
fault
locating
methods
interconnect modules
Prior art date
Application number
TW094119790A
Other languages
Chinese (zh)
Other versions
TW200612107A (en
Inventor
Richard Schultz
Derryl Allman
Jan Fure
Original Assignee
Lsi Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/900,642 external-priority patent/US7308627B2/en
Application filed by Lsi Corp filed Critical Lsi Corp
Publication of TW200612107A publication Critical patent/TW200612107A/en
Application granted granted Critical
Publication of TWI369504B publication Critical patent/TWI369504B/en

Links

TW094119790A 2004-07-27 2005-06-15 Methods of locating a fault within an array of integrated circuits, methods of testing an array of interconnect modules, and speed fault test vehicles for locating a fault within an array of interconnect modules TWI369504B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/900,642 US7308627B2 (en) 2003-04-16 2004-07-27 Self-timed reliability and yield vehicle with gated data and clock

Publications (2)

Publication Number Publication Date
TW200612107A TW200612107A (en) 2006-04-16
TWI369504B true TWI369504B (en) 2012-08-01

Family

ID=36080762

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094119790A TWI369504B (en) 2004-07-27 2005-06-15 Methods of locating a fault within an array of integrated circuits, methods of testing an array of interconnect modules, and speed fault test vehicles for locating a fault within an array of interconnect modules

Country Status (2)

Country Link
CN (1) CN1738020B (en)
TW (1) TWI369504B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI567403B (en) * 2013-09-18 2017-01-21 台灣積體電路製造股份有限公司 Monolithic stacked integrated circuit, monolithic stacked integrated circuit known-good-layer path delay test pattern generation method, and monolithic stacked integrated circuit known-good-layer delay fault testing method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102855338B (en) * 2011-06-28 2015-04-15 重庆重邮信科通信技术有限公司 Field programmable gate array (FPGA) prototype verification device and method
JP6754954B2 (en) * 2016-02-18 2020-09-16 パナソニックＩｐマネジメント株式会社 Terminals, control methods for terminals, and wireless communication systems using these terminals
CN109143023A (en) * 2018-06-26 2019-01-04 北京中电华大电子设计有限责任公司 A kind of iddq test graphical design method being generally applicable to LSI

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5251228A (en) * 1989-12-05 1993-10-05 Vlsi Technology, Inc. Reliability qualification vehicle for application specific integrated circuits
US5674651A (en) * 1994-09-27 1997-10-07 Nikon Corporation Alignment method for use in an exposure system
KR19990053744A (en) * 1997-12-24 1999-07-15 김영환 Gate electrode formation method of semiconductor device
US6483176B2 (en) * 1999-12-22 2002-11-19 Kabushiki Kaisha Toshiba Semiconductor with multilayer wiring structure that offer high speed performance
JP3980827B2 (en) * 2000-03-10 2007-09-26 株式会社ルネサステクノロジ Semiconductor integrated circuit device and manufacturing method
KR100395880B1 (en) * 2001-09-11 2003-08-25 삼성전자주식회사 Test element group structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI567403B (en) * 2013-09-18 2017-01-21 台灣積體電路製造股份有限公司 Monolithic stacked integrated circuit, monolithic stacked integrated circuit known-good-layer path delay test pattern generation method, and monolithic stacked integrated circuit known-good-layer delay fault testing method

Also Published As

Publication number Publication date
CN1738020B (en) 2010-06-23
TW200612107A (en) 2006-04-16
CN1738020A (en) 2006-02-22

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