TWI356415B - Method of operating non-volatile storage and non-v - Google Patents

Description

IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION [0002] Embodiments in accordance with the present disclosure are directed to an array comprising a non-volatile memory cell array and, in particular, an array of passive component memory cells incorporated Circuit. [Prior Art] Materials having a detectable level change (e.g., a resistance or phase change) are used to form various types of non-volatile semiconductor based memory devices. For example, a simple antifuse is used for binary data storage in a field programmable (〇τρ) memory array by assigning a lower resistance initial physical state of a memory cell to a first A logic state (eg, logic "〇") assigns one of the higher resistance entity states of a single A to a second logic state (eg, logic Μ 1 Μ) Ο some material can be back in the direction of its initial resistance Switching its resistance. These materials can be used to form a rewritable memory cell. The material can be used to form a multi-state device that may or may not be rewriteable. The material of the recall effect (for example, a detectable resistance level) is often placed in series with the lead member to form a memory device. A diode or other device having a non-linear conduction current is generally used. Used as the guiding element. In many embodiments, a set of word lines and bit lines are configured in a substantially vertical configuration, and a memory unit is in the parent of each word line and bit line. Point. You can put two The memory unit of the terminal is constructed at the intersection of the terminal (eg, the terminal portion of the unit or the separated layer of the unit) and the conductor (4) forming the individual word line and the other terminal (4) 123008.doc 1356415 Conductor contact of individual bit lines. In such cases, when a non-volatile memory array having a passive element memory cell including a switchable resistive material or a phase change material is implemented as the state change element, 'read and Bias conditions during write operations are a factor to consider. When attempting to produce a memory device that includes one or more passive component memory cell arrays that can be reliably fabricated, programmed, and/or read. High leakage currents, program disturbances, read disturbances, etc. can cause difficulties. Φ For example, 'These factors often limit system performance by reducing the number of cells that can be addressed simultaneously to keep the leakage current at an acceptable level. Small differences between individual memory cells may also result when multiple cells are individually or simultaneously addressed for frequent bandwidth read and program operations Difficulties. A particular unit may have characteristics that may cause the resistance to exceed a range associated with a data state corresponding to one of the operations. For example, a particular unit may experience a different number than other units that are subject to the same bias conditions. Resistance Deviation. SUMMARY OF THE INVENTION The present invention discloses a reverse bias adjustment operation for a reset state of a non-volatile memory system. A non-volatile memory S-element including a resistance-changing element undergoes -& The M is re-stated to change the state of the 丨 resistor from one of the first resistance levels to one of the second resistance levels to reset the state. The specific memory cell depth is reset to exceed - the resistance level for the target level of the reset state. The second reverse bias is set to the memory cell set to re-set each depth of the cell The resistance moves toward the target level of the reset state of 123008.doc 1356415. A smaller reverse bias than one of the reverse offsets used for the reset operation may offset the lightning resistance of the cells toward the set level from their depth reset conditions.兮 The operation is self-limiting because the unit stops its resistance offset when it reaches the target level. Units that are not re-set in depth are not affected. In a specific embodiment, a method of operating a non-volatile storage is provided, comprising applying a first level of reverse bias to a plurality of non-volatile storage elements to store each storage element in a first direction The t-resistor moves from a first resistance state to a second resistance state. The method then includes applying a two-level reverse bias 1 to the plurality of non-volatile storage elements to: the plurality of storage elements having a resistance that exceeds a target resistance level for the second resistance state A resistor of a subset moves in the second direction toward the target resistance level. In a specific embodiment, a method of operating a non-volatile storage is provided, comprising applying a storage element from a lower portion by applying a first level of reverse bias to a plurality of non-volatile storage elements The resistance state is switched to a higher resistance state. Applying a second level of reverse bias to the storage elements after switching, "reducing a subset of the storage elements having a resistance corresponding to a target level of the second resistance state" One resistance. In one embodiment, a non-volatile memory (four) system is provided, comprising a plurality of non-volatile storage elements having i less than one resistance changing element and a control circuit in communication with the plurality of non-volatile storage 5 elements. The control circuit performs a reset operation, comprising: setting the storage elements from a lower resistance by applying at least one reverse bias voltage to the plurality of sigma storage elements to reset the voltage Resetting the state to a higher resistance reset state; and applying at least the "non-voltage" adjustment voltage to the plurality of non-volatile storage elements, having a s-out for the second higher power. The history of one of the target values of one of the plurality of non-volatile storage resistors is one of a subset of the resistance values. * [Embodiment] Figure 1 illustrates an exemplary structure that can be used in accordance with one embodiment of the present disclosure for a non-volatile 5 memory unit. A two-terminal memory unit 100 as shown in Fig. i includes a first terminal portion connected to one of the first conductors 1 and a second terminal portion connected to a second conductor 112. The memory unit includes a boot device 102 in series with a state change element 104 and an antifuse 106 to provide non-volatile data storage. The guiding element can take the form of any suitable device (e.g., a simple diode) that exhibits a non-linear conduction current characteristic. The state change element will vary with the particular embodiment and may include many types of materials to store data via a representative entity state. The state changing element 104 may include a resistance change material, a phase change resistance material, or the like. For example, in one embodiment a passive storage element is formed using a semiconductor or other material having a detectable resistance change of at least two levels (eg, from low to high and from high to low). Hey. The memory unit 1 can provide reliable data read/write capability by assigning logic data values to various levels of resistors that can be set and read from the resistance change element 104. The anti-fuse 106 can further provide a resistance state change capability that can be utilized for non-volatile data storage. The anti-solving wire system is made of 123008.doc 丄356415. It is still in a state of resistance and can be tripped or dissolved into a lower resistance state. The antifuse is generally non-conductive when in its initial state and exhibits high conductivity under low resistance conditions in its tripped or fused state. Since a discrete device or component can have a resistance and a different resistance state, the term resistivity and resistivity states are used to indicate the properties of the material itself. Therefore, the resistance changing element or device may have a resistive state, but a resistivity changing material may have a resistivity state. • The anti-fuse 106 can provide the memory unit 1 with the advantage of exceeding its state change capability. For example, an anti-fuse can be used to set the on-resistance of the memory cell to an appropriate level relative to a read write circuit associated with the cell. These circuits are typically used to trip the antifuse and have an associated resistance. Since the circuits drive voltage and current levels to trip the antifuse, the antifuse tends to set the memory cell to an appropriate turn-on resistance state for one of the same circuits during subsequent operations. . It should be understood that other types of two-terminal non-volatile memory units can be used in a particular embodiment. For example, a particular embodiment does not have an antifuse 106 and only includes state changing element 1〇4 and guiding element 1〇2. Other embodiments may include additional state changing elements as an alternative to the antifuse • element or additional element. Various suitable memory cells are described in U.S. Patent No. 0,034,882, the entire disclosure of which is incorporated herein by reference. A variety of other types of single 7L can be used, including those described in the following patents: U.S. Patent No. 6,420,215 and U.S. Patent Application Serial No. 9/897, the entire disclosure of which is incorporated herein. A three-dimensional memory array of a chained diode stack is applied at 123008.doc, June 29, pp. 1556415, and U.S. Patent Application Serial No. (4) 560 626, /. The present invention is incorporated herein by reference in its entirety. The resistivity change characteristic of 7〇1〇4. Suitable for the change of resistance state 7L parts of 1G4 include, but not limited to, doped semiconductors (eg 'polycrystalline II', @ __ Polycrystalline) 'transition metal oxides, composite metal oxides, programmable metallization junctions, phase change resistors, organic material variable resistors, carbon polymer films, doped chalcogenide glasses, and contain varying resistance Action of the atomic Schottky (Sch〇t (four) barrier diode. In some cases τ, the resistivity of these materials can be set only in a first direction (for example, from high to low), while in other In this case, the resistivity can be set from a first level (eg, higher resistance) to a second level (eg, a lower level) and then reset back to the first resistivity level. A range of resistance values can be referred to Give an entity data status to accommodate differences between devices and changes in the device after setting and resetting cycles. The term setting and resetting are generally used to indicate that a component is changed from a high resistance solid state to a low resistance. The physical state (set) and the procedure for changing the component from a low resistance physical state to a high resistance physical state (reset). Embodiments in accordance with the present disclosure may be used to set the memory cell to a lower resistance state Or set the memory unit to a higher resistance state. Although a specific specification can be provided with respect to the setting or resetting operation, the example is only an example and the disclosure is not limited by this example. The conductors 110 and 112 are generally orthogonal to each other to form an array termination line for accessing a memory cell array 100. The array termination lines (also referred to as array lines) in one layer may be referred to as word lines or X. Line "Array lines in a vertical adjacent layer may be referred to as bit lines or Y lines. A memory cell may be formed on each word line and each bit line. The convex intersections are connected between the individual cross-character lines and the bit lines (as shown for the formation of the memory unit 100 in the figure). There are at least two memory unit levels (ie, two memories) Body plane) A three-dimensional memory array can utilize more than one word line and/or more than one bit line. A single-crystal three-dimensional memory array is formed on a single substrate (eg, a wafer) An array of multiple memory levels, with no intervening substrates. Figures 2A and 2B are more detailed illustrations of exemplary memory cells that may be used in various embodiments. In Figure 2A, in the first and second metals A memory cell 120 is formed between the conductive layers 110 and 112. The memory cell includes a pin-type diode having a heavily doped n-type region 122, an intrinsic region 124, and a heavily doped p-type region 126. In other embodiments, region 122 may be p-type and region 126 is n-type. Region 124 is essentially 'or not intentionally doped' but in some embodiments it may be lightly doped. The undoped regions may not be excellent in electrical neutrality, but defects, contaminants, etc., which cause their properties to be as mild as η doping or p doping. We still consider this one-pole as one of the essential intermediate layers of p_i_n type dipole. Other types of diodes can also be used, such as junction diode 123008.doc -13 - a solution-dissolving filament 128 between the doped p-type region 126 and the conductor 110. The anti-fuse 128 exhibits substantially non-conductive characteristics in its initial state and exhibits substantially conductive characteristics in its set state. Various types of antifuse can be used in accordance with specific embodiments. Applying a large bias across the antifuse in a generally fabricated antifuse will fuse the forming material such that the antifuse becomes substantially electrically conductive. This operation is generally referred to as tripping the antifuse. The memory unit 120 further includes a state changing element formed by one or more of the diodes. It has been found that the material used to form the diode in some memory cells exhibits a resistance change capability. For example, in one embodiment, the essential region of the diode is formed of polysilicon, which is shown to have a lower resistivity state from a higher resistivity state and then from the lower resistivity state. Set the ability to return to a higher resistivity state. Therefore, the one body itself or a part thereof can also form the state changing element 104 as shown in FIG. In other embodiments, one or more additional layers may be included in memory unit 120 to form a state change element as shown in FIG. For example, an additional layer of polysilicon, a transition metal oxide, or the like as described above may be included in the cell to provide a state change memory effect. This additional layer may be included between the diode and conductor 112, between the diode and the antifuse 128 or between the antifuse and conductor 110. Figure 2B illustrates a simple memory unit configuration in which no anti-solvent filaments 128 are present. The memory unit 140 includes only heavily doped regions 丨 42, 123008.doc -14 - 1356415, an intrinsic region 144, and a heavily doped p-type region 146. The memory effect of the diodes formed by the regions or the layers formed by such regions is as described in ±. In a particular embodiment, the memory unit (10) may also include other layers to form additional state changing elements for one of the units.

Figures 3A through 3B illustrate portions of an exemplary single stone three dimensional memory array that can be used in an embodiment. However, other memory structures can be used in accordance with various embodiments, including two-dimensional memory structures fabricated on, above, or within a semiconductor substrate. However, the word line and bit line layers are shared between the memory cells in the structure illustrated in the perspective of Figure 3A. This configuration is often referred to as a fully mirrored structure. A plurality of substantially flush and coplanar conductors form a first set of bit lines 162 at a first memory level L. A memory cell 152 at level L0 is formed between the bit lines and adjacent word lines. In the configuration from the figure to 3B, the word line 164 is shared between the memory layers 10 and L1, and thus further connected to the memory unit 17A at the memory level L1. A third set of conductors forms a bit line 174 for the cells of level L1. These bit lines 174 are in turn shared between the memory level L1 and the memory level [2, as illustrated in the cross-sectional view of Figure 3B. The memory cell ι78 is connected to the bit line 174 and the word line 176 to form a third memory level L2, and the memory unit 182 is connected to the sub-element 176 and the bit line 18A to form a fourth memory level L3. And the hex memory cell 186 is connected to the bit line 180 and the word line 184 to form a fifth memory level L5. The configuration of the polarities of the diodes and the individual configuration of the word lines and bit lines can vary from embodiment to embodiment. In addition, more or less than five memory levels can be used. 123008.doc • 15· 1356415 If a p_i_n diode is used as the guiding element of the memory cells in the embodiment of FIG. 3A, the diode of the memory cell 17 can be relative to the first level. The pin diode of the memory cell 丨52 is formed upside down. For example, if the cell 152 includes an n-type bottom heavily doped region and a doped top heavily doped region, the bottom heavily doped region may be p-type and the top is severe in the second-level cell 丨7〇 The doped region is n-type. In an alternate embodiment, an interlevel dielectric can be formed between adjacent memory levels. No conductors are shared between memory levels. Such structures for three-dimensional single stone storage memories are often referred to as a non-mirror structure. In some embodiments, adjacent memory levels of shared conductors and adjacent memory levels of unshared conductors may be stacked in the same single-crystal three-dimensional memory array. In other embodiments, some of the conductive systems are shared while other conductors are not shared. For example, only some of these word lines or only those bit lines can be shared in some configurations. A first memory level L〇 may comprise a memory cell between a bit line level BL〇 and a word line level WL〇. The word lines at level WL0 may be shared to form a unit connected to a second bit line BL1 at a memory level L1. The bit line layers are not shared, so the next layer can include an interlevel dielectric to separate the bit line BL1 from the next level of conductor. This type of configuration is often referred to as semi-mirror. The memory levels do not have to be formed to have the same type of memory unit. If desired, the memory level of the resistor-changing material can be alternated with the memory level of other types of memory cells. In one example, as described in U.S. Patent No. 7,054,219 (the name is "Transistor Layout Configuration for Closely Spaced Memory Array Lines), in the example of 123008.doc •16·1356415, the use of The words on the different word line layers of the array form a word read. It can be made into a different word line. Each word line is resident = the segments are connected to form a 70 line body that resides on the separation layer and substantially The sub-line of the vertical alignment (although there are some offsets on some layers) can be collectively referred to as a - column. The word lines in a column preferably share the column. At least a portion of the address. Similarly, the individual lines reside on a separate layer and are substantially vertically aligned (again, although there is a small lateral offset on some layers) - the group of bit lines can be collectively referred to as - Preferably, the bit lines in the row share at least a portion of the row address. Figure 4 is a block diagram of one of the integrated circuits including a memory array 2〇2. Lines consist of columns of columns and columns organized into columns The integrated circuit 200 includes a column control circuit 220, and the output 2〇8 of the column control circuit 22 is connected to individual word lines of the memory array 202. The column control circuit receives a group M column address signals and one or more various control signals, and may generally include both read and write (ie, stylized) such as column decoder 222, array terminal driver 224, and block selection circuit 226. The integrated circuit 200 further includes a row control circuit 21, and the input/output 206 of the row control circuit 21 is connected to individual bit lines of the memory array 2〇 2. The row control circuit 206 receives A group of row address signals and one or more various control signals, and generally may include, for example, a row decoder 212, an array terminal receiver or driver 214, a block selection circuit 216, and a read/write circuit and Circuits such as /O multiplexers, such as column control circuit 220 and row control circuit 210, may be collectively referred to as control circuits, or as they are connected to respective array terminals of memory 123008.doc 17-1356415 body array 2G2 (Iv) a column termination circuit.

The integrative-integrated circuit of the memory array generally subdivides the array into a sometimes larger number of sub-arrays or blocks. The blocks can be grouped into blocks containing, for example, 16, 32 or a different number of blocks. In the case of common conditions, a sub-array is a continuous group of memory cells with consecutive characters and bit fields that are generally not broken by decoders, drivers, sense amplifiers, and input/output circuits. This is done for any of a variety of reasons. For example, signal delays (i.e., RC delays) that traverse along the lines due to the resistance and capacitance of the word lines and bit lines can be quite significant in a large array. These RC delays can be reduced by subdividing a larger array into a smaller group of sub-arrays such that the length of each word line and/or each bit line is reduced. As another example, the power associated with accessing a group of memory cells can indicate an upper limit on the number of memory cells that can be simultaneously accessed during a given memory ring. Therefore, a larger memory array is often subdivided into smaller sub-arrays to reduce the number of memory cells accessed simultaneously. However, for convenience of explanation, the array can be used synonymously with the sub-array to indicate that there is a general cause. A continuous group of memory cells separated by a decoder, a driver, a sense amplifier, and an input/output circuit. An integrated circuit can include - or more than one memory array. Figure 5 is a graph illustrating a resistance distribution for a state of a set of memory cells in a non-volatile memory system, in accordance with an embodiment. The exemplary memory system depicted in FIG. 5 utilizes four resistive dimensions, but may be combined with a system utilizing different numbers and/or combinations of resistive states. 123008.doc -18-1356415 uses specific embodiments in accordance with the present disclosure. Line 250 is used to illustrate the original (or initial) state of the set of memory cells. The resistance distribution for the cells in their initial state after fabrication is shown as a function of the probability of the conduction current of the cell at a selected voltage bias (e.g., 2 V). The original state of the cells after fabrication is a relatively high resistance state having a conduction current of about 1 〇 -1 ϋΑ to 1 〇 -9 a at the selected voltage. One of the trip states of the device is illustrated on line 252. State 252 corresponds to one of the lowest resistance states of the device. The device in state 252 exhibits a conduction current of about 1 〇 -5 a at the voltage level of 2 V as illustrated in Figure 5. In a specific example, the memory cell can be set from its initial state of resistance to the lowest resistance trip state by tripping an antifuse. In other embodiments, the resistivity of one of the resistance change materials, such as polysilicon or a metal oxide, can be switched to set the unit to the lower resistance cancer. In one embodiment, tripping an antifuse to set the device to one of the trip states as illustrated by line 252 includes applying a greater forward bias to the cells, such as about 8 volts. Other techniques, bias conditions, and/or voltage leveling lines 254 may also be used for such operations to indicate that the lower resistance state illustrated by line 252 is reset to a higher resistance reset state for the set of memory cells. After the resistance distribution. The memory cell in this reset state exhibits a conduction current of about 10, to 1 〇 - at the applied 2V voltage level. The reset state is at a lower resistance than the higher resistance initial state, but may be at a higher resistance in other embodiments. In a particular embodiment, a reverse bias reset operation as described below can be used to reset the resistance of the memory cell from state 252 to state 254. For example, in one embodiment, the resistivity of one of the tenth resistivity changing materials can be increased by subjecting the memory cells to one of a reverse bias of about -10V to -12v. • Line 256 indicates one of the memory unit setting states. The memory 'body unit can be set from its higher resistance reset state 254 to a lower resistance set state 256. The memory cell in the set state 256 has a conduction current of about ι 〇 6α at the applied voltage level of 2V. The individual resistances in the set state 256 are more south than the resistance of the cells in the tripped state 252 but lower than the resistance of the cells in the reset state 254. In one embodiment, a resistance of a memory cell can be switched from a reset state 254 to a set state 256 using a forward bias of about +8 乂. In other embodiments, other bias conditions and/or voltage levels can be used to set the memory cells. The four resistance states illustrated in Figure 5 can be used to form various types of memory systems. In one embodiment, the reset state transition is used to perform a stylized operation in the secondary programmable memory array. One of the memory change cells is connected to the memory cell from the initial state 25 〇 factory • set to the lower resistance state 252. The memory and body array including the memory unit are then provided to the end user. The lower resistance state obtained by setting the cell from its higher resistance initial state during manufacture is for a formatted or unprogrammed state of the cell. The memory array is provided to circuitry to reset the selected memory unit to a higher resistance state 254 in accordance with data received from an end user or host device in communication with the memory unit. In another embodiment, the four resistance states are used to form a multi-state memory system. The memory unit can be programmed from the initial state 250 to any of the states 252, 254, or 256 (or retained in state 250) based on the user profile. In one such embodiment, each unit can store a 2-bit data. In another embodiment, a rewritable memory system can be formed. The cell can be set to state 256 and then reset multiple times back to state 254 to form a one-bit rewritable array. Other types of memory systems may also be used in accordance with specific embodiments, including, by way of non-limiting example: US Patent Application No. __ (MD-294Y, attorney docket number 10519.141), entitled "" "Usage memory unit and memory array"; US Patent Application No. 1 (MD-296Y lawyer file number 10519·142), whose name is "mixed memory array"; US patent application No.-- - (MD_31〇Y lawyer file number 10519-149), whose name is "mixed memory array with different data status"; and US patent application number -_ (lawyer file number MD · 163- υ, the name is " using a memory cell containing one of the switchable semiconductor memory elements with adjustable resistors, ^ for reading, setting or resetting (4) and biasing the two terminal memory banks = array 'can Generating program disturb, read disturb, and high leakage power that may affect the power consumption and the reliability of such read and program operations: for example, when selecting a particular memory bank within an array When stay for a particular order, these conditions may cause unintended bias via the unselected memory 123008.doc • 21 1356415 of earlier% & Although the leakage current in the memory array guide element.

Under the condition of line-to-character line configuration, a low voltage or ground condition is applied to a selected word line by applying a -large voltage to the selected bit line to generate a larger positive The unselected bit line of bias voltage 6 can be at a relatively small positive bias and the unselected word line is under the condition of the memory array, with the selected word line or bit green being a large positive bias. Bias in this manner may, in some cases, be present via a cell selected along the half of the < 疋 元 线 or bit line and via unselected cells along an unselected word line and bit line Unacceptable level current leakage. Similarly, an unacceptable level of leakage current may occur during a forward bias setting operation (which can be used to program a memory cell array). The number of selected memory cells that are operational at a time is limited by the cumulative effect of the smaller leakage current of the unselected cells. It has been found that a reverse bias can be applied to a memory cell having a resistance changing element to change the detectable resistance of one of the cells. For example, such materials can be reset from a lower resistivity state to a lower voltage by subjecting a material such as the above-described metal oxide, polysilicon, to a voltage pulse that produces a reverse bias across one of the materials. High resistivity state. In a specific embodiment, a reverse bias is applied during a reset operation to minimize leakage current through the memory array. In some embodiments, an essentially zero bias voltage can be provided to a particular unselected memory bank 123008.doc -22. Since these 4/1 current systems are minimized, a larger number of memory cells can be selected to recognize the *β in the reset operation. This is improved by reducing the stylization and/or erasing time. In addition, these low leakage currents can be promoted by normalizing the performance of the service unit to the expected level.

Awkward operation. The name is " incorporated into the reversible polarity of the word line and the bit line decoder of the Youxu - / 1L scatter device memory array • • US patent application No. 0 -1 ~ --~~~~ (MD-273 attorney docket number 023-0048) discloses a reverse bias operation that can be used to minimize leakage current through unselected and semi-selected memory cells. Figure 6 is a circuit diagram of a portion of a memory array during a reverse bias operation in accordance with an embodiment. These reverse bias conditions can be used to set the memory cell to a low resistance state or to reset the memory cell to a high resistance state. A specific reference to a reset operation may be made below for convenience', but this does not indicate one of the biases and techniques disclosed in the application. One or more selected word lines are at a positive bias and one or more selected bit lines are at a negative bias voltage. For example, the selected word line can receive one of +1/2 VRR to reset the voltage signal Vwr And driving the selected positioning element line by resetting the voltage signal VBR with a negative bias of about -1/2 VRR. * VRR is the number of reverse bias (or negative voltage) required to reset the memory and can It varies depending on the specific embodiment. In an exemplary embodiment, the VRR is about 12V such that the selected word lines receive +6V and the selected positioning lines receive -6V to produce a 12V reverse bias level. Unselected word lines and bit lines are grounded. The guiding elements for the selected memory cells (denoted S) are reverse biased, allowing a reverse current to pass through 123008.doc • 23· 1356415

'Please see US Patent Application No.* — _ Teacher's Standard No. 023-0048, whose name is "Incorporated and Bit Line Decoder's Passive Component Memory Array Used for Resistance Change of These Selected Units material. Under this reverse bias condition, the resistance change material switches from a first resistance state to a second resistance state. The bias conditions illustrated in FIG. 6 are advantageously provided for the unselected cells (denoted as U). A zero bias condition. Thus, low leakage current through unselected and semi-selected memory cells during program operation can be obtained. ? Represents a memory cell selected along half of a selected bit line, and n represents a selected memory cell along a half of a selected word line. In addition, the selection of +/· 1 /2 VRR for the selected array lines requires a smaller load on the driver circuit to create the voltage level for the reverse bias reset operation. By dividing the bias voltages across the array lines using positive and negative voltage levels, the driver circuit only needs to produce one-half of the total voltage level required in certain embodiments. Other bias conditions can also be used to reverse bias the selected memory banks 7L for a reset operation. For example, in one embodiment, a positive voltage bias (e.g., 'vRR) can be applied to selected ground and selected bit lines of ground. Unselected characters and bit lines can each receive + 1/2 VRR. This biasing condition will also provide a reverse bias to the selected memory cells that can be used to reset the cells back to a higher resistance state after a set operation. Regarding the reverse bias operation, more resources - _ (MD-273 law reversible polarity character line may be in a memory cell array in some memory implementation state, for one in a reset The resistance distribution may be too wide or include 123008.doc • 24· 1356415 . A larger range of resistance than the desired range. For example, the resistance of the memory cell in the reset state shown in line 252 of Figure 5 The distribution includes a relatively large range of resistance. Some memory cells exhibit a conduction current of about ι 〇 8α at the applied voltage level, while other memory cells in the same physical state exhibit about 1 〇. One of the large conduction currents of -7a. This 'constant conduction current proves that there is a large difference in resistance between the single elements that are expected to be in the same reset physical state. The important system is that the depth is reset to a very high The memory cells of the resistor (the memory cells that are closer to a 10-8A conduction current) do not have a wider separation from the memory cells in the original or initial state 250. In some embodiments The lack of limits between these two entity states may prove problematic during read and write operations. A larger range of resistance may result in erroneous readings of data stored in the memory cells. For example, depth A unit that is reset to a very high resistance may not conduct sufficiently when a read reference voltage is applied, thereby indicating that it is in a reset physical state. It may be mistaken for the unit's initial or original state. During other operations, such as stylization, these cells may be incorrectly read during a verification step, resulting in an erroneous application of an additional stylized voltage that may not be needed. • According to a particular embodiment, - adjustment The operation system is used for or the person-reset ▼ (operation to provide a more J resistance knife for the memory unit in the -reset state. An adjustment bias can be applied to the memory unit after resetting it. Units that are associated with the re-settable S—required or target=quad offset back to depth. After resetting, have more than 1 level The memory cell of the resistor can have its resistance reduced to match more closely with other cells in the reset state at 123008.doc -25 - 1356415. A self-limiting reverse bias adjustment operation is used in the specific embodiment. It has been found that applying a small reverse bias to the memory cell increases its resistance without reducing its resistance as if a large reverse bias was applied to the reset operation. Figure 5 illustrates a The reverse bias adjustment operation is used for the effect of a reverse bias reset operation. Line 258 represents one of the target resistors of the memory unit in the reset state 254 (or a resistor material having a different average resistance) may be used. The individual characteristics provide different target resistance levels. The target resistance for this reset state can be determined by such characteristics that tend to indicate a resetting level of one of the materials in the most natural case. A certain number of cells have their resistance lower than the target level in Figure 5, while other cells have their resistance above the target level. A reverse bias is applied that is lower than the reverse bias reset level ν(10), resulting in a memory cell having a resistance higher than the desired level 258 being shifted to a lower resistance. It has been found that a relatively small number of reverse biases reduces the resistance of the material in a self-limiting manner. A cell having a resistance at or above a particular level will increase its resistance when subjected to a small reverse bias. However, cells below this particular resistance level are not affected by this reverse bias. In an embodiment, it has been shown that a level in the range of one of the reverse biases has a similar effect on the cell resistance. For example, a reverse bias of about 10V to 12V during a reset operation from state 252 to state 254 can increase the resistance of a selected memory cell by an amount as shown in FIG. A reverse bias equal to one of the reverse bias applied during the reset operation of about 5〇% to 6〇0/〇 (eg, 123008.doc -26-1356415, eg, 6 V to 7 V) can be used Increasing the resistance of a particular memory cell in the memory cell that has a higher resistance than a particular level. The increase in resistance in this adjustment operation is self-limiting because the cells stop reducing the resistance when the number of resistors is reached. In addition, only those cells that are still at a critical level of resistance are affected by the adjustment operation. A cell that is already in the proper resistance range does not experience a resistance offset, even if it is subjected to the reverse bias regulation voltage. Thus, the cells having a resistance below the target level 258 as shown in Figure 5 are unaffected by the reverse bias for the adjustment operation. Figure 7 is a circuit diagram showing one of the reverse bias adjustment operations for a non-volatile memory system reset state in accordance with an embodiment. An adjusted voltage signal Vwt is supplied to one or more selected word lines at a positive voltage level + vTT to apply a reverse bias for the adjustment operation. In a specific embodiment, the VTT is the amount of reverse bias applied to the selected cells during the adjustment. In the biasing case shown in Figure 7, the selected bit line is grounded, thus applying a full amount of adjustment bias to the selected word line at +VTT to produce one of the same number across each selected Reverse bias of the unit. In one embodiment, the number of adjusted reverse bias voltages Vtt is equal to about 6% of the total reverse reset bias level of VRR. Continuing with the above example, if the reverse bias reset potential is equal to about 12 V, the reverse bias adjustment level VTT can be about 6 or 7 乂. Thus, in a particular embodiment, +6 V or +7 V is applied to the selected word lines. Other bias conditions can be used for an adjustment operation in accordance with one or more embodiments of the present disclosure. For example, in one embodiment, a voltage of +1/2 Vtt is applied to the selected word line and one of -1/2 Vtt is applied to the selected bit line to 123008.doc -27. What about electricity? The reverse bias generated across each cell is the same as previously described (Vtt), however, individual biases have been distributed across different types of array lines. Since only those units requiring resistance offset are affected by the reverse bias adjustment, the operation and the data are not "can be implemented for high frequency wide applications. In a specific embodiment, a high frequency operation is used. To adjust the memory cells of a group A at the same time. In an example, each bit line of the memory cell block is selected for the adjustment operation at one time. Select one of the word lines from the block and target The operation is repeated for each word line. In addition, multiple blocks within an array can be simultaneously selected during the adjustment operation, but in a single embodiment, a single block is selected. With this technique, one-time adjustment A large number of units may not have an unreasonable effect on the bandwidth of the reset operation. In other embodiments, other groups may be used. In a particular embodiment, multiple locations from across the array may be selected. a line and one or more word lines. & Figure 8 is a flow diagram of a method for resetting a memory unit in accordance with an embodiment incorporating a reverse bias adjustment operation In step ', the column and row control circuit for the array of 5 memory cells receives the address and control element of the selected unit that is specified, and is reset. For example, a rewritable array 1 is received for the One of the selected cells erases the request, * can receive - write the request in the multi-state array. Receiving the write or erase request can include resetting the selected cells as shown. In step 302, The reset unit applies one or more reset 123008.d〇<28. 1356415 constant voltage pulse signals. A new voltage is used to set the bias voltage on the line. For example, vWR can include a positive voltage pulse (eg, voltage signal Vbr) Including a negative voltage pulse (eg, the reverse weight can be applied across the selected cells by the selected characters and bit combinations as described above) - in particular embodiment t, the word line voltage signal is selected Unit +1 /2 vrr) and the bit line '4/2 VRR' is reverse biased in step 304. If there is still a memory unit to be reset, the method returns to apply - (or more Extra pulse, or, if The unit to be reset has received a message. The signal voltage continues to step 3〇6. In a specific embodiment, the smaller part of the array can be subjected to individual The pulse is set to minimize leakage current through the line of semi-selected or unselected Cuiyuan. For example, in one embodiment, each iteration of steps 3〇2 and 3〇4 can be from the memory. Many racks (for example, "to 2024 racks or more" - each rack - (or in more than one other) blocks apply a pulse until each selected location line has been received A reset voltage pulse is reset. In other embodiments, other numbers of bit lines and/or word lines may be selected in step 302. U.S. Patent Application Serial No. (MD-303 attorney docket number 023-0052) entitled "Incorporating Memory Arrays for Two Data Bus Arrays for Memory Array Block Selection" and entitled "" U.S. Patent Application Serial No. (MD-307 attorney docket number 023-0053) for a block selectable memory array is described for use with a memory array ( For example, array 302) performs techniques for increased parallel access. 123008.doc • 29- 1356415

After applying a reverse bias voltage pulse to each selected memory cell, a verify operation is performed by reading back the resistance states of the devices in step 306. Step 306 can include determining whether the resistance of a memory cell has increased to be at or above a minimum critical resistance. Various techniques, including sensing the current or voltage of a selected cell under a set of reference bias conditions, can be used in step 3-6 to determine whether to fully reset a memory bank 70. The name is " used to read a multi-level passive component memory cell array

The device "US Patent Application No. __ Division File Number 023-0049) describes the appropriate reading technique that can be used to have the ---_ number (MD-274 law read back operation verify the reset state). In step 3-8, the resetting operation is performed for the bit lines having the memory cells that are not fully reset. In the optional step 310, the characters and/or bits are utilized.

The memory cells of the line voltage signals VWR &amp; VBR apply a retry pulse. In a particular embodiment, the pulse is applied simultaneously to individual bit lines having a memory unit that is not sufficiently reset. Individual pulses can be applied using various groups of the bit lines. In a particular embodiment, no retry pulses are applied. If the - retry pulse is used, it is targeted in step 3. The unit performs the verification operation. If it is determined in step 3 &quot; that the unit is not fully re-established, the error correction code is used in the step to replace the early elements or replace them with redundant memory units. The reset voltages applied in steps 302 and 314 may therefore have been reset to a high resistance state as described above. The tighter resistance distribution for the I-heavy U state will provide a greater limit between the states and thus provide a more reliable device. Therefore, after successfully verifying the unit in steps 308 and 3U or after disposing of any unit that has not been reset in step 316, an adjustment operation is performed for the emerald to be reset in step 3 (4). t. In the specific embodiment, for each unit undergoing the reset operation. - (d) Step 318 is performed. Since this operation is self-limiting, it is also possible to subject the unit that is not fully or deeply reset to the adjustment bias without negative effects. These units do not experience the resistance offset of the advance step. In addition, the cells adjusted to a lower resistance will stop their resistance change when they reach a level associated with the adjustment bias. As described above, in a specific embodiment, a reverse bias voltage VTT is applied to the cells. A small amount of reverse bias is applied in a particular embodiment to reduce the resistance during an adjustment operation rather than increasing the resistance during a reset operation. After the reverse bias adjustment voltage VTT is applied to each cell, the reset operation is completed in step 320. Many variations can be made to the method illustrated in Figure 8 in accordance with a particular embodiment. For example, the adjustment operations in step 318 may be incorporated after steps 302 and 307 are completed for all of the reconfigured units and before verification is performed in step 306. </ RTI> Figure 9A illustrates one embodiment of a portion of the control circuit 220 that can also be used to apply the reverse bias reset conditions of Figure 6. Column decoder 422 corresponds to a selected word line during the reset pulse and outputs a ground to the NMOS/PMOS word line driver circuit (e.g., 224 in Figure 4). The upper PM 〇s devices 402 and 404 are turned on for the ground input of the driver circuit. The ground input causes the driver circuit to pass the reverse source 12300S.doc • 31· 1356415 select bus signal VWR and GND to the selected word line and each semi-selected word line associated with decoder 422, respectively. Each column decoder 423 corresponding to an unselected word line outputs VwR to its individual driver circuit as shown in Figure 9B. The positive bias of VWR turns on the NMOS devices 416 and 418 of the driver circuits of the unselected word lines. Accordingly, the source select bus level (both GND) is selected and driven on each corresponding unselected word line. In one embodiment, the word line reverse reset voltage VWR is equal to about +1/2 VRR as previously described. VWR can also provide other voltage levels. For example, one or more reverse reset voltage pulses having a tilt pulse (e.g., start K + 1/2 Vrr and then increase) can be provided for the reset operation as described below. 10A and 10B are circuit diagrams of portions of a row control circuit 210 that can be used to apply bias conditions for the reverse reset operation. Row decoder 5 12 controls a selected bit line driver to provide the selected bit line voltage pulse VBR. In one embodiment, the vBR provides a voltage pulse of _1/2 Vrr. Row decoder 512 may be shared across a plurality of bit line drivers (e.g., 24) and will also connect the semi-selected bit lines to a ground bias just prior to application of the reset pulses. During the application of the pulse, the semi-selected bit lines float near ground. A plurality of unselected cells on the semi-selected bit line provide a leakage current that causes the semi-selected bit line to remain close to ground. In one embodiment, a row of decoders is shared with the selected bit line during a reset operation. The memory unit can be a half-selected memory unit "e.g., the unit can be connected to the selected word line during the reset operation. The selected row decoder 512 outputs gnd 123008.doc -32 - 1356415 to the input of the driver circuit for the row decoder. The GND input at the NMOS/PMOS pair of the driver circuit will turn on the lower NMOS device 506. The reverse source select bus level VBR is passed to the selected bit line. The unselected column decoder 513 provides VBR to the gates of its individual driver circuits to select the PMOS device at the top of each driver pair. The source select bus signal levels (both at GND) are provided to each unselected word line corresponding to decoder 513. Figure 11A illustrates one embodiment of a portion of a column control circuit 220 that can be used to apply the reverse bias adjustment conditions of Figure 7. The selected column decoder 422 outputs a word line adjustment voltage pulse VWT to the NMOS/PMOS word line driver circuit. Vwt is a positive voltage and turns on the lower NMOS devices 406 and 408. The driver circuit passes the source select bus signal VWT to the selected word line. Each unselected column decoder 423 outputs GND to its individual driver circuit as shown in Figure 11B. The upper PMOS devices 412 and 414 are turned on and the GND signal from the reverse source select bus is passed to each of the unselected word lines. Figure 10A is a circuit diagram of one portion of a row control circuit 210 that can be used to apply bias conditions for the reverse bias adjustment operation. The selected row decoder 5 12 controls a selected bit line driver, turns on the upper PMOS devices and passes GND to each bit line selected for the reset operation. This adjustment operation is independent of the data, and a large number of units can be selected at one time under the self-limiting condition of the operation. Thus, each bit line in a selected block receives the GND level signal to apply the reverse bias to adjust the voltage level. 123008.doc -33- 1356415 The driver circuit associated with the column and row decoders illustrated in Figures 9A through 10B may include additional NMOS/PMOS device pairs forming driver select circuits for additional word lines and bit lines . For example, each driver set for the column control circuit can include 16 NM 〇 s / pM 〇 s for the 16 . NM 〇 S / PMOS pairs are connected to the 16 different word lines of the array and Department • Associated with a single column decoder. Each driver set for the row control circuit can include 12 NMOS/PMOS pairs that are connected to the 12 different word lines of the array and tied to a single The row decoder is associated. This configuration is exemplary and other configurations may be used depending on the particular embodiment. However, this set of states as described above can advantageously provide a reasonable fanout of one of the array lines at each memory level. It also facilitates placing the driver circuit at the same distance from the array lines associated with the driver circuit. In addition to adapting to a large number of array lines, this configuration avoids the long-distance transmission of various driver voltage levels to the array and thus improves power efficiency. More details regarding the driver and control circuitry used to control a memory array (including, in one embodiment, one of the choices for implementing selected and unselected characters and/or bit lines associated with the data) "Double busbar architecture" can be found in R0y E. Scheuerlein and Luca G. • Fasoli's US Patent Application No. ____ (MD_295 attorney number 023-0051), whose name is &quot;for reading The / write circuit is coupled to a data-dependent dual bus of a memory array. The difference in device characteristics can affect the characteristics of individual memory cells within the memory array 202 during a reverse reset operation as described. The sensible unit can have different sizes due to the process. The device is between 123008.doc • 34- than 6415.

The composition of the material (for example, polycrystalline stone 姑 M M can be caused by this," the fish may lack specific uniformity. Guided by the money - the nominal level of the flat element compared to the standard, &gt; A lower power (1). According to the disclosure of the present invention, in a higher embodiment, the memory cell array (including individual memory singles) is fully re-defined. Between the changes, the 'applied to the selected memory cell of the array during the reset operation, the &gt; t-shift pulse has an amplitude with a varying slope, thereby

The reverse bias applied to the selected memory cells is gradually increased. A unit that requires a large reset voltage level will be reset to a higher reverse bias after the amplitude of the voltage pulse has changed, and only the lower-reset unit that resets the dust level will be reset. A smaller level of reverse bias. This technique accommodates changes between devices while also providing an efficient procedure for one of the devices that does not compromise resetting. Since a single reset voltage pulse can be applied to generate a reverse bias reset condition range, time consuming verify operations are avoided or minimized. The single pulse can be applied across each cell and the amplitude changes to increase the reverse bias. The cell reset at the lower value of the reset voltage pulse will automatically turn off when it is reset to the higher resistance state. The higher resistance after reset will reduce or stop the current flow through these devices' to ensure that it is not damaged by the higher value of the reset voltage. Figures 13A through 13B illustrate re-voltages applied to selected word lines and bit lines, respectively, during a reset operation as shown in Figure 6, in accordance with an embodiment. Figure 13A illustrates a word line reset voltage mirror VwR that rises to a maximum of about 123008.doc - 35 · 1356415 + 1/2 VRR during the duration of the portion of the illustrated operation (eg, ' +6 V). A bit line re-set voltage signal VBR having a start value of one -1/2 VRR for each reset voltage pulse is illustrated in Fig. 13B. The reset signal on the bit line has an amplitude that varies according to a substantially constant slope. In Figure 13B, this bit • the meta-reset voltage signal is increased from an initial value of approximately -1/2 VRR to an end value of approximately _(1/2 VRR + 2V). The amplitude amplitude of each negative bit line pulse is increased by about 2 V (e.g., up to -8 V) such that the reverse bias applied across the selected portion of the array is gradually increased. The amplitude of the VBR pulse is limited to the VBR bias level shown by the dashed line in Figure 13B by the output of one of the charge pump circuits as shown in Figure 丨〇B. The VBR bias level returns to its initial value between the application of the VBR pulses by controlling the counter 712 of Figure 14B. In the condition that one of the mothers and the first element of the body is aligned from the bit line to the word line as shown in FIG. 6 'the constant value of the word line reset voltage and the bit line reset voltage The increased negative voltage of the signal causes the reverse bias applied to each of the memory cells along the selected bit line and the selected word line to increase. A voltage signal is reset for the bit line, and a plurality of pulses are displayed that can be used to individually reset a smaller portion of the array. For example, a first reset voltage pulse can be applied to one of the bit lines in each of the plurality of selected blocks (sub-arrays) to each of the plurality of selected blocks. A second bit line applies a second pulse. Apply more 'reset pulses' to more bit lines until all the data provided by the user is encoded. This technique may require 16 to 64 or more reset voltage pulses in inverse proportion to the number of blocks used to store user data for one page. 123008.doc -36- 1356415 The starting and ending values for vBR can vary from implementation to implementation. In a specific embodiment, statistics or experiments are used to select the optimal start and end values for each pulse. For example, the initial value of the pulse can be selected to produce a reverse bias that is determined to be the minimum value that any cell would need before resetting from the lower resistance state to the higher resistance state. . The end value of each pulse can be selected to produce the maximum reverse bias typically required to reset any cells of the array. By gradually applying an increased reverse bias, resetting the memory unit at a lower reset reverse bias level can avoid damage to the increased reverse bias level "When a memory cell is re- When set to this higher resistance reset state, it will conduct less current and behave in a self-limiting manner. When it has been successfully reset, it shuts itself down or stops conduction to a sufficient extent. This self-limiting cutoff point will avoid damage under these reverse bias conditions. It should be noted that the amplitude of a reset pulse is gradually increased from a starting value to a larger terminating value to thereby increase the reverse bias for the selected memory cell without having a larger starting value with the application. The same electrical effect of the constant pulse. A pulse having a larger starting value may detract from the material forming the resistance changing element or cause a permanent deflection of one of the resistors. Accordingly, one embodiment of the disclosed technology utilizes a tilt reverse reset pulse to successfully and safely erase memory cells having different device characteristics. 12A &amp; i2B illustrate portions of a column control circuit and a row control circuit that can provide a re-sampling voltage 彳g number, respectively, in a particular embodiment. In FIG. 14A, a charge pump 7〇6 transmits a reverse-reset VwR bias level to the counter by including a-reverse source selection bus line 123008.doc -37· 1356415. A bus bar (e.g., bus bar 430 in Figures 9A through 12) is selected to the source and provided directly to the column decoder circuit (e.g., decoder 322 in Figure 4). The reference voltage generator 702 receives a supply voltage vcc and provides a reference voltage Vref to the electric pump controller 704. Using one of the outputs from the charge pump 7〇6, the controller can provide an initial vWR bias level of about i/2 vRR as needed. The row control circuit illustrated in Figure 12B utilizes a counter 712 and a digital to analog converter 714 to generate a bit line reset voltage VBR bias level having a negative ramp output (negative level and slope). Counter 712 receives a pulse start time and uses a clock signal to provide a pulse input to DAC 714 to produce an analog skew output. The DAC 714 receives the digital input and provides a voltage level to the charge pump controller. The charge pump 718 generates a negative bit line reset voltage VBR that is increased by a substantially constant and negative slope generated by the counter. The amplitude of the negative voltage Vbr bias level is increased in accordance with the defined slope to gradually increase the reverse bias applied across the memory array. Figures 15A and 15B illustrate a set of voltage signals instead of one of the reverse biases of Figure 6. A positive voltage pulse VWR is applied to the selected word line and increases in accordance with a positive slope. A negative bit line voltage pulse vBR is applied to the (equal) selected bit line. Each word line voltage pulse begins at a start value of about +5 V and increases by 2 V to about +7 Ve. The amplitude of the VwR pulse is limited by the rounded vWR bias level from the charge pump circuit and is Shown as the dashed line in Figure 15A, the combination of the word line and bit line reset pulses 123008.doc • 38 · 1356415 will provide an increased reverse bias across each selected memory cell. Additional bit line reset voltage pulses are described as available for setting or resetting additional bit line groups. As shown in Figures 9A through 9B, the pulses of Figures 11A through 11B can be used to generate a forward bias in some embodiments. In another embodiment, the pulses are not oblique. For example, a first voltage pulse having a negative polarity can be applied to a first array line and a second voltage pulse having a positive polarity can be applied to a first 'array line to generate a reverse bias. This configuration can also switch the resistance of the memory cells' but does not include the slope of one of the pulses or the offset produced by one of the applied biases. The embodiment of Figures 15A and 15B includes a retry technique for using a reset pulse level that is slightly higher by one of the VwR bias levels for a memory cell that is not reset when the initial voltage pulse is applied. . For example, the result of the resetting of a selected portion of the beta array can be applied after applying the last reset voltage pulses 8〇4 and 814. A verify operation can include reading back the resistance state of the memory cell and comparing it to a predefined level for the re-δ state. Any row or bit line that is not reset can be subjected to a higher level one retry pulse. The initial value of the word line voltage pulse 806 is increased to 7v and increased to a level of 9V. The value of any retry pulse can vary from embodiment to embodiment and can be selected based on statistical information and/or testing as previously described. The retry pulse is applied to each bit line of the array that has not passed the verification for a reset state in Figs. 15A and 15B. In other embodiments, a retry pulse (or more than 123008.doc - 39 - 1356415 pulses) may be applied after each of the initial reset voltage pulses is applied. If a cell or group of cells fails verification of the target resistance state after a retry pulse (or multiple retry pulses), it can be processed using error correction control techniques or redundant memory. Replace the unit. Figures 16A and 16B illustrate portions of a column and row control circuit that can be used to provide the pulses of Figures i3A and 13B in accordance with an embodiment. The selected word lines provide a positive reset signal having an amplitude that is increased in accordance with a positive slope in this embodiment. A counter 904 and a digital to analog converter 9〇6 are utilized when driving the charge pump controller 9〇8. Controller 9〇8 uses the analog output of DAC 906 and generates a positive tilt bias level via charge pump 91〇. The output of charge pump 910 is applied directly to the word line decoders and applied to the reverse source select bus line via a reverse source select bus pulse generation circuit. Figure 16B illustrates a portion of a row control circuit 210 for providing a negative Vbr bias level. A reference voltage generator 914 delivers the reference voltage Vref to the charge pump controller 916. The controller utilizes one of the outputs from the charge pump 918 to return the loop to maintain a stable value of the VBR bias for resetting the voltage signal for the bit line. The foregoing detailed description of the invention has been presented for purposes of illustration It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above principles. The specific embodiments are chosen to best explain the principles of the invention and its actual deer'''''''''' Various modifications. It is intended that the scope of the invention be defined by the scope of the appended claims. 123008.doc -40· 1356415 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates an exemplary non-volatile memory single 7G in accordance with one embodiment. Sexual Nonvolatile Tables 2A and 2B illustrate an example memory unit in accordance with an embodiment.

3A and 3B are individual perspective and cross-sectional views of a particular embodiment. Figure 4 is a block diagram of a non-volatile tenant according to a specific embodiment. FIG. 5 is a graph showing the resistance distribution of various states according to a specific embodiment. FIG. 6 is a diagram illustrating the basis of the specific reverse (four)-reverse bias reset operation. One of the bias conditions is one of the memory arrays that simplifies the circuit diagram. Figure 7 is a simplified circuit diagram of a memory array in accordance with a bias condition for a reverse bias adjustment operation in accordance with an embodiment.

A Non-Volatile Memory System Figure 8 is a flow diagram of one method for resetting a memory cell array in accordance with an embodiment incorporating an adjustment operation. 9A and 9B are circuit diagrams of a portion of a control circuit for providing a reverse bias reset condition of FIG. 6 in accordance with an embodiment. FIGS. 10A and 1B can be used to provide FIG. 6 in accordance with an embodiment. The reverse bias voltage resets the circuit diagram of a portion of the conditional control circuit. 11A and 11B are circuit diagrams of a portion of a control circuit for providing a reverse bias adjustment condition of FIG. 7 in accordance with an embodiment. Figure 12 is a circuit diagram of one portion of a row control circuit for providing a reverse bias voltage of 123008.doc • 41 - ^56415 of Figure 7 in accordance with an embodiment. 13A and 13B illustrate exemplary bit line and word line reset voltage signals for generating an increased reverse bias during a reset operation in accordance with an embodiment. 14A and 14B are circuit diagrams of portions of a control circuit that can be used to generate a ramp pulse reset voltage signal as shown in Figs. 11A and 11B. 15A and 15B illustrate other exemplary bit line and word line reset voltages used to generate an increased reverse bias during a reset operation in accordance with an embodiment. Figures 16A and 16B are circuit level diagrams of portions of a control circuit that can be used to generate the ramp reset pulse signals as shown in Figures 9A and 9B. [Main Element Symbol Description] 100 Memory Unit/Passive Storage Element 102 Guide Element 104 State Change Element 106 Anti-Fuse 110 First Conductor/First Metal Conductive Layer 112 Second Conductor/Second Metal Conductive Layer 120 Memory Unit 122 Heavily doped n-type region 124 essential region 126 heavily mixed Ρ-type region 128 anti-solvent filament 140 memory unit 123008.doc -42· 1356415 142 heavily doped n-type region 144 essential region 146 heavily doped ρ Type area 152 memory unit 162 first bit line set 164 word line 170 memory unit

174 bit line 176 word line 178 memory unit 180 bit line 182 memory unit 184 word line 186 memory unit 200 integrated circuit

202 memory array 206 row control circuit 210 input/output 208 column control circuit 220 output 210 row control circuit 212 row decoder 214 array terminal receiver or driver 216 block selection circuit 220 column control circuit 222 column decoder 123008. Doc -43 - 1356415 224 Array Terminal Driver 226 Block Selection Circuit 250 Line / State 252 Line / State 254 Line / State 256 Line / State 258 Line / Target Level 402 Upper PMOS Device 404 Upper PMOS Device 406 Lower NMOS Device 408 Lower NMOS device 412 upper PMOS device 414 upper PMOS device 416 NMOS device 418 NMOS device 422 column decoder 423 column decoder 430 bus 506 lower NMOS device 512 row decoder 513 unselected column decoder 702 reference voltage generator 704 charge help Pu controller 706 charge pump -44- 123008.doc 1356415 712 counter

714 Digital to Analog Converter / DAC 716 Charge Pump Control Circuit 718 Charge Pump 804 Reset Voltage Pulse 806 Word Line Voltage Pulse 814 Reset Voltage Pulse 904 Counter

906 Digital to Analog Converter / DAC 908 Charge Pump Controller 910 Charge Pump 914 Voltage Generator 916 Charge Pump Controller 918 Charge Pump

123008.doc -45 -

Claims (1)

1356415 Patent Application No. 096127570 Replacement of Chinese Patent Application (August 1st) X. Patent Application Range: 1. A method for operating non-volatile storage, which includes: (4) The annual order is revised by day Transmitting a first level of reverse bias to a plurality of non-volatile storage elements, switching the storage elements from a lower resistance state to a higher resistance state; and switching the storage elements to the The storage element applies a second level of reverse bias to reduce a resistance of a subset of the storage elements having a resistance that exceeds a target level corresponding to the higher resistance state. 2. The method of claim 1, wherein: the reverse bias of the first level is higher than the reverse bias of the second level. 3. The method of claim 2, wherein: the second level of reverse bias is about 60% of the level of the first level of reverse bias. 4) The method of claim 1, wherein: the knowing that the reverse bias of the first level comprises applying a &quot;&quot; positive voltage pulse to the first array line of the storage element The storage element passes through the second array line to apply a negative voltage pulse; and the reverse biasing of applying the second level includes applying a positive voltage pulse to the first array line and applying a fixed to the second array line Dust. 5. The method of claim 1, wherein each of the plurality of non-volatile storage elements includes a rate change material, and the reverse bias is applied to the plurality of levels to increase the number of the plurality of non-volatile storage elements. Store 123008-looo8i9.doc '=7 The resistivity of the memory component changes the resistivity of the material; X reverses the bias of the first 'level to reduce the access + for the storage component, and the side of m The resistivity changes the resistivity of the material. 6. The method of claim 5, wherein: the resistivity change material is polycrystalline. 7. The method of claim 5, wherein: the resistivity changes the material system - the metal oxide. 8. The method of claim 5, wherein: the plurality of non-volatile (four) rate-changing materials are electrically run, and the component includes the guiding: the guiding element, the resistivity changing material forming at least 70 of the portion. 9. The method of claim 5, wherein: each of the components of the resistance storage component comprises an anti-fuse coupled to the electrical lunch variant. The method of claim 1, wherein: the virtuosome memory array is a portion of the plurality of non-volatile storage elements. 11. The method of claim 10, wherein: the &quot;Hai array comprises a first plurality of arrays, a sum of which is perpendicular to the second plurality of arrays H of the first plurality of array lines and the first An individual line shared between a plurality of array lines and at least one of the second plurality of array lines of memory levels of the three-dimensional array. 12. The method of claim </ RTI> wherein: the lower resistance state corresponds to a set state 123008-1000819.doc • 2-state for the storage elements; and the higher resistance state is for the temple shaped bear. The method of claim 12, wherein: the method of claim 12, wherein: the lower resistance state is a state of the material element. : 15 such as: a number of non-volatile storage elements include more than two states. 5. The method of claim 13, wherein: the plurality of non-volatile storage elements are multi-state storage. 16. The method of claim 12, wherein: the plurality of non-volatile storage elements are formed into - The field can be programmed as part of one of the arrays of the brothers; the lower resistance state of the field is for one of the formatted states of the _T. 17. The method of claim 1, wherein: applying a reverse level of the second level, the bias voltage does not qualitatively change one of the plurality of storage elements having a resistance within the target level . A non-volatile memory system comprising: a plurality of non-volatile storage elements including a resistance change element. The non-volatile storage elements each comprise a diode; and a control circuit that communicates with the plurality of non-volatile storage elements, the control circuit by means of applying a -first level of the reverse (four) of the storage elements Resetting 123008-1000819.doc 1356415 from a lower resistance state to a higher resistance state, the control circuit applies a second to the storage elements after switching the storage elements A level of reverse bias is applied to reduce a resistance of a subset of the storage elements having a resistance that exceeds a target level corresponding to the higher resistance state. 19. The non-volatile memory system of claim 18 wherein: the first level of reverse bias is higher than the second level of reverse bias. 20. The non-volatile memory system of claim 19 wherein: the reverse bias of the first level of δκ is about 60% of the level of the reverse bias of the first level. 21. The non-volatile memory system of claim 18, wherein: the control circuit communicates with the storage element by applying a positive voltage pulse to a first array line in communication with the storage elements A second array line applies a negative voltage pulse to apply the reverse bias of the first level; and the control circuit applies the second level of reverse bias to apply a positive charge to the first array line A fixed bias is applied to the second array line by a pulse. 22. The non-volatile memory system of claim 18, wherein: each of the plurality of non-volatile storage elements comprises a resistivity change material; applying a reverse bias of the first level And increasing each of the storage elements for the plurality of storage elements - the resistivity changing material resistivity. applying the second level of reverse bias to reduce the each of the storage elements for the sub-port The resistivity changes the resistivity of one of the materials. 23. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> A non-volatile memory system of claim 22, wherein: the resistivity change material is polycrystalline germanium. 24. The non-volatile memory system of claim 22, wherein: the resistivity changing material is a metal oxide. 25. The non-volatile memory system of claim 22, wherein: each of the plurality of non-volatile library elements comprises a guiding element in series with the resistivity changing material, the resistivity changing material forming the At least a portion of the guiding element. 26. The non-volatile memory system of claim 22, wherein: each of the plurality of non-volatile storage elements comprises an anti-fuse in series with the resistivity change material. 27. The non-volatile memory system of claim 18, wherein the step comprises: - a three-dimensional single stone memory train comprising the plurality of non-volatile storage elements. 28. The non-volatile memory system of claim 27, further comprising a first plurality of array lines; and a second plurality of array lines qualitatively perpendicular to the first plurality of arrays, in fact column lines; a first plurality of array lines and the one comprising an individual shared between the second plurality of array lines of the three-dimensional array and the body level. 29. The non-volatile memory system of claim 18, wherein: The lower resistance state corresponds to the state for the storage elements; and 123008-1000819.doc -5 - 1356415 one of the components resets the higher resistance state corresponding to the stored state for the storage. 30. The non-volatile memory system of claim 29, wherein: the lower resistance state is for one of the storage elements of the sequel + 忑, etc. 3. The non-volatile memory system of claim 30 Wherein the plurality of non-volatile elements are rewritable storage elements. 32. The non-volatile memory system of claim 30 wherein: the plurality of non-volatile storage elements comprises more than two states. 33. The non-volatile memory system of claim 29, wherein: the L(tetra)Wei field can program a portion of one of the arrays of memory; the lower resistance state is for a formatted state of the storage elements. 34. The non-volatile memory system of claim 18, wherein: applying the second level of reverse bias does not substantially alter one of the plurality of storage elements having a resistance within the target level resistance. 35. The non-volatile memory system of clause 18, wherein: the control circuit comprises at least one of a column control circuit and a row control circuit. 123008-1000819.doc