1353519 、 » .» • 玖、發明說明： • 【發明所屬之技術領域】 • 本發明侧於-種·刚記憶體裝置及其存取方法，尤指__種具有 型快閃記憶體之NOR介面快閃記憶體裝置及其存取方法。 【先前技術】 快閃記憶體(Flash Memory)為一非揮發性(n〇n_v〇latile)之記憶體，在電 源關閉時仍可保存先前寫入的資料。與其他儲存媒體(如硬碟、軟碟或磁帶 鲁 等)比較’快閃記憶體有體積小、重量輕、防震動、存取時無機械動作延遲 與低耗電等特性。由於快閃記憶體的這些特性，因此近年來消費性電子產 品、嵌入式系統或可攜式電腦等資料儲存媒體皆大量採用。 快閃記憶體主要可分兩種：NOR型快閃記憶體與NAND型快閃記憶 體。NOR型快閃記憶體的優點為低電壓、存取快且穩定性高，因此已被大 $應用於可攜式電子裝置及電子通訊裝置，諸如個人電腦(Personal1353519, » .» • 玖, invention description: • [Technical field of invention] • The invention is a side-of-the-memory memory device and its access method, especially the NOR of a type of flash memory. Interface flash memory device and access method thereof. [Prior Art] Flash Memory is a non-volatile (n〇n_v〇latile) memory that retains previously written data when the power is turned off. Compared with other storage media (such as hard disk, floppy disk or tape tape), the flash memory has the characteristics of small size, light weight, anti-vibration, no mechanical action delay and low power consumption during access. Due to these characteristics of flash memory, in recent years, data storage media such as consumer electronic products, embedded systems or portable computers have been widely used. There are two main types of flash memory: NOR flash memory and NAND flash memory. NOR-type flash memory has the advantages of low voltage, fast access and high stability, so it has been used in portable electronic devices and electronic communication devices, such as personal computers (Personal).
Computer ’ PC)、行動電話、個人數位助理(pers〇nai Digitai Assistanee，PDA> • 以及轉頻器(Set-t〇PB〇X，STB)等。NAND型快閃記憶體是專門為資料儲存 用途而設計之快閃記憶體，通常應用於儲存並保存大量的資料的儲存媒 介’如可攜式記憶卡(SD Memory Card，Compact Flash Card，Memory Stick 等等）。 , NAND型快閃記憶體寫入速度雖然較NOR型快閃記憶體快速，但其不 支援本地執行代碼(XIP，eXecute In Place)功能。反觀N〇R型快閃記憶體由 於具有依照線性的記憶體位置區即能快速且隨機地讀取資料(Rand〇m Read) 5 1353519 • 的特性，故能支援本地執行代碼。因此’ NOR型快閃記憶體多用於儲存電 子裝置如：手機、攜帶型電腦等之主控制程式 '開機程式。而NA^D型快 閃記憶體由於具有快速抹除、寫入的特性’且單位容量成本遠較N〇R型快 閃記憶體為低，主要應用於單純、大量的資料儲存。然而，一般而言，對 ΝΑΝϋ型快閃記憶體之資料存取係以頁(Page)為單位，無法如NOR型快閃 5己憶體隨機地讀取資料(Rand〇m Reaci)，是以，讀取的速度遠較型為 慢，且其不支援本地執行代碼(χιρ)功能，如在前述電子產品中採用ΝΑΝ〇 φ 型快閃5己憶體儲存主控制程式、開機程式等，將會出現電子產品啟動速度 慢、較容易當機等嚴重的問題。 由於NAND型快閃記憶體的容量遠大於n〇r型快閃記憶體，現今業 界對快閃記憶體已發展出若干解決方案，嘗試使快閃記憶體裝置產品能兼 顧NAND型快閃記憶體高容量及N〇R縣閃記憶體高速讀取且可靠度高 的優點。 現今業界所提出之方案不外將SRAM加入快閃記憶體裝置内，利用 • SRAM高速，仿效中央處理器(cpu)内部設置快取(cache)的方式，提高快閃 記憶體裝置之讀取速度4者，或更進—步設計—嵌人式控躲體即時 監控NAND型快閃記憶體的讀寫區塊，當出現損壞區塊時，立即加以隱藏， 避免&式」存取到此損壞區域，而導致電子產品啟動速度慢當機等嚴 重的問題’而能避免NAND型快閃記憶體物理上的不可靠缺陷。 然而’此類解決方案於主機端仍然需要嵌入式控制軟體等及驅動程式的 支挺’其主機對_記聽裝置之存取指令械是以對NAND型快閃記憶 6 1353519 * · * • 體的模式進行資料的存取，而非以對NOR型快閃記憶體的模式依照線性的 — 記憶體位置區進行資料存取。且其雖利用SRAM作為快取而達到支援本地 執行代碼的功能’但亦僅能支援1KB長度的本地執行代碼，與N〇R型快 閃記憶體仍具有相當的差距。 除此之外，欲從一主機端連續發送複數個讀取命令以讀取快閃記憶體内 複數筆資料時，由於NAND快閃記憶體的特性，每—個讀取命令會從快閃 記體内的各個區塊(block)内找到所要讀取的資料，而後職到的資料傳輸回 φ 主機端，當資料傳輸完成後，快閃記憶體傳回一狀態訊息回主機端，接下 來下一讀取指令會繼續如上的流程直到所有讀取指令都完成其對應的程 序。在母-個讀取命令的讀取過程内，主機傳達讀取命令到快閃記憶體' 快閃s己憶體將所要讀取的資料自各個區塊中找出、以及從快閃記憶體傳狀 態訊息回主機端的準備時間總和約為將資料從快閃記憶體傳輸回主機端的 時間的三倍。雖然資料傳輸時間會隨著資料量的增加而增加，但是整個準 備時間總和並不會’料量的增加而增加^所以在短_岐續產生複數 •讀取指令時，等待資料傳輸的時間往往都被浪費掉。所以如能發展出-與 NOR型㈣記紐相#之關記鐘裝置及其倾存取方法，能快速且隨 機地存取貝料’兼具NAND型快閃記憶體以及NOR型快閃記憶體的優點， 使快閃記憶體裝置產品能滿足各式產品全方位需求。 【發明内容】 本㈣之主要目的在於提供―種㈣記憶猶置及赫衫法，提供 多管式(pipeHne)的資料存取方式，能快速地存取資料。 7 1353519 本發明之一實施例係提供一種快閃記憶體裝置，其包含一 nand型快 閃記憶體、一資料緩衝區、一指令緩衝區、一比較器以及一 NOR型快閃記 憶體介面。該NAND型快閃記憶體係用以儲存一資料。該資料緩衝區係用 來暫存該NAND型快閃記憶體所儲存之該資料。該指令緩衝區係用來暫存 複數個讀取指令，每一讀取指令包含一讀取資料位址。該比較器係用來比 較每一讀取指令之讀取資料位址與該資料緩衝區所暫存資料之位址，以產 生一比較資Λ。該NOR型快閃記憶體介面係用來依據該比較資訊決定自該 資料緩衝區讀取資料或是自該NAND型快閃記憶體讀取資料。 本發明之資料緩衝區所暫存之資料之位址係對應於儲存於該NAND快 閃記憶體之實體位址。 本發明之該指令緩衝區包含複數個指令緩衝區塊，每一指令緩衝區塊 係用來暫存該等讀取指令之_讀取指令。該指令缓衝區係__先進先出緩衝 區(First-in First-out buffer)。每一指令緩衝區塊包含一邏輯區塊位址欄位以 及哉別資料攔位’ 5亥邏輯區塊位址欄位係用來儲存每一讀取指令之讀取 Η料位址„亥識別資料緩衝欄位係用來儲存每一讀取指令所對應之比較資 訊0 本七明之a玄NORS快閃記憶體介面係以多管式响e㈣的方式依據該 才"、友衝所儲存之該啸資訊，自該資料緩衝區讀取資料或是自該 NANT□型快閃記憶體讀取資料。 本發明之另—實關储供—種(_記㈣裝置存取方法該快閃記 8 憶體装置包含—N細型‘_記憶體以及—資料緩衝區，該NAND型快閃 記憶體用嘯，，物職_錢N獅侧記憶體所 儲存之該資料，該方法包含下列步驟： 讀取資 將複數㈣取齡暫存於—齡緩_，每—讀取指令包含一 料位址； 比較每一讀取指令之讀取資制 只取貝枓位址與s玄貢料緩衝區所暫存資料之位 址’以產生一比較資訊；以及 依據該比較資訊決定自該資料緩衝_取資料或是自該N娜型快閃 記憶體讀取資料。 為讓本發明之上述和其他目的、特徵、和優職更賴紐，配合所 附圖式，作詳細說明如下： 【實施方式】 凊參考第1 ®，第1圖係本發明之快閃記憶體裝置1〇〇之功能方塊圖。 快閃記憶體裝置100包含-NAND型快閃記憶體1〇2以及一控制器， 控制器包含-邏輯區塊轉換單元202、一 N0R型快閃記憶體介面204、 NAND型快閃δ己憶體介面206、一資料緩衝區208、一指令緩衝區212 以及一比較器210。快閃記憶體裝置1〇〇透過N〇R型快閃記憶體介面2〇4 與一主機300通連，接收來自主機3〇〇之讀取指令。主機3〇〇可為桌上型 電月a、葦3己型電腦、工業電腦或可錄放DVD播放裝置等等。NAND快閃記 憶體102包含複數個區塊(bi〇ck) ’每一個區塊均由64個頁(page)所組成， 每一個頁為2K位元組(bytes)或是512位元(bits)大小。 1353519 NAND型快閃記憶體102可用以儲存程式媽(啟動碼，b_〇de)或者單 純的資料。NAND型快閃記憶體介面2〇6搞接於NAND型快閃記憶體· 資料緩衝區208耦接於 用以存取NAND型快閃記憶體102所儲存之資料 nor型快閃記憶體介面204與NAND型快閃記憶體介面2〇6之間用以暫 存NAND型快閃記憶體介面施所存取之資料。邏輯區塊轉換單元施用Computer 'PC', mobile phone, personal digital assistant (pers〇nai Digitai Assistanee, PDA> • and transponder (Set-t〇PB〇X, STB), etc. NAND flash memory is designed for data storage purposes. Designed flash memory, usually used to store and store a large amount of data storage media such as portable memory card (SD Memory Card, Compact Flash Card, Memory Stick, etc.), NAND flash memory write Although the input speed is faster than the NOR flash memory, it does not support the local execution code (XIP, eXecute In Place) function. In contrast, the N〇R type flash memory can be quickly and quickly due to the linear memory location area. Randomly read the data (Rand〇m Read) 5 1353519 • Features, so it can support local execution code. Therefore, 'NOR type flash memory is used to store electronic devices such as mobile phones, portable computers and other main control programs' The booting program, while the NA^D flash memory has the characteristics of fast erasing and writing, and the unit capacity cost is much lower than that of the N〇R type flash memory, mainly used for simple and large amounts of data. However, in general, the data access to the 快-type flash memory is in units of pages, and it is not possible to read data randomly (Rand〇m Reaci) as in the NOR type flash memory. Therefore, the reading speed is much slower than the type, and it does not support the local execution code (χιρ) function. For example, in the aforementioned electronic products, the ΝΑΝ〇φ type flash memory 5 memory is used to store the main control program, the boot program, and the like. There will be serious problems such as slow start-up of electronic products and easier crashing. Since the capacity of NAND-type flash memory is much larger than that of n〇r-type flash memory, some flash memory has been developed in the industry today. Solution, try to make the flash memory device products have the advantages of high-capacity NAND flash memory and high-speed reading of N〇R county flash memory with high reliability. Now the solution proposed by the industry is to add SRAM. In the flash memory device, using SRAM high speed, emulating the internal CPU (cpu) to set the cache to improve the read speed of the flash memory device, or more advanced design - embedded Instant control of human control The NAND-type flash memory read/write block is hidden immediately when a damaged block occurs, avoiding & access to the damaged area, resulting in serious problems such as slow start-up of electronic products. It can avoid the physical unreliability of NAND flash memory. However, 'this kind of solution still needs embedded control software and driver support on the host side.' The data is accessed in the mode of the NAND type flash memory 6 1353519 * · * • instead of the data in the linear - memory location area in the mode of the NOR type flash memory. Moreover, although SRAM is used as a cache to support local execution of code, it can only support 1KB of local execution code, and there is still a considerable gap with N〇R type flash memory. In addition, when a plurality of read commands are continuously sent from a host to read multiple data in the flash memory, each read command will be flashed from the flash memory due to the characteristics of the NAND flash memory. The data to be read is found in each block in the block, and the data from the post-office is transmitted back to the φ host. When the data transfer is completed, the flash memory returns a status message back to the host, and then next. The read instruction will continue as above until all read instructions complete their corresponding program. During the reading of the parent-read command, the host communicates the read command to the flash memory' flash memory. The data to be read is found in each block and from the flash memory. The sum of the preparation time for transmitting the status message back to the host is about three times the time for transferring the data from the flash memory back to the host. Although the data transmission time will increase with the increase of the amount of data, the total preparation time will not increase with the increase of the amount of material. Therefore, in the short _ continuation of the generation of multiple reading commands, the time for waiting for data transmission is often Both are wasted. Therefore, if it can be developed - with the NOR type (four) remember the clock device and its dumping method, can quickly and randomly access the shell material 'both NAND flash memory and NOR flash memory The advantages of the body enable the flash memory device products to meet the full range of needs of various products. SUMMARY OF THE INVENTION The main purpose of this (4) is to provide a kind of (four) memory and hologram method, and provide a multi-pipe (pipeHne) data access method, which can quickly access data. 7 1353519 An embodiment of the present invention provides a flash memory device including a nand type flash memory, a data buffer, an instruction buffer, a comparator, and a NOR type flash memory interface. The NAND type flash memory system is used to store a data. The data buffer is used to temporarily store the data stored in the NAND flash memory. The instruction buffer is used to temporarily store a plurality of read instructions, each of which includes a read data address. The comparator is used to compare the read data address of each read command with the address of the data temporarily stored in the data buffer to generate a comparison. The NOR flash memory interface is configured to read data from the data buffer or read data from the NAND flash memory based on the comparison information. The address of the data temporarily stored in the data buffer of the present invention corresponds to the physical address stored in the NAND flash memory. The instruction buffer of the present invention includes a plurality of instruction buffer blocks, each instruction buffer block being used to temporarily store the read instruction of the read instructions. The instruction buffer is __First-in First-out buffer. Each instruction buffer block contains a logical block address field and a screening data block. The 5H logical block address field is used to store the read data address of each read command. The data buffer field is used to store the comparison information corresponding to each read command. The seven-nano NORS flash memory interface is based on the multi-tube type e (four) according to the method. The whistle information, reading data from the data buffer or reading data from the NANT□ type flash memory. The other embodiment of the present invention - the actual storage and storage - (_ note (four) device access method the flash flash 8 The memory device includes -N fine type '_memory and - data buffer, the NAND type flash memory uses the data stored by the _ _ _ money N lion side memory, the method comprises the following steps: The capital will be stored in the plural (4) age-old in the age-slow _, each-reading command contains a material address; the reading resource of each reading instruction is only taken from the shellfish address and the s-weight buffer The address of the temporary data is 'to generate a comparison information; and based on the comparison information The data buffer _ takes data or reads data from the N-type flash memory. In order to make the above and other objects, features, and superior functions of the present invention more closely related to the drawings, the following is described in detail. [Embodiment] Referring to FIG. 1 and FIG. 1 is a functional block diagram of a flash memory device of the present invention. The flash memory device 100 includes a -NAND type flash memory 1〇2 and a The controller includes a logic block conversion unit 202, an N0R type flash memory interface 204, a NAND type flash δ memory interface 206, a data buffer 208, an instruction buffer 212, and a comparator. 210. The flash memory device is connected to a host 300 through the N〇R type flash memory interface 2〇4, and receives a read command from the host 3. The host 3〇〇 can be a desktop type A monthly computer, an industrial computer or a recordable DVD playback device, etc. The NAND flash memory 102 includes a plurality of blocks (bi〇ck) 'Each block has 64 pages. Composition, each page is 2K bytes or 512 bits. 1353519 NAND The flash memory 102 can be used to store a program mother (boot code, b_〇de) or simple data. The NAND type flash memory interface 2〇6 is connected to the NAND type flash memory. The data buffer 208 is coupled. The NAND type flash memory interface is temporarily stored between the nor type flash memory interface 204 and the NAND type flash memory interface 2〇6 for accessing the data stored in the NAND flash memory 102. Access data. Logical block conversion unit application
來管理快p松M1G2内之倾記縣齡址(Physieal Bbek祕_他) 對應於NOR型快閃記憶體介面2〇4存取資料所對應之邏輯區塊位址 (Logic㈣ock施職’ LBA)關係。也就是說，透過舰型快閃記憶體介 面施以及邏無塊轉換單㈣，域可靖峨憶物模擬為 如硬碟機-般的區塊裝置，因此主機就可使用—般的檔案系統，如 4寫請求來存取 FAT32或EXT3等等，發出以區段(sect〇r)作為單位的 NAMD型快閃記憶體102的資料。 請一併參Μ丨_及第2圖’第2 _本個之,_記憶體裝置存 ® 取方法流程圖。其方法有下列步驟： 步驟210 :接收複數個讀取指令。 步驟犯：將魏個tlW旨令暫存於—齡_區，每1取指令包人 一讀取資料位址。 7I3 緩衝區所暫存資 步驟2M:比較每—讀取指令之讀取簡位址與該資料 料之位址，若是，執行步驟216，若否，執行步驟218。 步驟216:自該資料緩衝區讀取資料。 步驟218:自該NAND型快閃記憶體讀取資料。 當主機300發出複數個讀取指令以讀取NAND型快閃記憶體1〇2内的 資料時，指令緩衝區212會暫存自主機300所發送之讀取指令。請注意， 指令緩衝區212包含複數個指令缓衝區塊220’每一指令緩衝區塊22〇包含 一邏輯區塊位址櫊位222以及一識別資料欄位221，邏輯區塊位址攔位222 係用來儲存每一讀取指令之讀取資料的邏輯區塊位址(LBA)。如果主機3〇〇 連續發出3個讀取指令，其中第一讀取指令請求讀取邏輯區塊位址LBA_1 的資料、第二讀取指令請求讀取邏輯區塊位址LBA_2的資料、第三讀取指 令請求讀取邏輯區塊位址LBA—3的資料。NOR型快閃記憶體介面204會根 據邏輯位址轉換單元202判斷邏輯區塊位址LBA_1對應至NANB型快閃記 憶體102内區塊1頁16(B1，P16)所儲存的資料、邏輯區塊位址LBA_2對應 至NAND型快閃記憶體1〇2區塊1頁30(B1，P30)的資料、以及邏輯區塊位 址LBA—3對應至NAND型快閃記憶體102區塊2頁10(B2，P10)所儲存的資 料。而指令緩衝區212的指令緩衝區塊2201的邏輯區塊位址欄位222則會 暫存邏輯區塊位址LBA_1、指令缓衝區塊22〇2的邏輯區塊位址攔位222則 會暫存邏輯區塊位址LBA_2以及指令緩衝區塊2203的邏輯區塊位址欄位 222則會暫存邏輯區塊位址LBA_3。 如果主機300之前曾請求讀取邏輯區塊位址LBA_2的資料，則NOR 型快閃記憶體介面204會控制資料緩衝區208暫存區塊1頁30(B1，P30)的資 料。接下來，比較器210會比較每一讀取指令之讀取資料位址與該資料緩 1353519 衝區所暫存資料之位址，也就是說’比較器210會比較第一讀取命令的讀 取資料位址LBAJ是否與資料緩衝區208所暫存資料之位址LBA_2相同。 一但發現兩者位址不相符，則比較器210將指令緩衝區塊2201的識別資料 欄位221之值改為〇(亦即比較資訊）。接下來NOR型快閃記憶體介面204 會依據比較資訊的内容，透過NAND型快閃記憶體介面206從NAND型快 閃記憶體102讀取區塊1頁16(B1，P16)所儲存的資料。在讀取naND型快 閃記憶體102之區塊1頁16(B1，P16)的資料的期間，比較器21〇會同時繼續 • 判斷出第二讀取命令的讀取資料位址LBA_2與資料緩衝區208所暫存資料 之位址LBAJ2相同，所以比較器210將指令緩衝區塊2202的識別資料欄 位221之值改為1(亦即比較資訊）。所以型快閃記憶體介面2〇4會依 據比較資訊的内容，直接從資料緩衝區208讀取資料，如此一來可縮短透 過NAND型快閃記憶體介面206從NAND独閃記麵1〇2讀取區塊i 頁30(B1，P30)的時間。在自資料緩衝區2〇8讀取資料期間，比較器2ι〇會同 時繼續判斷出第三讀取命令的讀取資料位址LBA—3是否與資料緩衝區观 • 所暫存資料之位址服-2相同，並持續上述之步驟直到指令緩衝器區212 内的指令㈣處理完畢。也就是說，指令緩倾212係—先進先出緩衝區 (First-in細刪buffo) ’並透過μ式指令的存取處理方式來處理複數個 讀取指令，故能大幅提昇刪_型快閃記憶體介面2〇4的存取效能。 相較於先前技術，本發明能以職型快閃記憶體介面快速且隨機地對 Ν厕型快閃繼存取射[除此之外，本發侧—齡緩衝區來儲 存複數個讀取指令，並以多管式的處理方式判斷讀取指令的讀取資料位址 12 1353519 . » - 是否與資料緩衝區所暫存資料之位址相符，若相符，則直接從資料緩衝區 讀取所要的資料。如此一來，本發明可大幅縮短以nor型快閃記情體介面 • 讀取NAND型快閃記憶體資料的處理時間。 雖然本發明以已一較佳實施例揭露如上，然其並非用以限定本發明。 本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍 内，當可作各種之變更和潤飾。因此，本發明之保護範圍當視後附之申請 專利範圍所界定者為準。 【圖式簡單說明】 第1圖係本發明之快閃記憶體裝置之功能方塊圖。 第2圖係依據本發明之N0R介面快閃記憶體裝置之存取方法的流程 圖。 【主要元件符號說明】 100 快閃記憶體裝置 102 NAND型快閃記憶體 200 控制器 202 邏輯位址轉換單元 204 nor型快閃記憶體介面 206 NANDfl，_記憶體介面 208 資料緩衝區 210 比較器 212 指令緩衝區 220 指令緩衝區塊 2201-220N指令緩衝區塊 221 識別資料攔乜 222 邏輯區塊位址攔位 300 主機 13To manage the puncture county address (Physieal Bbek secret _ he) in the fast Psong M1G2 corresponds to the logical block address corresponding to the NOR flash memory interface 2 〇 4 access data (Logic (4) ock job 'LBA) relationship. That is to say, through the ship-type flash memory interface and the logic-free block conversion (4), the domain can be simulated as a hard disk-like block device, so the host can use the general file system. For example, a 4 write request to access FAT32 or EXT3 or the like, and a data of the NAMD type flash memory 102 in units of segments (sect〇r) is issued. Please refer to the _ and the second picture '2nd _ this one, _ memory device storage ® take method flow chart. The method has the following steps: Step 210: Receive a plurality of read instructions. Step-by-step: The Wei tlW decree is temporarily stored in the age-of-age zone, and each commander takes a reading of the data address. Step 7M: Compare the read address of each read command with the address of the data, and if yes, go to step 216. If no, go to step 218. Step 216: Read data from the data buffer. Step 218: Read data from the NAND type flash memory. When the host 300 issues a plurality of read commands to read the data in the NAND flash memory 1〇2, the instruction buffer 212 temporarily stores the read command sent from the host 300. Please note that the instruction buffer 212 includes a plurality of instruction buffer blocks 220'. Each instruction buffer block 22 includes a logical block address field 222 and an identification data field 221, and a logical block address block. 222 is a logical block address (LBA) used to store the read data of each read instruction. If the host 3 〇〇 continuously issues 3 read commands, the first read command requests to read the data of the logical block address LBA_1, the second read command requests to read the data of the logical block address LBA_2, and the third The read instruction requests to read the data of the logical block address LBA-3. The NOR type flash memory interface 204 determines, according to the logical address conversion unit 202, that the logical block address LBA_1 corresponds to the data and logical area stored in the first block 16 (B1, P16) of the NANB type flash memory 102. The block address LBA_2 corresponds to the data of the NAND type flash memory block 1 〇 2 block 1 page 30 (B1, P30), and the logical block address LBA-3 corresponds to the NAND type flash memory block 102 block 2 page 10 (B2, P10) stored data. The logical block address field 222 of the instruction buffer block 2201 of the instruction buffer 212 temporarily stores the logical block address LBA_1 and the logical block address block 222 of the instruction buffer block 22〇2. The temporary logical block address LBA_2 and the logical block address field 222 of the instruction buffer block 2203 are temporarily stored in the logical block address LBA_3. If the host 300 has previously requested to read the data of the logical block address LBA_2, the NOR type flash memory interface 204 controls the data buffer 208 temporary storage block 1 page 30 (B1, P30). Next, the comparator 210 compares the read data address of each read command with the address of the data stored in the data buffer 1353519, that is, the comparator 210 compares the read of the first read command. Whether the data address LBAJ is the same as the address LBA_2 of the data temporarily stored in the data buffer 208. Once the address is found to be inconsistent, the comparator 210 changes the value of the identification field 221 of the instruction buffer block 2201 to 〇 (i.e., comparison information). Next, the NOR type flash memory interface 204 reads the data stored in the block 1 page 16 (B1, P16) from the NAND type flash memory 102 through the NAND type flash memory interface 206 according to the content of the comparison information. . During the reading of the data of the block 1 page 16 (B1, P16) of the naND type flash memory 102, the comparator 21〇 continues at the same time. • The read data address LBA_2 and the data of the second read command are judged. The address LBAJ2 of the temporary storage data of the buffer 208 is the same, so the comparator 210 changes the value of the identification data field 221 of the instruction buffer block 2202 to 1 (that is, comparison information). Therefore, the type flash memory interface 2〇4 will directly read data from the data buffer 208 according to the content of the comparison information, so that the NAND flash memory interface 206 can be shortened from the NAND flash memory surface 1〇2 through the NAND type flash memory interface 206. Take the time of block i page 30 (B1, P30). During the reading of data from the data buffer 2〇8, the comparator 2ι〇 will continue to determine whether the read data address LBA-3 of the third read command and the data buffer view • the address of the temporarily stored data The service-2 is the same and continues the above steps until the instruction (4) in the instruction buffer area 212 is processed. That is to say, the instruction slow-down 212-first-in-first-out buffer (First-in fine-deleted buffo)' and handles a plurality of read instructions through the access processing method of the μ-type instruction, so that the deletion can be greatly improved. The access performance of the flash memory interface 2〇4. Compared with the prior art, the present invention can quickly and randomly access the squat-type flash relay access by the job-type flash memory interface [other than this, the hair-side buffer to store multiple readings. Command, and multi-tube processing to determine the read data address of the read command 12 1353519. » - Whether it matches the address of the data buffer temporarily stored, if it matches, read directly from the data buffer The required information. In this way, the present invention can greatly shorten the processing time of reading the NAND type flash memory data with the nor type flash memory interface. Although the invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention. Various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a functional block diagram of a flash memory device of the present invention. Fig. 2 is a flow chart showing an access method of the NOR interface flash memory device according to the present invention. [Main component symbol description] 100 flash memory device 102 NAND type flash memory 200 controller 202 logical address conversion unit 204 nor type flash memory interface 206 NANDfl, _ memory interface 208 data buffer 210 comparator 212 Instruction Buffer 220 Instruction Buffer Block 2201-220N Instruction Buffer Block 221 Identification Data Block 222 Logical Block Address Block 300 Host 13