1333676 • 九、發明說明： • 【發明所屬之技術領域】 本發明係有關於一種利用複合硬遮罩層之製作金氧半 ' 導體電晶體（metal-oxide semiconductor，MOS transistor)之 - 方法’尤指一種利用選擇性蠢晶（selective epitaxial growth，以下簡稱為SEG)成長製作之MOS電晶體的方法。 _ 【先前技術】 選擇性磊晶成長（SEG)技術主要是於一單晶基板表面 形成一晶格排列與基板相同之磊晶層，其應用於許多半導 體元件的製作中，例如具有增高式源極/汲極(raised source/drain)之電晶體具有良好短通道特性與低寄生電阻 的優點，同時藉由增高之磊晶層之存在，可避免形成金屬 矽化物時過度消耗矽基底導致漏電流之困擾；而嵌入式源 極/沒極(recessed source/drain)則具有可改善沒極引發能帶 •降低效應（drain induced barrier lowering，DIBL)與擊穿 (punchthrough)效應、降低截止態漏電流、以及減少功率消 耗之優點。 一般而言，SEG技術係先利用一表面清洗製程完全地 清除基板表面的原生氧化物（native oxide)或其它不純物 (impurity)後，於基板表面沉積一蠢晶層，並使蟲晶層沿著 基板表面之晶格結構向上生長。請參閱第1圖至第4圖， 1333676 第1圖至第4圖係為一習知利用SEG技術製作應變矽m〇S 電晶體之方法之示意圖。如第1圖所示，首先提供一基底 100，如一矽基底，基底100上已形成有複數個淺溝隔離 (shallow trench isolation，STI) 102，並於基底上依序形成 一介電層112、一多晶石夕層114、與一包含有氮化石夕或氧化 石夕之硬遮罩層，其中硬遮罩層係藉由一微影製程圖案化， 而所得之圖案化硬遮罩層120係用以定義一閘極之位置及 線寬。 請參閱第2圖。接下來進行一蝕刻製程，移除部分多 晶矽層114與介電層112，以形成一閘極110。隨後進行一 離子佈植製程，以於閘極110兩側之基底100中分別形成 輪摻雜沒極(lightly doped drains ’ LDD) 116 ’ 並於閘極 11 〇 之側壁形成一側壁子118。接下來請參閱第3圖與第4圖。 隨後利用圖案化硬遮罩層120與側壁子118作為一蝕刻遮 罩’於閘極110兩側之基底100内分別蝕刻一凹槽130。 如第4圖所示，凹槽13〇内之基底100表面係於後續seG 製程時生成一磊晶層132。另外，在蝕刻凹槽130之前或 SEG製程形成磊晶層132之後，係可進行一離子佈植製 程’以形成一嵌入式源極/没極。 值得注意的是，在形成閘極110後，及進行形成嵌入 式源極/汲極之SEG製程前，基底100尚會經過多次蝕刻與 7 1333676 清洗步驟，例如多晶石夕層114 #刻後清洗、輕摻雜没極116 離子佈植後之清洗、側壁子118之触刻與钱刻後清洗、凹 槽130蝕刻及蝕刻後清洗、以及SEG製程前之清洗，上述 蝕刻及清洗製程在在耗損原本覆蓋於多晶矽層114上之硬 遮罩層120。因此在進行SEG製程前，被耗損的圖案化硬 遮罩層120致使其下方之多晶矽層114暴露出來，此種耗 損之發生尤以圖案化硬遮罩層120之邊緣居多。而在進行 後續SEG製程時，該等暴露出之多晶矽層114邊角（corner) 會形成不應出現的蟲晶層。該等蟲晶層的形成可能造成推 雜於多晶矽層114内之離子擴散至該等磊晶層内，因而降 低閘極110之活化程度（activation)或增加閘極110之反轉 (inversion)，影響元件表現。該等磊晶層132甚至可能在後 續製程中造成閘極110與源極/汲極間之短路，造成良率的 下降。 • 此外，由於氮化矽構成之硬遮罩層120不易移除，因 此亦常於後續移除硬遮罩層120之移除步驟中，例如移除 硬遮罩層120以於多晶矽層114表面形成一金屬矽化物， 會影響閘極110之表面輪廓，甚至於移除步驟中將側壁子 118 —同移除，而對閘極110之側壁或對多晶矽層114底部 之介電層112造成傷害。 因此，如何提供一可有效抵抗蝕刻與清洗步驟所造成 1333676 之耗損，亦可於移除時不致對其他元件造成損害之硬遮罩 層，實為半導體技術領域中一重要課題。 【發明内容】 因此，本發明於此提供一種利用複合硬遮罩之製作 MOS電晶體之方法，以改善習知技術中硬遮罩層因消耗而 損及其他元件，以及移除硬遮罩層時損害其他元件之缺失。 根據本發明之申請專利範圍，係提供一種利用複合硬 遮罩層之金氧半導體電晶體之製作方法。該方法包含有提 供一表面包含有一介電層與一多晶石夕層之基底，隨後形成 至少一複合硬遮罩於該多晶矽層上，該複合硬遮罩包含有 一中間硬遮罩與一覆蓋該中間硬遮罩側壁之側壁硬遮罩。 接下來進行一第一蝕刻製程，利用該複合硬遮罩為蝕刻遮 罩蝕刻該多晶矽層與該介電層，以形成一閘極結構；進行 一第二蝕刻製程，以於該閘極結構兩側之基底中分別形成 一凹槽（recesses)。之後進行一選擇性遙晶成長（SEG)製程， 以於該等凹槽内分別形成一磊晶層。 根據本發明之申請專利範圍，係提供一種具有複合硬 遮罩層之金氧半導體電晶體製作方法。該方法包含有提供 一表面包含有一介電層與一多晶石夕層之基底，依序形成一 第一硬遮罩層與一第二硬遮罩層於該膜層上，並進行一微 1333676 影暨蝕刻製程，以移除部分該第一硬遮罩層與部分該第二 硬遮罩層而形成至少一中間硬遮罩。接下來形成一覆蓋該 多晶矽層與該中間硬遮罩之第三硬遮罩層，並進行一回蝕 刻製程，以移除部分該第三硬遮罩層而形成至少一側壁硬 遮罩，且該側壁硬遮罩係覆蓋該中間硬遮罩之側壁以構成 一複合硬遮罩。進行一第一蝕刻製程，利用該複合硬遮罩 為蝕刻遮罩蝕刻該多晶矽層與該介電層以形成一閘極結 構；與進行一第二蝕刻製程，以於該閘極結構兩側之基底 中分別形成一凹槽。之後進行一 SEG製程，以於該等凹槽 内分別形成一蠢晶層。 根據本發明之申請專利範圍，更提供一種用以製作 MOS電晶體之複合硬遮罩，包含有一中間硬遮罩（middle hard mask)以及一側壁硬遮罩（spacer hard mask)，且該側壁 硬遮罩係設置於該中間硬遮罩層之側壁。 根據本發明之申請專利範圍，更提供一種MOS電晶 體，包含有一設置於一基底上之閘極結構、一複合硬遮罩 層，設置於該閘極結構上，該複合硬遮罩層係包含有一中 間硬遮罩以及一側壁硬遮罩設置於該中間硬遮罩之側壁。 該MOS電晶體尚包含有一對分別設置於該閘極結構兩側 之該基底内之輕摻雜汲極；以及一對分別設置於該閘極結 構兩側之該基底内，用以作為該MOS電晶體之一源極/汲 1333676 • 極之蠢晶層。 本發明所提供之利用複合硬遮罩之製作 MOS電晶體 之方法’係利用該複合硬遮罩之侧壁硬遮罩有效抵抗㈣ 與清洗步驟所造成之耗損，有效保護其遮蔽之元件；同時 作為主體之該中間硬遮罩係可於移除時不至造成其他元件 之損傷，而可提升良率。 • 【實施方式】 请參閱第5圖至第η圖’第5圖至第u圖係為本發 明所提供之複合硬遮罩層之製作方法之第一較佳實施例。 如第5圖所示’首先提供一基底2〇〇，如一矽基底，基底 200上已形成有複數個淺溝隔離（shau〇w trench isolation， STI) 202。隨後於基底200上依序形成一介電層212、一多 晶矽層214、與一第一硬遮罩層22〇。第一硬遮罩層22〇係 • 包含有包含有氧化矽(SiO)、氮化矽(SiN)、氮氧化矽 (SiON)、氮碳化石夕（SiCN)、碳化石夕（SiC)、含氧碳化石夕 (SiOC)、多矽氮化矽（Silicon-rich-nitride，SRN)、高溫氧化 石夕（high temperature oxide，HT0)、抗反射底層、或二（特 丁基氨基）石夕烧(3丨8(^1'1:-1)以丫1311^11〇)8如1^，6丁6入8)。於第 一硬遮罩層220上形成一光阻層222，並藉由一微影製程 圖案化光阻層222。 11 1333676 請參閱第6圖。接下來進行一蝕刻製程，利用圖案化 之光阻層222為遮罩移除部分第一硬遮罩層220，以形成 一中間硬遮罩224。 請參閱第7圖。隨後，於多晶矽層214與中間硬遮罩 224上形成一第二硬遮罩層230。第二硬遮罩層230係包含 有氮化矽、氮氧化矽、氮碳化矽、碳化矽、含氧碳化矽、 或多矽氮化矽（SRN)。而第二硬遮罩層230與第一硬遮罩層 220係具有不同之蝕刻選擇比。 請參閱第8圖。接下來，進行一回钱刻（etching back) 製程移除部分第二硬遮罩層230，以於中間硬遮罩224之 側壁形成一側壁硬遮罩234。而中間硬遮罩224與側壁硬 遮罩234係構成一複合硬遮罩240。如前所述，中間硬遮 罩224與側壁硬遮罩234係具有不同之蝕刻選擇比。且如 第8圖所示，中間硬遮罩224具有之一寬度X與側壁硬遮 罩234具有之一款度Y之比值約為1:10。此外，側壁硬遮 罩層234之寬度係不大於10奈米（nanometer)。 本第一較佳實施例所提供之複合硬遮罩240係用以於 一 SEG製程中定義一閘極結構210之位置。請參閱第9圖， 接下來係進行一第一蝕刻製程，經由複合硬遮罩240向下 蝕刻膜層214與介電層212，形成一閘極結構210。由於複 12 1333676 合硬遮罩240係用以定義閘極結構21 〇之位置及線寬，因 此在進行圖案化第一光阻層222之微影製程後，係可再進 行一修整（trimming)步驟，用以修整該圖案化之第一光阻層 222;或者在形成中間硬遮罩224之蝕刻製程後，再進行一 修整步驟，用以修整中間硬遮罩224。簡單地說，藉由修 整步驟’本第一較佳實施例係可調整中間硬遮罩224之寬 度，並輔以側壁硬遮罩234之寬度以定義閘極結構21〇之 線寬。 請參閱第10圖，隨後進行一離子佈植製程，以於閘極 結構210兩側之基底200中分別形成一輕捧雜沒極(lightly doped drains，LDD) 216，並於閘極結構210之側壁形成一 側壁子218。側壁子218與複合硬遮罩240係於一第二蝕 刻製程中作為蝕刻遮罩，以於閘極結構21〇兩側之基底2〇〇 内分別形成一凹槽250。 請參閱第11圖。凹槽250内之基底200表面係於SEG 製矛壬時生成一絲日日層252 ,以作為一嵌入式源極/沒極。當 然，在蝕刻凹槽250之前或SEG製程形成磊晶層之後，係 可進行一離子佈植製程，以形成一前述之嵌入式源極/汲 極。若MOS電晶體係一 PM〇s電晶體，則嵌入式源極/汲 極係包含有鍺化矽（SiGe)等；若M〇s電晶體係—NM〇s電 晶體，則嵌入式源極/汲極係包含有碳化矽（Sic)等。此外， 13 1333676 • 本第一較佳實施例所提供之方法係不限定於製作前述之嵌 ·· 入式源極/汲極，其亦可用於製作增高式（raised)源極/汲極 或平面式（planer)源極/汲極。 由於在進行形成嵌入式源極/汲極之SEG製程前’基底 200尚會經過多次蝕刻與清洗步驟，例如多晶矽層214蝕 刻後清洗、輕摻雜汲極216離子佈植後之清洗、側壁子218 之蝕刻與蝕刻後清洗、凹槽25〇蝕刻及蝕刻後清洗、以及 籲 SEG製程刖之清洗，上述钱刻及清洗製程接會耗損複合硬 遮罩240。然而由於複合硬遮罩240之側壁硬遮罩234之 蝕刻選擇比不同於中間硬遮罩224之蝕刻比，或者說，側 壁硬遮罩234之蝕刻率遠低於中間硬遮罩224之蝕刻率， 因此上述之蝕刻及清洗製程對於複合硬遮罩24〇邊緣之耗 損將會大幅降低，使得複合硬遮罩24〇所覆蔽之閘極結構 210不至於在上述蝕刻及清洗製程後暴露出來，也因此閘 • 極結構210邊角於SEG製程時形成不致出現磊晶層，降低 閘極結構210之活化程度或增加閘極結構21〇之反轉，影 響閘極表現。 另外’由於複合硬遮罩240之主體仍為中間硬遮罩 224,在後續去除複合硬遮罩234之步驟，較不易損及其他 元件，例如影響閘極210之表面輪廓，甚至於移除步驟中 " 將側壁子218 —同移除。 1333676 請參閱第12圖至第16圖，第12圖至第16圖係為本 發明所提供之複合硬遮罩層之製作方法之第二較佳實施 例。如第12圖所示，首先提供一基底300，如一矽基底， 基底300上已形成有複數個淺溝隔離（STI) 302。隨後於基 底300上依序形成一介電層312、—多晶石夕層 硬遮罩層32G與1二硬遮罩層322。第-硬遮罩層32〇 係包含有包含錢切(⑽）、氮切(SiN)、氮氧化石夕 (Sl〇N)、氮碳切(SiCN)、碳化邦⑹、含氧碳化石夕 (s1〇C)、多錢切（SRN)、高溫氧切_)、抗反射底 層、或-（特丁基氨基）石夕燒(BTBAS)。而第二硬遮罩層 322則包含有氧化發、氮切、氮氧切、氮碳切、^ ㈣、含氧碳切、多魏切(SRN)、高溫氧切(Ητ〇)、 抗反射底I (特丁基氨基）梦烷（BTBAS)等材料。 而第一硬遮罩層3^n命够_ 20與第二硬遮罩層322係具有不同之蝕 刻比。 ::閱第13圖與第14圖。進行一微影暨蝕刻製程， •r先形成-光阻層324於第二硬遮 影製程圖案化光阻岸324, ^ 微 ” a 324並利用圖案化之光阻層324進 行一#刻I程移除部分第一 弟硬遮罩層320與部分第二硬遮 罩層322 ’待移除光阻芦仏 令間硬遮罩326。曰324後’即形成如第Μ圖所示之 15 1333676 請參閱第15圖。接下來於多晶矽層314以及中間硬遮 罩326上形成一第三硬遮罩層330。第三硬遮罩層330係 包含有氮化矽、氮氧化矽、氮碳化矽、碳化矽、含氧碳化 矽、或多矽氮化矽（SRN)等材料。 請參閱第15圖與第16圖。隨後進行一回蝕刻製程， 移除部分第三硬遮罩層330，以於中間硬遮罩326之側壁 形成一側壁硬遮罩336。而中間硬遮罩326與側壁硬遮罩 336係構成一複合硬遮罩340。值得注意的是，中間硬遮罩 326與側壁硬遮罩336係具有不同之蝕刻比。且如第15圖 所示，中間硬遮罩326具有之一寬度X與側壁硬遮罩336 具有之一款度Y之比值約為1:10。此外，側壁硬遮罩層336 之寬度係不大於10奈米（nanometer)。1333676 • IX. Description of the Invention: • Technical Field of the Invention The present invention relates to a method for fabricating a metal-oxide semiconductor (MOS transistor) using a composite hard mask layer. A method of MOS transistor fabricated by selective epitaxial growth (hereinafter referred to as SEG) growth. _ [Prior Art] Selective epitaxial growth (SEG) technology is mainly to form a crystal lattice with the same epitaxial layer as the substrate on the surface of a single crystal substrate, which is used in the fabrication of many semiconductor components, such as an elevated source. The polarized source/drain transistor has the advantages of good short channel characteristics and low parasitic resistance, and at the same time, by the presence of an increased epitaxial layer, leakage current can be avoided by excessively consuming the substrate during the formation of the metal telluride. The problem is that the embedded source/drain has the effect of improving the drain induced barrier lowering (DIBL) and punching effects and reducing the off-state leakage current. And the advantages of reducing power consumption. In general, the SEG technology first uses a surface cleaning process to completely remove the native oxide or other impurities on the surface of the substrate, depositing a stupid layer on the surface of the substrate, and causing the layer of the insect along the surface. The lattice structure of the surface of the substrate grows upward. Please refer to FIGS. 1 to 4, and 1333676 FIGS. 1 to 4 are schematic views of a conventional method for fabricating a strain 矽m〇S transistor using SEG technology. As shown in FIG. 1, a substrate 100, such as a substrate, is provided. A plurality of shallow trench isolation (STI) 102 are formed on the substrate 100, and a dielectric layer 112 is sequentially formed on the substrate. a polycrystalline layer 114, and a hard mask layer comprising a nitride or oxidized stone, wherein the hard mask layer is patterned by a lithography process, and the resulting patterned hard mask layer 120 is obtained. It is used to define the position and line width of a gate. Please refer to Figure 2. Next, an etching process is performed to remove a portion of the polysilicon layer 114 and the dielectric layer 112 to form a gate 110. An ion implantation process is then performed to form lightly doped drains (LDD) 116' in the substrate 100 on both sides of the gate 110, and a sidewall 118 is formed on the sidewall of the gate 11'. Next, please refer to Figure 3 and Figure 4. A recess 130 is then etched into the substrate 100 on either side of the gate 110 by using the patterned hard mask layer 120 and the sidewall spacers 118 as an etch mask. As shown in FIG. 4, the surface of the substrate 100 in the recess 13 is formed to form an epitaxial layer 132 during the subsequent seG process. Alternatively, an ion implantation process can be performed prior to etching the recess 130 or after forming the epitaxial layer 132 by the SEG process to form an embedded source/drain. It is worth noting that after forming the gate 110 and before performing the SEG process of forming the embedded source/drain, the substrate 100 is subjected to multiple etching and 7 1333676 cleaning steps, such as the polycrystalline layer 114. Post-cleaning, light doping, cleaning after ion implantation, ionization of sidewalls 118, post-cleaning of the sidewalls, etching of the grooves 130 and cleaning after etching, and cleaning before the SEG process, the etching and cleaning processes described above The hard mask layer 120 originally covering the polysilicon layer 114 is consumed. Therefore, before the SEG process is performed, the patterned patterned hard mask layer 120 exposes the underlying polysilicon layer 114, which is particularly caused by the edges of the patterned hard mask layer 120. When the subsequent SEG process is performed, the exposed corners of the polysilicon layer 114 form a layer of insect crystal which should not appear. The formation of such wormhole layers may cause ions immersed in the polysilicon layer 114 to diffuse into the epitaxial layers, thereby reducing the activation of the gate 110 or increasing the inversion of the gate 110. Affects component performance. These epitaxial layers 132 may even cause a short circuit between the gate 110 and the source/drain during subsequent processing, resulting in a drop in yield. In addition, since the hard mask layer 120 composed of tantalum nitride is not easily removed, it is often used in the subsequent removal step of removing the hard mask layer 120, for example, removing the hard mask layer 120 to the surface of the polysilicon layer 114. Forming a metal germanide affects the surface profile of the gate 110, and even removes the sidewalls 118 during the removal step, and damages the sidewalls of the gate 110 or the dielectric layer 112 at the bottom of the polysilicon layer 114. . Therefore, how to provide a hard mask layer which can effectively resist the loss of 1333676 caused by the etching and cleaning steps, and which can not cause damage to other components when removed, is an important subject in the field of semiconductor technology. SUMMARY OF THE INVENTION Accordingly, the present invention provides a method of fabricating a MOS transistor using a composite hard mask to improve the damage of other components in the hard mask layer due to consumption in the prior art, and to remove the hard mask layer. At the time of damage to other components. According to the scope of the invention, there is provided a method of fabricating a MOS transistor using a composite hard mask layer. The method includes providing a substrate having a dielectric layer and a polycrystalline layer, and subsequently forming at least one composite hard mask on the polysilicon layer, the composite hard mask comprising an intermediate hard mask and a cover The side wall of the intermediate hard mask sidewall is hard covered. Next, a first etching process is performed, wherein the polysilicon layer and the dielectric layer are etched by the composite hard mask to form a gate structure; and a second etching process is performed to form the gate structure. A recess is formed in each of the sides of the substrate. A selective remote crystal growth (SEG) process is then performed to form an epitaxial layer in the recesses, respectively. According to the scope of the invention, there is provided a method of fabricating a MOS transistor having a composite hard mask layer. The method includes providing a substrate having a dielectric layer and a polycrystalline layer on the surface, sequentially forming a first hard mask layer and a second hard mask layer on the film layer, and performing a micro 1333676 A shadow and etching process to remove a portion of the first hard mask layer and a portion of the second hard mask layer to form at least one intermediate hard mask. Forming a third hard mask layer covering the polysilicon layer and the intermediate hard mask, and performing an etching process to remove a portion of the third hard mask layer to form at least one sidewall hard mask, and The sidewall hard mask covers the sidewall of the intermediate hard mask to form a composite hard mask. Performing a first etching process, using the composite hard mask to etch the polysilicon layer and the dielectric layer to form a gate structure for the etch mask; and performing a second etching process on both sides of the gate structure A groove is formed in the substrate. A SEG process is then performed to form a stray layer in each of the grooves. According to the patent application scope of the present invention, there is further provided a composite hard mask for fabricating an MOS transistor, comprising a middle hard mask and a side hard mask, and the side wall is hard A mask is disposed on a sidewall of the intermediate hard mask layer. According to the scope of the invention, there is further provided a MOS transistor comprising a gate structure disposed on a substrate, and a composite hard mask layer disposed on the gate structure, the composite hard mask layer comprising An intermediate hard mask and a side wall hard mask are disposed on the side wall of the intermediate hard mask. The MOS transistor further includes a pair of lightly doped drains respectively disposed in the substrate on both sides of the gate structure; and a pair of the bases respectively disposed on both sides of the gate structure for use as the MOS One source of the transistor / 汲 1333676 • Extremely stupid layer. The method for fabricating a MOS transistor using a composite hard mask provided by the present invention utilizes the sidewall hard mask of the composite hard mask to effectively resist (4) and the wear caused by the cleaning step, thereby effectively protecting the shielded component; The intermediate hard mask as the main body can be removed without causing damage to other components, and can improve the yield. • [Embodiment] Please refer to Fig. 5 to Fig. 5 to Fig. 5 to Fig. 5 for a first preferred embodiment of the method for fabricating the composite hard mask layer provided by the present invention. As shown in Fig. 5, a substrate 2 is first provided, such as a substrate, and a plurality of shallow trench isolation (STI) 202 have been formed on the substrate 200. A dielectric layer 212, a polysilicon layer 214, and a first hard mask layer 22 are sequentially formed on the substrate 200. The first hard mask layer 22 includes: cerium oxide (SiO), tantalum nitride (SiN), cerium oxynitride (SiON), carbonitride (SiCN), carbon carbide (SiC), Oxygen carbide fossil (SiOC), silicon-rich-nitride (SRN), high temperature oxide (HT0), anti-reflective bottom layer, or di(tert-butylamino) stone (3丨8(^1'1:-1) is 丫1311^11〇)8 as 1^, 6丁6 into 8). A photoresist layer 222 is formed on the first hard mask layer 220, and the photoresist layer 222 is patterned by a lithography process. 11 1333676 See Figure 6. Next, an etching process is performed to remove a portion of the first hard mask layer 220 by using the patterned photoresist layer 222 to form an intermediate hard mask 224. Please refer to Figure 7. Subsequently, a second hard mask layer 230 is formed over the polysilicon layer 214 and the intermediate hard mask 224. The second hard mask layer 230 contains tantalum nitride, hafnium oxynitride, niobium carbide, niobium carbide, niobium oxide, or tantalum nitride (SRN). The second hard mask layer 230 and the first hard mask layer 220 have different etching selectivity ratios. Please refer to Figure 8. Next, an etching back process is performed to remove a portion of the second hard mask layer 230 to form a sidewall hard mask 234 on the sidewall of the intermediate hard mask 224. The intermediate hard mask 224 and the side wall hard mask 234 form a composite hard mask 240. As previously mentioned, the intermediate hard mask 224 and the sidewall hard mask 234 have different etch selectivity ratios. And as shown in Fig. 8, the intermediate hard mask 224 has a width X and a side wall hard mask 234 having a ratio Y of about 1:10. Further, the sidewall hard mask layer 234 has a width of no more than 10 nanometers. The composite hard mask 240 provided in the first preferred embodiment is used to define the position of a gate structure 210 in a SEG process. Referring to FIG. 9, a first etching process is performed to etch the film layer 214 and the dielectric layer 212 via the composite hard mask 240 to form a gate structure 210. Since the complex 12 1333676 hard mask 240 is used to define the position and line width of the gate structure 21 ,, after performing the lithography process of patterning the first photoresist layer 222, a trimming can be performed. The step of trimming the patterned first photoresist layer 222; or after the etching process for forming the intermediate hard mask 224, performing a trimming step for trimming the intermediate hard mask 224. Briefly, the width of the intermediate hard mask 224 can be adjusted by the trimming step 'this first preferred embodiment', and the width of the sidewall hard mask 234 can be supplemented to define the line width of the gate structure 21〇. Referring to FIG. 10, an ion implantation process is then performed to form a lightly doped drains (LDD) 216 in the substrate 200 on both sides of the gate structure 210, and in the gate structure 210. The sidewall defines a sidewall 218. The sidewall 218 and the composite hard mask 240 are used as an etch mask in a second etching process to form a recess 250 in the substrate 2 〇 on both sides of the gate structure 21 . Please refer to Figure 11. The surface of the substrate 200 in the recess 250 is formed by a SEG spear to create a strand of day 252 as an embedded source/no pole. Of course, an ion implantation process can be performed prior to etching the recess 250 or after forming the epitaxial layer in the SEG process to form an embedded source/drain as described above. If the MOS electro-crystal system is a PM〇s transistor, the embedded source/drain system includes bismuth telluride (SiGe), etc.; if the M〇s electro-crystalline system-NM〇s transistor, the embedded source The / bismuth system includes bismuth carbide (Sic) and the like. In addition, 13 1333676 • The method provided by the first preferred embodiment is not limited to the fabrication of the aforementioned embedded source/drain, which can also be used to fabricate raised source/drain or Planer source/drain. Since the substrate 200 is subjected to multiple etching and cleaning steps before performing the SEG process of forming the embedded source/drain, for example, the polysilicon layer 214 is cleaned after etching, the lightly doped drain 216 is implanted, and the sidewall is cleaned. Sub-218 etching and post-etch cleaning, recess 25 etch and post-etch cleaning, and SEG process 刖 cleaning, the above-mentioned money engraving and cleaning process will consume the composite hard mask 240. However, since the etching option of the sidewall hard mask 234 of the composite hard mask 240 is different from the etching ratio of the intermediate hard mask 224, the etching rate of the sidewall hard mask 234 is much lower than that of the intermediate hard mask 224. Therefore, the etching and cleaning process described above greatly reduces the wear and tear of the edge of the composite hard mask 24, so that the gate structure 210 covered by the composite hard mask 24 is not exposed after the etching and cleaning process. Therefore, the edge of the gate structure 210 is formed in the SEG process without forming an epitaxial layer, reducing the activation degree of the gate structure 210 or increasing the reversal of the gate structure 21〇, which affects the gate performance. In addition, since the main body of the composite hard mask 240 is still the intermediate hard mask 224, the subsequent steps of removing the composite hard mask 234 are less likely to damage other components, such as affecting the surface profile of the gate 210, and even the removal step. Medium " removes the side wall 218. 1333676 Referring to Figures 12 through 16, Figures 12 through 16 are a second preferred embodiment of a method of fabricating a composite hard mask layer according to the present invention. As shown in Fig. 12, a substrate 300, such as a substrate, is initially provided, and a plurality of shallow trench isolations (STIs) 302 have been formed on the substrate 300. A dielectric layer 312, a polycrystalline hard layer 32G and a second hard mask layer 322 are then sequentially formed on the substrate 300. The first hard mask layer 32 includes a carbon cut ((10)), a nitrogen cut (SiN), a nitrogen oxynitride (Sl〇N), a nitrogen carbon cut (SiCN), a carbonized state (6), an oxygenated carbonized fossil (s1〇C), multi-cut (SRN), high-temperature oxygen-cut _), anti-reflective underlayer, or -(t-butylamino) zebra (BTBAS). The second hard mask layer 322 includes oxidized hair, nitrogen cut, oxynitride, nitrogen carbon cut, ^ (four), oxygen-containing carbon cut, multi-wei cut (SRN), high temperature oxygen cut (Ητ〇), anti-reflection Bottom I (tert-butylamino) montanane (BTBAS) and other materials. The first hard mask layer 3 has a different etching ratio than the second hard mask layer 322. :: Read Figure 13 and Figure 14. Performing a lithography and etching process, • first forming a photoresist layer 324 on the second hard masking process to pattern the photoresist bank 324, ^ micro" a 324 and using the patterned photoresist layer 324 to perform a The process removes a portion of the first hard mask layer 320 and a portion of the second hard mask layer 322 'to remove the photoresist reed between the hard masks 326. After the 曰 324', the 15 is formed as shown in FIG. 1333676 Please refer to Fig. 15. Next, a third hard mask layer 330 is formed on the polysilicon layer 314 and the intermediate hard mask 326. The third hard mask layer 330 includes tantalum nitride, hafnium oxynitride, and nitrogen carbonization. Materials such as tantalum, tantalum carbide, niobium carbide, or tantalum nitride (SRN). See Figures 15 and 16. Next, an etching process is performed to remove a portion of the third hard mask layer 330. A sidewall hard mask 336 is formed on the sidewall of the intermediate hard mask 326. The intermediate hard mask 326 and the sidewall hard mask 336 form a composite hard mask 340. It is noted that the intermediate hard mask 326 and the side wall The hard mask 336 has different etching ratios, and as shown in Fig. 15, the intermediate hard mask 326 has a width X and a side wall hard The mask 336 has a ratio of one degree Y of about 1: 10. Further, the width of the side wall hard mask layer 336 is no more than 10 nanometers.
本第二較佳實施例所提供之複合硬遮罩340係同於前 述之第一較佳實施例，可用於一 SEG製程中，定義一閘極 之位置及線寬。由於複合硬遮罩340係用以定義閘極之線 寬，因此在圖案化光阻層324之微影製程後，係可進行一 修整步驟，用以修整該圖案化之光阻層324 ;或者在形成 中間硬遮罩326之蝕刻製程後，進行一修整步驟，用以修 整中間硬遮罩326。簡單地說，藉由修整步驟，本第二較 佳實施例係可調整中間硬遮罩326之寬度，而輔以側壁硬 遮罩336之寬度以定義閘極之線寬。由於後續之製作MOS 16 1333676 電晶體之製程係同於第一較佳實施例所述，故於此不再贅 述。 由於複合硬遮罩340中之側壁硬遮罩336之蝕刻率不 同於中間硬遮罩326之敍刻率’或者說，側壁硬遮罩％6 之钱刻率遠低於中間硬遮罩326，因此半導體製程所需之 钱刻及清洗製程對於複合硬遮罩340邊緣之耗損將會大幅 降低，也使得複合硬遮罩340所覆蔽之元件，如本第二實 施例中所述之閘極，將不至於在上述蝕刻及清洗製程後暴 露出來，導致閘極邊角於SEG製程時形成不應出現的磊晶 層，降低閘極之活化程度或增加閘極之反轉，影響閘極表 現。 另外；由於複合硬遮罩340之主體仍為中間硬遮罩 326，在後續去除複合硬遮罩336之步驟，較不易損及其他 元件，例如影響閘極之表面輪廓，甚至於移除步驟中將側 壁子一同移除。 請再參閱第9圖以及第16圖。綜上所述，本發明係提 供一種用以製作MOS電晶體之複合硬遮罩層（hybrid hard mask) 240/340，其包含有一中間硬遮罩（middle hard mask) 224/326以及一設置於中間硬遮罩224/326之側壁之側壁硬 遮罩（spacer hard mask) 234/336。而中間硬遮罩 224/326 更 C S ) 17 1333676 . 可包含如第16圖所示之—底部遮罩層（bottomhardmask) ·- 320與一頂部硬遮罩（top hard mask) 322。底部硬遮罩32〇 包含有氧化矽（si〇)、氮化矽（SiN)、氮氧化#(Si〇N)、氮碳 化矽（SiCN)、碳化矽（SiC)、含氧碳化矽（Si〇c)、多矽氮化 - 矽（SRN)、高溫氧化矽(HT〇)、抗反射底層、或二（特丁基 氨基）矽烷(BTBAS)。頂部硬遮罩322包含有氧化矽、氮 化矽、氮氧化矽、氮碳化矽、碳化矽、含氧碳化矽、多矽 φ 氮化矽（SRN)、高溫氧化矽(HTO)、抗反射底層、或二（特 丁基氨基）矽烷(BTBAS)等材料。而底部硬遮罩層32〇與 頂部硬遮罩層322係具有相同或不同之蝕刻比。 、 側壁硬遮罩234/336係包含有氮化矽、氮氧化矽、氮 碳化矽、碳化矽、含氧碳化矽、或多矽氮化矽（SRN)等材 且側壁硬遮罩234/336與中間硬遮罩224/326係具有 f 蝕刻比。中間硬遮罩2 2 4/3 2 6之一寬度與側壁硬遮軍不冋之 • 234/336之-寬度具有-比值，且該比值約為1:ι 此外， 側壁硬遮罩層234/336之寬度係不大於1〇奈求 (nanometer) 〇 由於在SEG製程中，負載各種元件之基底會經過多a 蝕刻以及清洗過程，而用以定義元件位置及大小之複合人 遮罩由於側壁硬遮罩之蝕刻比不同於中間硬遮罩之硬 比，即側壁硬遮罩之蝕刻比遠低於中間硬遮罩，因此2述 18 1333676 * 之钱刻及清洗製程對於複合硬遮罩邊緣之耗損將會大幅降 : 低，也使得複合硬遮罩所覆蔽之閘棰結構不至於在上述蝕 刻及清洗製程後暴露出來，而後續製稃中耗損或者形成不 . 應出現的磊晶層而影響了閘極結構的性能表現。例如於本 - 第一較佳實施例與第二較佳實施例所述，SEG製程中之磊 晶層將不會生成於閘極邊角，影響問椏活化程度或増加閘 極之反轉。此外，由於複合硬遮罩之主體仍為中間硬遮罩， _ 在後續去除複合硬遮罩之步驟中，亦較不易損及其他元件。 簡單地說’本發明所提供之利用複合硬遮罩之M〇s 電晶體之製作方法，係利用側壁硬遮罩有效抵抗蝕刻與清 洗步驟所造成之耗損，並保護其遮蔽之元件；同時作為主 體之中間硬遮罩係可於移除時不至造成其他元件之損傷， 故可提升良率。 _ 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第4圖係為一習知利用SEG技術製作應變矽M〇 電晶體之方法之示意圖。 第5圖至第11圖係為本發明所提供之複合硬遮罩層之製作 •方法之第-較佳實施例。 、 19 1333676 第12圖至第16圖係為本發明所提供之複合硬遮罩層之製 作方法之第二較佳實施例。The composite hard mask 340 provided in the second preferred embodiment is similar to the first preferred embodiment described above and can be used in an SEG process to define the position and line width of a gate. Since the composite hard mask 340 is used to define the line width of the gate, after the lithography process of the patterned photoresist layer 324, a trimming step may be performed to trim the patterned photoresist layer 324; or After the etching process to form the intermediate hard mask 326, a trimming step is performed to trim the intermediate hard mask 326. Briefly, by the trimming step, the second preferred embodiment adjusts the width of the intermediate hard mask 326, supplemented by the width of the sidewall hard mask 336 to define the line width of the gate. Since the subsequent fabrication of the MOS 16 1333676 transistor is the same as that described in the first preferred embodiment, it will not be described herein. Since the etching rate of the sidewall hard mask 336 in the composite hard mask 340 is different from the etch rate of the intermediate hard mask 326, or the sidewall hard mask %6 is much lower than the intermediate hard mask 326, Therefore, the cost and cleaning process required for the semiconductor process will greatly reduce the loss of the edge of the composite hard mask 340, and also the components covered by the composite hard mask 340, such as the gate described in the second embodiment. It will not be exposed after the above etching and cleaning process, resulting in the formation of an epitaxial layer that should not occur during the SEG process, reducing the activation of the gate or increasing the reversal of the gate, affecting the gate performance. . In addition, since the main body of the composite hard mask 340 is still the intermediate hard mask 326, the subsequent steps of removing the composite hard mask 336 are less likely to damage other components, such as affecting the surface profile of the gate, even during the removal step. Remove the side walls together. Please refer to Figure 9 and Figure 16 again. In summary, the present invention provides a composite hard mask 240/340 for fabricating a MOS transistor, which includes a middle hard mask 224/326 and a The side hard mask of the side wall of the intermediate hard mask 224/326 is 234/336. The intermediate hard mask 224/326 is further C S ) 17 1333676 . It may include a bottom hard mask · - 320 and a top hard mask 322 as shown in FIG. 16 . The bottom hard mask 32 includes bismuth oxide (si〇), tantalum nitride (SiN), oxynitride #(Si〇N), niobium oxynitride (SiCN), niobium carbide (SiC), niobium oxide (Si) 〇c), polyfluorene-nitride-strontium (SRN), high-temperature yttrium oxide (HT〇), antireflective underlayer, or di(tert-butylamino)decane (BTBAS). The top hard mask 322 comprises ruthenium oxide, tantalum nitride, ruthenium oxynitride, niobium carbide, niobium carbide, niobium oxycarbonate, polyfluorene yttrium nitride (SRN), high temperature yttrium oxide (HTO), antireflection underlayer Or a material such as di(tert-butylamino) decane (BTBAS). The bottom hard mask layer 32 and the top hard mask layer 322 have the same or different etching ratios. The sidewall hard mask 234/336 comprises tantalum nitride, niobium oxynitride, niobium carbide, tantalum carbide, niobium carbide, or polysilicon nitride (SRN) and the sidewall hard mask 234/336 It has an f-etch ratio with the intermediate hard mask 224/326. The middle hard mask 2 2 4/3 2 6 has a width and side walls that are hard to cover. • 234/336-width has a ratio, and the ratio is about 1:ι. In addition, the side wall hard mask layer 234/ The width of 336 is not more than 1 nanometer. 〇Because in the SEG process, the substrate carrying various components will undergo multiple a-etching and cleaning processes, and the composite mask used to define the position and size of the component is hard. The etching ratio of the mask is different from that of the intermediate hard mask, that is, the etching ratio of the sidewall hard mask is much lower than that of the intermediate hard mask, so the description of the 18 1333676 * money and cleaning process for the edge of the composite hard mask The loss will be greatly reduced: low, and the gate structure covered by the composite hard mask will not be exposed after the above etching and cleaning process, and the subsequent plating will be worn or formed without the occurrence of the epitaxial layer. Affects the performance of the gate structure. For example, in the first preferred embodiment and the second preferred embodiment, the epitaxial layer in the SEG process will not be generated at the gate corner, affecting the degree of activation or the reversal of the gate. In addition, since the main body of the composite hard mask is still an intermediate hard mask, _ in the subsequent step of removing the composite hard mask, it is less likely to damage other components. Briefly, the method for fabricating a M〇s transistor using a composite hard mask provided by the present invention utilizes a sidewall hard mask to effectively resist the wear and tear caused by the etching and cleaning steps, and protects the shielded component thereof; The middle hard mask of the main body can not be damaged by other components when removed, so the yield can be improved. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 4 are schematic views showing a conventional method of fabricating a strain 矽M〇 transistor using SEG technology. Figures 5 through 11 are the first preferred embodiment of the method of making a composite hard mask layer of the present invention. 19 1333676 Figures 12 through 16 are second preferred embodiments of the method of fabricating a composite hard mask layer of the present invention.
【主要元件符號說明】 100 基底 102 淺溝隔離 110 閘極 112 介電層 114 多晶矽層 116 輕摻雜汲極 118 側壁子 120 圖案化硬遮罩層 130 凹槽 132 蠢晶層 200 基底 202 淺溝隔離 210 閘極 212 介電層 214 膜層 216 輕摻雜汲極 218 側壁子 220 第一硬遮罩層 222 光阻層 224 中間硬遮罩 230 第二硬遮罩層 234 側壁硬遮罩 240 複合硬遮罩 250 凹槽 252 遙晶層 300 基底 302 淺溝隔離 312 介電層 314 膜層 320 第一硬遮罩層 322 第二硬遮罩層 324 光阻層 326 中間硬遮罩 330 第三硬遮罩層 336 側壁硬遮罩 340 複合硬遮罩 20[Main component symbol description] 100 substrate 102 shallow trench isolation 110 gate 112 dielectric layer 114 polysilicon layer 116 lightly doped gate 118 sidewall spacer 120 patterned hard mask layer 130 recess 132 stupid layer 200 substrate 202 shallow trench Isolation 210 Gate 212 Dielectric Layer 214 Film Layer 216 Lightly Doped Dippole 218 Sidewall Sub 220 First Hard Mask Layer 222 Photoresist Layer 224 Intermediate Hard Mask 230 Second Hard Mask Layer 234 Side Wall Hard Mask 240 Composite Hard mask 250 recess 252 tele-crystal layer 300 substrate 302 shallow trench isolation 312 dielectric layer 314 film layer 320 first hard mask layer 322 second hard mask layer 324 photoresist layer 326 intermediate hard mask 330 third hard Mask layer 336 side wall hard mask 340 composite hard mask 20