1327272 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種監視計時器，特別係指一 種監視計時器致能電路及其方法。 【先前技術】1327272 IX. Description of the Invention: [Technical Field] The present invention relates to a watchdog timer, and more particularly to a watchdog timer enable circuit and method therefor. [Prior Art]
車人體執行的fe疋度對任何工作平台（work platform)來 說都是很重要的基本要求。然而，像微處理器當機（crash) 或程式執行出問題等卻也常常是使用者最常碰見的問題。 因此’需要在微處理器中設置監視計時器（watchd〇g timer) ’來防止微處理器執行應用程式時，發生問題，即應 用程式跳到未知的地方或無法跳出無窮迴圈等。 當微處理益正常地執行應用程式時，監視計時器不會 計數到終值，且會在計數到終值前，清除計數内容，使監 視=時器重置到初值’因此不會輸出重置信號來重置微處 ，态。當微處理器在執行應用程式發生問題時，監視計時 益則會發生溢位，並輪出—個重置信號使系統重置，使微 處理益恢復正常工作’此即為熱重置（丽⑽对）。 在過去，設計者會在微處理器令 ;能電路，，計時器，以重新啟動系統：而十； -Li視電路僅靠—個硬體控制單元所輸出的 :在2訊的;境中時，硬體致能訊號很容易； 致此贫成失ι，因此造成微處理器無法恢復正常工作。 【發明内容】 5 132.7272 本發明為一監視計時器致能電路及其方法，係以結合 硬體致能方法及軟體致能方法，來增加防止微處理器因外 在環境因素造成監視計時器失效的能力，即使其中一種致 能方法失效，仍能致能監視計時器，以進行微處理器之系 統重置的動作。 依據本發明所提出之監視計時器致能電路及其方 法，其監視計時器致能電路包含：硬體控制單元、軟 體控制單元、控制及運算電路及監視計時器。 • 在第一實施例中，首先啟動硬體致能，硬體控制單元 根據一第一時脈訊號，由微處理器内之記憶單元中，操取 預先設定的硬體致能值，以產生硬體致能訊號。接著，啟 動軟體致能，軟體控制單元根據一第二時脈訊號，由微處 - 理器内之複數個資料線中，擷取複數個軟體致能值以產生 . 軟體致能訊號。最後，當完成了軟體致能及硬體致能的設 定後，分別將硬體致能訊號及軟體致能訊號作運算，以產 生致能控制訊號。最後，當系統不正常時監視言v時器會重 Φ 置微處理器。 在第二實施例中，與第一實施例不同點在於，係先啟 動軟體致能，再啟動硬體致能，使系統發生不正常時，監 • 視計時器可以重置微處理器。 • 在第三實施例中，與第一及第二實施例不同點在於’ 係同時啟動硬體致能及軟體致能，使系統發生不正常時’ 監視計時器可以重置微處理器。 【實施方式】 請參考第一圖所示，其係為本發明内容之監視計時器 6 ^能電路之方塊示意圖。本發明之監視計時器致能電路可 <置於微處理器内’包含—硬體控制單A (hardwale 咖_ unit) 10、一軟體控制單元（software __响 :: '。-控制及運算電路30及一監視計時器(watchd〇g如的 硬體控制單元10連結於控制及運算電路3〇’用以輪 出硬體致能訊號(hardware enable signal)至控制及運算電 路30。顧名思義，硬體控制單元1〇内之硬體致 hardware enable value)係於設計者在設計微處理器（未繪 :)時就已設定完成，且燒錄在微處理器内之記憶單元（未 、’’曰不）中。當微處理器通電重置(power_〇nreset)後，便會產 生—時脈訊號(dock)至硬體控制單元1〇内的暫存器（丄硌 示^，用以控制硬體控制單元丨0來擷取記憶單元中的硬▲ 值至暫存益中’以進一步地產生硬體致能訊號。此外， :通兒重置-次’硬體控制單s 1G就由記憶單元中榻取至 :個位元(bk)的硬體致能值至暫存器中。硬體致能值可 以係零（0 )或壹（1 )。 敕體控制單元20連結於控制及運算電路3〇，用以輸 庫人體致能訊號至控制及運算電路3〇。軟體控制單元2〇 =之軟體致能值（software enable valueM系由微處理器内之 =個資料線（databus)所提供’再配合由設計者在設定 =控制單⑽⑽暫存器（未繪示）的值所產生的時脈 在進—步地產生軟體致能訊號。其中，軟體致能值 係為令或壹的任意值。 拴制及運异電路3〇連結於監視計時器仙。用以當微 處理器執行應用程式發生錯誤時，將硬體致能訊號及軟體 132.7272 1 一双此役刺汛號（enable contml s^nal)，^：；；1 •^tl?^(resetsi^ ' ^ 糸統重置（d”pi.eset)。此外，由於控制及運 用“來運算L由硬體控制單^1G所提供之硬體‘訊號“ 軟體控制單70 2 G所提供之軟體致能訊號，以產生: 訊號，因此控制及運算電路3G係由至少—個邏輯電The performance of the car body is a very important basic requirement for any work platform. However, problems such as microprocessor crashes or program execution problems are often the most common problems users encounter. Therefore, it is necessary to set a watchdog timer (watchd〇g timer) in the microprocessor to prevent the microprocessor from executing the application, that is, the application jumps to an unknown place or cannot jump out of an infinite loop. When the microprocessor executes the application normally, the watchdog timer does not count to the final value, and the count content is cleared before the count reaches the final value, so that the monitor=timer is reset to the initial value' so the output is not Set the signal to reset the micro, state. When the microprocessor is experiencing problems with the application, the monitoring timing will overflow, and a reset signal will be reset to reset the system, so that the microprocessor will resume normal operation. This is a hot reset. (10) Yes). In the past, the designer would be in the microprocessor; the circuit, the timer, to restart the system: and the ten; -Li view circuit is only output by a hardware control unit: in the 2; When the hardware enables the signal, it is easy; the poor result is lost, so the microprocessor can not resume normal work. SUMMARY OF THE INVENTION 5 132.7272 The present invention is a watchdog timer enabling circuit and method thereof, which combines a hardware-enabled method and a software-enabled method to increase the prevention of a microprocessor's watchdog timer failure due to external environmental factors. The ability to enable a watchdog timer to perform a system reset of the microprocessor, even if one of the enabling methods fails. According to the monitoring timer enabling circuit and method thereof, the monitoring timer enabling circuit comprises: a hardware control unit, a software control unit, a control and arithmetic circuit, and a watchdog timer. In the first embodiment, the hardware enabling is first initiated, and the hardware control unit generates a predetermined hardware enable value from the memory unit in the microprocessor according to a first clock signal to generate Hardware-enabled signal. Then, the software enable unit starts, and the software control unit generates a plurality of software enable values from the plurality of data lines in the micro-processor according to a second clock signal to generate a software enable signal. Finally, after the software-enabled and hardware-enabled settings are completed, the hardware-enabled signal and the software-enabled signal are respectively operated to generate an enable control signal. Finally, when the system is not normal, the monitor will reset the microprocessor. In the second embodiment, the difference from the first embodiment is that the software enable is enabled first, and then the hardware enable is enabled, so that when the system malfunctions, the monitor timer can reset the microprocessor. • In the third embodiment, the difference from the first and second embodiments is that the hardware enable and the soft body enable are simultaneously enabled to cause the system to malfunction. The watchdog timer can reset the microprocessor. [Embodiment] Please refer to the first figure, which is a block diagram of the monitoring timer of the present invention. The watchdog timer enabling circuit of the present invention can be <located in the microprocessor' included - hardware control unit A (hardwale _ unit) 10, a software control unit (software __ ring:: '.- control and The arithmetic circuit 30 and a watchdog timer (the hardware control unit 10 is connected to the control and arithmetic circuit 3' for rotating the hardware enable signal to the control and operation circuit 30. As the name suggests The hardware enable value in the hardware control unit 1 is set by the designer when the microprocessor is designed (not shown), and is programmed in the memory unit of the microprocessor (not, ''曰不)'. When the microprocessor power-on reset (power_〇nreset), it will generate a clock signal (dock) to the scratchpad in the hardware control unit 1 (showing ^, It is used to control the hardware control unit 丨0 to retrieve the hard ▲ value in the memory unit to temporarily save the hardware to further generate the hardware enable signal. In addition, the passer resets the second 'hardware control list s 1G It is taken from the memory unit to: the hardware enable value of one bit (bk) to the scratchpad. The enable value can be zero (0) or 壹 (1). The body control unit 20 is coupled to the control and operation circuit 3A for transmitting the human body enable signal to the control and operation circuit 3. The software control unit 2 = software enable value (software enable valueM is provided by the data line in the microprocessor) and then generated by the designer in the setting = control list (10) (10) register (not shown) The clock generates the software enable signal in a stepwise manner, wherein the software enable value is any value of the order or the 壹. The control and the operation circuit 3 are connected to the watchdog timer. When an error occurs in the execution of the application, the hardware enable signal and software 132.7272 1 pair of thorns (enable contml s^nal), ^:;;1 •^tl?^(resetsi^ ' ^ reset (d"pi.eset). In addition, due to the control and operation of the software-enabled signal provided by the hardware control unit 70 2 G provided by the hardware control unit, the hardware control unit 70 2 G provides: Signal, so the control and operation circuit 3G is composed of at least one logic
成，例如由反或閘（NOR)或反及閘（NAND)所組成、。The composition is composed of, for example, a reverse OR gate (NOR) or a reverse gate (NAND).
致能訊號作運算，來產生 舉例來說’請參考第二圖所示，其係為本發明 硬體控制單元之方塊示意圖。硬體控制單元1〇包含一圮情 單元110、至少一緩衝電路(buffer circuit) 13〇及:少二二 體暫存單元(hardware register)丨5〇。由於執行硬體致=所需 之硬體致能值係預先儲存在硬體控制單元1〇内之記情^ 元110中，因此硬體控制單元10中之硬體暫存單元 會根據一第一時脈訊號來擷取記憶單元110中的硬體致能 值，其中’此第一時脈訊號係為硬體暫存單元153之工^ 時脈（load clock)，每當微處理器通電重置—次，微處理 為就會產生此弟一時脈訊號。 另外一方面，在擷取硬體致能值至硬體暫存單元15〇 的過程中’會先將硬體致能值先傳送至緩衝電路13〇來作 緩衝放大的動作，以增加硬體致能值的驅動能力（driving ability )。因此’記憶單元110可以係一次可程式記憶單元 (one-time programmable cell, OTP cell) ?即导隹揮發十生 |己十舞 體（non-volatile memory )的可抹除程式化唯讀記憶體 (Erasable Programmed Read On]y Memory, EPROM)。硬體暫存 單元150可以係由正反器所組成之邏輯電路。 8 元之；：其係為本發明内容之軟體控制單 1塊W0。軟體控制單元2G包含—第—軟體暫存單 ㈣㈣212、一第二軟體暫存單元別、-第 ^ =暫存早216、-第四軟體暫存單元218及碼 平兀（decoding unit) 240。 軟二:根::第二時脈訊號，由每-暫存單元（第- ^泉㈤姻擷取軟體致能值’以組成一多位元組。此 脈減料設計者在設計這純體㈣_時所產 的工作時脈。此多位元組係由複數個零或•壹所组成。 因此第-軟體暫存單元212、第二軟體暫存單力214、第三 軟體暫存單S训及第四軟體暫存單元⑽皆可以係正反 器。 ’、 接著，解碼單元240中之第—反向電路（_ C—241會將由第一軟體暫存單元212擷取出來的軟體 致能值反向，苐二反向電路243會將由第三軟體暫存單元 216操取出來的軟體致能值反向’並且配合由兩個軟 體暫存單元（第二軟體暫存單元214及第四軟體暫存單元 218)所擷取的軟體致能值，以提供致能控制電路245來作 運具’產生一車人體致能訊號。因此’第—反向電路241及 第二反向電路243皆係為反閘（NOT)，致能控制電路245 則可以係為反及閘（NAND)。 請參考第四圖所示’其係為本發明内容之第一實施例 且一併參考第一、 會預先設定執行硬 之監視計時器致能電路運作之流程圖 二、三圖。設計者在設計微處理器時 體致成所需要的硬體致此值’並燒錄在微處理器内之記情 132.7272 單元110中。 百先，當微處理器啟動電 時器致能電路會先啟動硬 :，D步驟S41G，監視計 器致能電路根據第—時脈；^ ’如步驟_。監視計時 由微處理器 内之記憶制硬體控制單元二 能值至所對應之硬體暫存單元。取】個位元的硬體致 中之硬體致能值將經由緩败，f是說，記憶單元110 元心以產生硬體致能專送至硬體暫存單 設計者在設計這些硬體暫存 :f，弗—時脈訊號係為 實施以⑽位，。硬體致能』^ 接奢’ ！〇_視什時态致能電跃合 S430。監視計時器致能電路^㈣軟體致能，如步驟 制:4制早兀2〇由微處理器内之資料線D0〜D3中，分 固位元的軟體致能值至資料線d〇〜d3所對應之軟 月二曰^單元。也就是說，資料線D〇上之敕體致能值將傳 迗至第-軟體暫存單元212’資料線m上的軟體致能值將 傳送至第二軟體暫存單元214,資料線D2上的軟體致能值 將傳送至第二軟體暫存單元216,以及資料線D3上的軟體 致能值將傳送至第四軟體暫存單元218。其中：第二時脈 訊號係為設計者在設計這些軟體暫存單元時所產生的工作 時脈。 解碼單元240中之第一反向電路241會將第一軟體暫 存單元212内之軟體致能值反向，第二反向電路243亦會 將第三軟體暫存單元216内之軟體致能值反向。最後，這 兩個反向後之軟體致能值及其他兩個未反向的軟體致能值 1327272 ^專㈣電路245巾作運算，料生軟體致能訊 以^係零^這四個位元的軟體致紐皆係為任意值，即可 欠體控制單元2〇 '系為高電位致_ ⑴⑴）。:資料線D〇〜D3戶斤提供之任*的多位元組為 向後第一反向電路241及第二反向電路243的反 除致^ΗΪ 〇)的多位元組。當軟體控制單元20預設解 將軟^制ί。1111)時’軟體致能訊號將會為一，因此不會 日士哭to工隹早凡2〇失能’且致能控制電路245會使監視計 ,40 £ 〇 # D〇^3 為u_)’經過第—反向電路24i及第二反 路243的反向後，形成（im)的多位元組 i20因預=除致能組如_)時，職體致能訊號 =’ 使軟體控制單元2G失能，且致能控制電路曰245 不-疋會使監視計時器4〇進行系統重置。 因，’軟體控制單元20内之反向電路的數量係可 角牛除致能組而作調整。而解除 + ’:思者 能控制電路245來作調整。多位此:且係'边者夕位元組及致 要，由微處理器内之個 為軟體致能值的來源 貝料線中選擇部分資料線，作 =财時H輕電路以成了賴魏及硬體 及軟雜㈣衫㈣㈣㈣致能訊號 時器致能電路内之控=運出=軸號傳送至監視計 會將硬體致能訊號及軟體致二電：30 制訊號，如步驟S440。致〜致能控 双月b控制訊號可以係高電位致能或 1327272 低電位致能。 其中，軟體致能及硬體致能可以係高電位致能或低電 位致能（low enable)，而高電位致能係利用位元狀態為一時 致能，低電位致能則係利用位元狀態為零時致能。致能控 制訊號則可根據控制及運算電路、硬體致能訊號及軟體致 能訊號，來決定係高電位致能或低電位致能。 最後，監視計時器致能電路會判斷微處理器是否發生 異常，如步驟S450。當微處理器未發生任何異常時，監視 計時器致能電路會進一步地將監視計時器内之計數内容清 除，即執行熱重置的動作，如步驟S460。當微處理器發生 了異常狀態，監視計時器致能電路會使監視計時器產生重 置訊號，以重置微處理器，如步驟S470。 請參考第五圖，其係為本發明内容之第二實施例之監 視計時器致能電路運作之流程圖，且一併參考第一、二、 三圖。首先，當微處理器啟動電源後，如步驟S510，監視 計時器致能電路會先啟動軟體致能，如步驟S520。 監視計時器致能電路會根據一第二時脈訊號，來控制 軟體控制單元20由微處理器内之資料線DO〜D3中，分別 擷取1個位元的軟體致能值至資料線D 0〜D 3所對應之軟體 暫存單元。解碼單元240中之第一反向電路241會將第一 軟體暫存單元212内之軟體致能值反向’第二反向電路243 亦會將第三軟體暫存單元216内之軟體致能值反向。最 後，這兩個反向後之軟體致能值及其他兩個未反向的軟體 致能值會傳送至致能控制電路245中作運算，以產生軟體 致能訊號。 接著，監視計時器致能電路會啟動硬體致能，如步驟 12 1327272 S530。監視計時器致能電路根擔 很據時脈訊號，來控制硬 Α制早兀10由微處理器内之記憶單元u〇巾，操取！ ㈣Μ硬體致能值至所對應之硬體暫存單元。也就是 記憶單元U〇中之硬體致能值將經由緩衝電路】30, 傳达至硬體暫存單元15〇，以產生硬體致能訊號。 白卜Γ =視、柄為致此電路皆完成了軟體致能及硬體致能 的§又疋後，分別將硬體控制單Α 1〇 卿控制單元2。所輸出的敕體致能訊二 W致能電路内之控制及運算電路3〇。控制及運管電路扣 ^將硬體缝訊號錄體致能訊财運: 制訊號，如步驟S54〇。 座生致肊抆 p最，，監視計㈣致能電路會騎微處理器是否發生 二2:?:當微處理器未發生任何異常時，監視 二Ί4會進一步地將監視計時器内之計數 除，即執行熱重置的動作，如步驟S56〇 / 了異常狀能，於讳呌卩士 + 田Μ誕t里态發生 ^现視s十日守裔致此黾路會使監視計時卷產生重 汛唬，以重置微處理器，如步驟S570。 視罐發明内容之第三實施例之監 一史丁„。双月b甩路運作之流程圖，且一併參考第―、二、 二，二百先’當微處理器啟動電源後，如步驟S61.0，監視 致能糾會同時啟動硬體致能及倾致能，如步驟 監視計㈣致能電路啟動軟體魏時，監視計時器 由根據：第二_訊號，來控制軟體控制單元20 體致=信^之資料線D〇〜D3中，分別擷取1個位元的軟 "^至貪料線1^〜D3所對應之軟體暫存單元。解碼單 13 元240中之第一反向電袼241會將第一軟體暫存單元 體致能值反向，第二反向電路243亦會將第三軟體 二二％ 216内之軟體玫能值反向。最後，這兩個反向後 能值及其他兩傾未反向的軟體致能值會傳送至致 此控，電路245中作運算，以產生軟體致能訊號。 監視料㈣能電路啟動硬體致能時，監視計時器 路會根據第一時脈訊號’來控制硬體控制單元10 之記憶單元11G中’操取1個位元的硬體致 ==之硬體暫存單元。也就是說，記憶單元no h致I值將經由緩衝電路13Q，傳送至硬體暫存單 疋150，以產生硬體致能訊號。 視料11致能電料完成了軟體魏及硬體致能 體二：^將Γη體控制單元10所輸出的硬體 二!所輸出的軟體致能訊號傳送至監視計時器 將制及運算1路3Q。控制及運算電路3〇會 號及軟體致能訊號作運算，以產生致能控制 5孔號’如步戰S630。 _£ a最i皿視构③致能電路會判斷微處理器是否發生 計時器致能電路會進何異常時，監視 除，即執行孰重置的動;;見物器内之計數内容清 了異常狀態致=:r。當微處理器發生 丁"°致月匕电路會使監視計時器產生重 置喊’以重置微處理器，如步驟s_。 重 視▲十二二=所&供之優點在於，增加軟體致能，使監 時=^路不易受到環境因素的影響，造成監視計 1327272 本發明内容所提供之另一優點在於，硬體致能值係預 先燒錄在微處理器内之記憶單元中。 本發明内容所提供之再一優點在於，用以產生軟體致 能訊號之多位元組係由微處理器内之複數個資料線所提 供，且係為零或壹所組成的任意值。 本發明内容所提供之再一優點在於，軟體控制單元係 由複數個軟體暫存單元及一個由至少一個反向電路及一個 致能控制電路所組成的解碼單元所組成，而軟體暫存單元 之數量隨著使用者的需求而調整。 本發明内容所提供之再一優點在於，硬體致能訊號、 軟體致能訊5虎及致能控制訊號可以係南電位致能或低電位 致能，且隨使用者需求而調整。 所附圖式僅提供參考與說明用，並非用來對；發明加 以限制者。惟以上所述僅為本發明之較佳可行實施例，非 因此即侷限本發明之專利範圍，故舉凡運用本發明說明書 及圖示内容所為之等效結構變化，均同理包含於本發明之 範圍内，合予陳明。 【圖式簡單說明】 第一圖係為本發明内容之監視計時器致能電路之方塊 示意圖； 第二圖係為本發明内容之監視計時器致能電路内之硬 體控制單元之方塊示意圖； 第三圖係為本發明内容之監視計時器致能電路内之軟 體控制單元之方塊示意圖； 15 1327272 第四圖係為本發明内容之第一實施例之監視計時器致 能電路執行系統重置之流程圖； 第五圖係為本發明内容之第二實施例之監視計時器致 能電路執行系統重置之流程圖；以及 第六圖係為本發明内容之第三實施例之監視計時器致 能電路執行系統重置之流程圖。 【主要元件符號說明】 • 硬體控制單元 10 記憶單元 110 缓衝電路 Π0 硬體暫存單元 150 • 軟體控制單元 20 第一軟體暫存單元 212 第二軟體暫存單元 214 第三軟體暫存單元 216 • S四軟體暫存單元218 解碼單元 240 • 第一反向電路 241 • 第二反向電路 243 致能控制電路 245 資料線 D0，D1,D2,D3 控制及運算電路 30 監視計時器 40 16The enable signal is calculated to generate an example. Please refer to the second figure, which is a block diagram of the hardware control unit of the present invention. The hardware control unit 1 includes a sensation unit 110, at least one buffer circuit 13 〇 and a less than two binary memory register 丨 5 〇. Since the hardware-enabled value required for executing the hardware is pre-stored in the memory unit 110 in the hardware control unit 1 , the hardware temporary storage unit in the hardware control unit 10 is based on a A clock signal is used to retrieve the hardware enable value in the memory unit 110, wherein the first clock signal is the load clock of the hardware temporary storage unit 153, and the microprocessor is powered on each time. Reset - times, the micro-processing will generate this brother's one-time signal. On the other hand, in the process of extracting the hardware enable value to the hardware temporary storage unit 15〇, the hardware enable value is first transmitted to the buffer circuit 13〇 to perform buffer amplification operation to increase the hardware. The driving ability of the enabling value. Therefore, the memory unit 110 can be a one-time programmable cell (OTP cell), that is, a non-volatile memory erasable stylized read-only memory. (Erasable Programmed Read On)y Memory, EPROM). The hardware temporary storage unit 150 can be a logic circuit composed of a flip-flop. 8 yuan;: It is the software control unit of the content of the invention 1 piece W0. The software control unit 2G includes a - software temporary storage list (4) (four) 212, a second software temporary storage unit, - a ^ ^ temporary storage early 216, a fourth software temporary storage unit 218, and a code decoding unit (decoding unit) 240. Soft 2: Root:: The second clock signal is composed of a per-storage unit (the -^泉(五) Marriage 软Softener enablement value' to form a multi-byte group. This pulse reduction designer is designing this pure The working clock generated by the body (4) _. The multi-byte group is composed of a plurality of zeros or 壹. Therefore, the first software temporary storage unit 212, the second software temporary storage unit force 214, and the third software temporary storage sheet S The fourth software temporary storage unit (10) can be a flip-flop. ', then, the first-reverse circuit in the decoding unit 240 (_C-241 will be extracted by the first software temporary storage unit 212) The energy value is reversed, and the second inversion circuit 243 reverses the software enablement value fetched by the third software temporary storage unit 216 and cooperates with the two software temporary storage units (the second software temporary storage unit 214 and the The software enable value obtained by the four-software temporary storage unit 218) is provided to enable the control circuit 245 to generate a vehicle body enable signal. Therefore, the first reverse circuit 241 and the second reverse circuit 243 is the reverse gate (NOT), and the enable control circuit 245 can be the reverse gate (NAND). Please refer to the fourth. </ RTI> is shown in the first embodiment of the present invention and together with reference to the first, will be preset to perform the operation of the hard watchdog timer enabling circuit, the second and third diagrams. When designing the microprocessor The body causes the required hardware to cause this value' and is burned in the microprocessor 132.7272 unit 110 in the microprocessor. Hundreds of first, when the microprocessor starts the electric circuit, the enabling circuit will start hard first: D step S41G, the monitor meter enabling circuit is based on the first clock; ^ 'step _. The monitoring timing is controlled by the memory hardware control unit in the microprocessor to the corresponding hardware temporary storage unit. The hard hardware-induced hard-acting value of the yuan will be slowed down, f is said, the memory unit 110 yuan to generate hardware-assisted special delivery to the hardware temporary storage list designer in the design of these hardware temporary storage: f , F--clock signal is implemented for (10), hardware-enabled 『^ 奢 extra'! 〇 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Step system: 4 system early 2兀 by the data line D0~D3 in the microprocessor, the softness of the fixed bit The enable value is to the soft moon 2曰 unit corresponding to the data line d〇~d3. That is to say, the body enable value on the data line D〇 is transmitted to the first-software temporary storage unit 212' data line m The upper software enable value will be transmitted to the second software temporary storage unit 214, the software enable value on the data line D2 will be transmitted to the second software temporary storage unit 216, and the software enable value on the data line D3 will be transmitted to The fourth software temporary storage unit 218. The second clock signal is a working clock generated by the designer when designing the software temporary storage unit. The first reverse circuit 241 in the decoding unit 240 will be the first software. The software enable value in the temporary storage unit 212 is reversed, and the second reverse circuit 243 also reverses the software enable value in the third software temporary storage unit 216. Finally, the two reversed soft body enable values and the other two unreversed soft body enable values are 1327272 ^Special (four) circuit 245 towel operation, the raw software enable signal to ^ ^ ^ ^ these four bits The soft body is all arbitrarily valued, that is, the lower body control unit 2 〇 ' is a high potential _ (1) (1)). The multi-bytes of the data line D〇~D3 are provided by the multi-bytes of the backward reverse circuit 241 and the second reverse circuit 243. When the software control unit 20 presets the solution, it will be soft. 1111) When the 'software enable signal will be one, so the Japanese will not cry, the work will be disabled 2' and the enable control circuit 245 will make the monitor, 40 £ 〇# D〇^3 for u_ After passing through the reverse of the first-reverse circuit 24i and the second reverse path 243, the multi-element i20 forming (im) is pre-set = the enable group is set to _), the body enable signal = 'make the software The control unit 2G is disabled and the enable control circuit 曰245 does not - cause the watchdog timer 4 to perform a system reset. Therefore, the number of reverse circuits in the software control unit 20 is adjusted by the enabler group. And release + ': the thinker can control circuit 245 to make adjustments. A multitude of this: and is the 'side of the octet and the desired one, select a part of the data line from the source of the soft-energy source in the microprocessor, for the financial time H light circuit becomes Lai Wei and hardware and soft (4) shirts (4) (4) (4) Controls in the enabling circuit when the signal is enabled = Out = The axis number is transmitted to the monitor and the hardware is enabled and the software is switched to the second: 30 signals, such as Step S440. To enable the control of the bimonthly b control signal can be high potential enable or 1327272 low potential enable. Among them, the soft body enabler and the hard body enable can be high potential enable or low enable, while the high potential enabler uses the bit state for one-time energy, and the low potential enable energy uses the bit element. Enable when the state is zero. The enable control signal can be determined based on the control and operation circuit, the hardware enable signal and the software enable signal to determine the high potential enable or low potential enable. Finally, the watchdog timer enable circuit determines if the microprocessor has an abnormality, as in step S450. When the microprocessor has not experienced any abnormality, the watchdog timer enable circuit further clears the count contents in the watchdog timer, i.e., performs a warm reset action, as by step S460. When the microprocessor has an abnormal state, the watchdog timer enable circuit causes the watchdog timer to generate a reset signal to reset the microprocessor, as by step S470. Please refer to the fifth figure, which is a flowchart of the operation of the monitoring timer enabling circuit according to the second embodiment of the present invention, and refers to the first, second and third figures. First, when the microprocessor starts the power supply, as in step S510, the monitoring timer enabling circuit first starts the software enabling, as in step S520. The watchdog timer enabling circuit controls the software control unit 20 to extract the software enable value of one bit from the data lines DO to D3 in the microprocessor to the data line D according to a second clock signal. 0 to D 3 corresponds to the software temporary storage unit. The first reverse circuit 241 in the decoding unit 240 reverses the software enablement value in the first software temporary storage unit 212. The second reverse circuit 243 also enables the software in the third software temporary storage unit 216. The value is reversed. Finally, the two inverted software enable values and the other two unreversed software enable values are passed to the enable control circuit 245 for operation to generate a software enable signal. Next, the watchdog timer enable circuit initiates hardware enablement, as in step 12 1327272 S530. The monitoring timer enables the root of the circuit. According to the clock signal, the control unit is controlled by the memory unit u wiper in the microprocessor. (4) The hardware enable value to the corresponding hardware temporary storage unit. That is, the hardware enable value in the memory unit U〇 is transmitted to the hardware temporary storage unit 15 via the buffer circuit 30 to generate a hardware enable signal. Bai Buzhen = view, handle, so that the circuit has completed the software enable and hardware enable § and then, respectively, the hardware control unit 1 〇 qing control unit 2. The output of the body is enabled to control and operate the circuit in the circuit. Control and management circuit deduction ^ The hard-sewn signal recording body enables the signal: the signal, as in step S54. The seat is the most, the monitor (4) enables the circuit to ride on the microprocessor. 2:?: When the microprocessor does not have any abnormality, the monitor 2 will further count the watch timer. In addition, the action of performing a warm reset, such as step S56 〇 / abnormal shape energy, occurs in the gentleman + Tian Yi birthday t state ^ now s 10 days of the sacred to the road will make the monitoring time volume A duplicate is generated to reset the microprocessor, as in step S570. According to the third embodiment of the invention, it is a flow chart of the operation of the double-month b-way, and together with reference to the first, second, second, and two hundred firsts, when the microprocessor starts the power supply, such as Step S61.0, monitoring the enabling of the correcting and simultaneously starting the hardware enabling and tilting energy. If the step monitoring meter (4) enables the circuit to start the software, the monitoring timer controls the software control unit according to the second signal. 20 body = letter ^ data line D 〇 ~ D3, respectively, take 1 bit of soft " ^ to the gracious line 1 ^ ~ D3 corresponding software temporary storage unit. Decoding single 13 yuan 240 The first reverse power 241 reverses the first software temporary storage unit body energy value, and the second reverse circuit 243 also reverses the soft body energy value of the third software body 22% 216. Finally, this The two reversed energy values and the other two inverted and unreversed software enable values are transmitted to the control, and the circuit 245 performs an operation to generate the software enable signal. The monitoring material (4) can enable the circuit to start the hardware enablement. The watchdog timer circuit controls the memory unit 11G of the hardware control unit 10 to operate 1 according to the first clock signal ' The bit hardware of the bit == the hardware temporary storage unit. That is to say, the memory unit no h causes the I value to be transmitted to the hardware temporary storage unit 150 via the buffer circuit 13Q to generate the hardware enable signal. Material 11 enables the electric material to complete the soft body and the hardware body 2: ^ The hardware enable signal output by the hardware 2 output from the Γη body control unit 10 is transmitted to the watchdog timer to make the operation 1 3Q. The control and operation circuit 3〇 and the software enable signal are operated to generate the enable control 5 hole number 'such as the step S630. _£ a The most discriminating circuit 3 will determine whether the microprocessor is When the timer enable circuit is abnormal, the monitoring is performed, that is, the operation of resetting is performed; the count content in the object is cleared to the abnormal state =: r. When the microprocessor generates Ding "° The circuit will cause the watchdog timer to generate a reset call to reset the microprocessor, such as the step s_. Pay attention to ▲ 12 two = the & the advantage is that the software is enabled to make the monitoring time = ^ road is not easy to receive The influence of environmental factors, resulting in a monitor 13227272, another advantage provided by the present invention is The hardware enabler value is pre-programmed in the memory unit in the microprocessor. A further advantage provided by the present invention is that the multi-bit group for generating the software-enabled signal is controlled by the microprocessor. A plurality of data lines are provided and are any values consisting of zero or 壹. Another advantage provided by the present invention is that the software control unit is composed of a plurality of software temporary storage units and one by at least one reverse circuit and A decoding unit composed of an enabling control circuit is formed, and the number of the software temporary storage units is adjusted according to the needs of the user. Another advantage provided by the present invention is that the hardware enabled signal and the soft body enable signal 5 Tiger and enable control signals can be enabled for south potential or low potential, and can be adjusted according to user needs. The drawings are provided for reference and description only, and are not intended to be limiting; However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, equivalent structural changes that are made by using the specification and the contents of the present invention are equally included in the present invention. Within the scope, it is combined with Chen Ming. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a block diagram of a watchdog timer enabling circuit of the present invention; the second figure is a block diagram of a hardware control unit in the watchdog timer enabling circuit of the present invention; The third figure is a block diagram of a software control unit in the watchdog timer enabling circuit of the present invention; 15 1327272 The fourth figure is a watchdog timer enabling circuit performing system reset according to the first embodiment of the present invention. The fifth diagram is a flowchart of performing a system reset of the watchdog timer enabling circuit of the second embodiment of the present invention; and the sixth figure is a watchdog timer of the third embodiment of the present invention. A flowchart of enabling the circuit to perform a system reset. [Main component symbol description] • Hardware control unit 10 Memory unit 110 Buffer circuit Π 0 Hardware temporary storage unit 150 • Software control unit 20 First software temporary storage unit 212 Second software temporary storage unit 214 Third software temporary storage unit 216 • S quad software temporary storage unit 218 decoding unit 240 • first reverse circuit 241 • second reverse circuit 243 enable control circuit 245 data line D0, D1, D2, D3 control and operation circuit 30 watchdog timer 40 16