1318005 九、發明說明： 【發明所屬之技術領域】 、本發明係關於一種金氧半導體 (metal-oxide-semiconductor; MOS)電晶體的製作方法，尤 指一種具有應變石夕（strained silicon)之金氧半導體電晶體的 製作方法。本發明的特徵在於先去除金氧半導體電晶體之 •側壁子，再於金氧半導體電晶體上形成一應力覆蓋層（cap 馨 stressed layer)來產生結構上應變，使金氧半導體電晶體可 以具有較高的驅動電流(drive current)，藉此提升半導體電 晶體的操作效能。 .【先前技術】 隨著半導體製造技術愈來愈精密，積體電路也發生重大 的變革’使得電腦的運算性能和存儲容量突飛猛進，並帶 •動周邊産業迅速發展。而半導體產業也如同摩爾定律所預 測的，以每18個月在積體電路上增加一倍電晶體數目的速 度發展著，同時半導體製程也已經從1999年的0.18微米、 2001年的〇· 13微米、2003年的9〇奈米，進入到2005年 65奈米。而隨著半導體製程進入深次微米時代，在半導體 製程t如何提升金氧半導體電晶體的驅動電流已逐漸成為 一熱門課題。 1318005 目前揭:升金氧半導體電晶體之驅動電流的方法有很多 - 種’例如美國專利公開號第2005/0059228號專利即教導一 .種提升金氧半導體電晶體的驅動電流之方法，其係利用一 氣化物氧化物混合覆蓋層之退火(anneal)製程來改變基底 的摻質分佈’以提升通道中的電子遷移率（electr〇n • mobllity)。上述方法請參考第i圖至第6圖，第1圖至第6 •圖為習知提升金氧半導體電晶體的驅動電流之方法示意 _ 圖。如第1圖所示，首先提供一半導體裝置300。於基底 3〇9中佈植n型摻質310,使其達到一預定之深度與濃度而 形成一主動區域302與一主動區域303，並於基底309中 •佈植P型摻質而形成二硼摻質區315。主動區域302與主 動區域303之間則定義出一 P型之通道區域301。半導體 裝置3〇〇包含有一閘極氧化層（gate oxide layer)3〇4、一多 晶矽氧化物(poly 〇xide)305、一多晶矽閘極(polysilicon • gate)306、以及一偏移侧壁予（0ffset Spacer)3n。 如第2圖所示，接著形成側壁子412、側壁子413、側 ‘壁子414’毗鄰於閘極氧化層304與多晶矽閘極306周圍。 然後以此多晶矽閘極306及側壁子412、側壁子413、側壁 子414做為遮罩進行離子佈植(j〇n jmpiantati〇n)，把坤或填 4 N型摻質植入於基底309中，以形成源極區域407與汲 極區域408。 7 1318005 如第3圖所示’接著進行一化學氣相沈積製程(chemical vapor deposition ; CVD) ’ 以形成一混合覆蓋層（composite cap)516。混合覆蓋層516包含有一襯墊層（未圖示）與一氮 化物層位於襯墊層之上，其中襯墊層通常由氧化物或氮氧 化物所構成。襯墊層之厚度約介於50至1〇〇埃(angstrom)， •而氮化物層之厚度約大於等於300埃。尤其注意的是，混 合覆蓋層516可以被選擇性地移除，而暴露出p型金氧半 導體電晶體。 如第4圖所示，然後進行一快速升溫退火(rapid让ennal annealin琴；RTA)製程’用以活化（active)丨原極區域與汲 極區域408内的摻質，並同時修補在離子佈植製程中受損 之基底3.09表面的晶格結構。混合覆蓋層5〗6之氮化物層 包含有多量之氫，部分氫617會於快速升溫退火製程中進 入氧化物或襯墊層中，使得氧化物之氫漢度上升，進而導 致通道區域301中部分之p型摻質輕易進入侧壁子412或 疋混合覆蓋層516之襯墊層中。由於通道區域中鄰近 閘極部分之P型摻質的數量減少，因此提升了 N型金氧半 導體電晶體的通道區域3〇1之電子遷移率。 如第5圖所示，隨後去除混合覆蓋層516。如第6圖所 示，接著進行一自對準金屬矽化物（salicide)製程，於基底 8 1318005 309表面形成一金屬層（未不於圖中），例如一鍊金屬層，使 金屬層與主動區域302、主動區域303、多晶矽閘極306等 - 矽化物相接觸的部分發生反應，形成金屬矽化物818，最 . 後再去除未反應成金屬矽化物818之金屬層。 瓤 習知技術利用通道區域301之p型摻質濃度下降來提升 通道區域301之電子遷移率，然而此方法受限於偏移側壁 子311、側壁子412、側壁子413、侧壁子414與混合覆蓋 鲁 層516之結構’僅能改變通道區域301與多晶矽閘極306 交界處的摻質濃度，因此習知技術之提升效果相當有限β 另一方面，習知技術雖可提升Ν型金氧·半導體電晶雔 的通道區域301之電子遷移率，然而，由於習知技術係利 用混合覆蓋層516而使基底309之Ρ型摻質的濃度下降.， 因此混合覆蓋層516也會減少ρ型金氧半導體電晶體之ρ 鲁 型輕摻雜汲極(p‘type lightly-doped-drain，PLDD)的 Ρ 型摻 質遭度’進而破壞所製作之ρ型金氧半導體電晶體的運 、作。有鑑於此，習知技術的混合覆蓋層516完全不適用於 P型金氧半導體電晶體。因此如何有效提升通道區域之電 子遷移率仍為該領域一重要議題。 【發明内容】 9 1318005 因此，本發明之主要目的在提供一種製作金氧半導體 電晶體之方法，其先去除金氧半導體電晶體之側壁子，再 於金氧半導體電晶體表面形成一應力覆蓋層來改變通道區 域的應力，使金氧半導體電晶體具有較佳的操作效能。 根據本發明之較佳實施例，本發明提供一種製作金氧 半導體電晶體的方法。首先，提供一半導體基底，半導體 基底上包含有一閘極結構。然後於閘極結構相對二側之半 I 導體基底中形成一淺接面源極延伸以及一淺接面汲極延 伸，再於閘極結構之相對二側壁上形成一襯墊層與一側壁 子，利用閘極結構以及側壁子作為佈植遮罩，對半導體基 底進行一離子佈植製程，藉此於閘極結構相對二側之半導 體基底中形成一源極區域與一汲極區域。去除側壁子之 後，於半導體基底上形成一應力覆蓋層，覆蓋於閘極結構、 襯墊層、源極區域與汲極區域上。接著，進行一活化製程，1318005 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a method for fabricating a metal-oxide-semiconductor (MOS) transistor, and more particularly to a gold having a strained silicon. A method of fabricating an oxygen semiconductor transistor. The invention is characterized in that the sidewall of the MOS transistor is removed first, and then a stress-stressed layer is formed on the MOS transistor to generate structural strain, so that the MOS transistor can have A higher drive current, thereby improving the operational efficiency of the semiconductor transistor. [Prior Art] With the increasing precision of semiconductor manufacturing technology, major changes have taken place in the integrated circuit, which has made the computer's computing performance and storage capacity soar, and the surrounding industries have developed rapidly. The semiconductor industry, as predicted by Moore's Law, is growing at a rate that doubles the number of transistors on integrated circuits every 18 months, and the semiconductor process has also been 0.18 micrometers in 1999 and 〇13 in 2001. Micron, 9 〇 nanometer in 2003, entered 65 nm in 2005. With the semiconductor process entering the deep submicron era, how to improve the driving current of the MOS transistor in the semiconductor process has gradually become a hot topic. 1318005 At present, there are many methods for driving the current of a MOS transistor. For example, the method of raising the driving current of a MOS transistor is disclosed in the patent of US Pat. Pub. No. 2005/0059228. An anneal process of a vaporized oxide mixed blanket is used to alter the dopant distribution of the substrate to enhance electron mobility (electr〇n • mobllity) in the channel. For the above method, please refer to the figures i to 6, and the first to sixth figures are schematic diagrams of the conventional method for improving the driving current of the MOS transistor. As shown in FIG. 1, a semiconductor device 300 is first provided. The n-type dopant 310 is implanted in the substrate 3〇9 to reach a predetermined depth and concentration to form an active region 302 and an active region 303, and in the substrate 309, a P-type dopant is implanted to form two Boron dopant region 315. A P-type channel region 301 is defined between the active region 302 and the active region 303. The semiconductor device 3 includes a gate oxide layer 3〇4, a poly germanium oxide (poly 〇xide) 305, a polysilicon gate 306, and an offset sidewall ( 0ffset Spacer) 3n. As shown in Fig. 2, sidewall spacers 412, sidewall spacers 413, and side "walls 414' are then formed adjacent to the gate oxide layer 304 and the periphery of the polysilicon gate 306. Then, the polysilicon gate 306 and the sidewall spacer 412, the sidewall spacer 413, and the sidewall spacer 414 are used as a mask for ion implantation (j〇n jmpiantati〇n), and the Kun or 4N-type dopant is implanted on the substrate 309. The source region 407 and the drain region 408 are formed. 7 1318005 As shown in FIG. 3, 'a chemical vapor deposition (CVD)' is then performed to form a composite cap 516. The hybrid cover layer 516 includes a liner layer (not shown) and a nitride layer overlying the liner layer, wherein the liner layer is typically comprised of an oxide or oxynitride. The thickness of the liner layer is about 50 to 1 angstrom, and the thickness of the nitride layer is about 300 angstroms or more. It is particularly noted that the hybrid cap layer 516 can be selectively removed to expose the p-type MOS transistor. As shown in Fig. 4, a rapid thermal annealing (rapid for ennal annealin piano; RTA) process is then used to activate the dopants in the primary and drain regions 408 and simultaneously repair the ion cloth. The lattice structure of the damaged surface of the substrate 3.09 during the implantation process. The nitride layer of the mixed cap layer 5-6 contains a large amount of hydrogen, and a part of the hydrogen 617 enters the oxide or the liner layer in the rapid temperature annealing process, so that the hydrogen degree of the oxide rises, thereby causing the channel region 301 to be A portion of the p-type dopant readily enters the liner layer of sidewall spacer 412 or tantalum hybrid overlay layer 516. Since the number of P-type dopants adjacent to the gate portion in the channel region is reduced, the electron mobility of the channel region 3〇1 of the N-type MOS transistor is improved. As shown in Figure 5, the hybrid cover layer 516 is subsequently removed. As shown in Fig. 6, a self-aligned metal salicide process is then performed to form a metal layer (not shown) on the surface of the substrate 8 1318005 309, such as a chain metal layer, to make the metal layer active. The region 302, the active region 303, the polysilicon gate 306, and the like - the portion in contact with the germanide phase reacts to form a metal germanide 818, and the metal layer which is not reacted into the metal germanide 818 is removed. The conventional technique utilizes a decrease in the p-type dopant concentration of the channel region 301 to increase the electron mobility of the channel region 301. However, this method is limited to the offset sidewall sub-311, the sidewall spacer 412, the sidewall sub-413, and the sidewall sub-414. The structure of the mixed cover layer 516 can only change the dopant concentration at the junction of the channel region 301 and the polysilicon gate 306, so the lifting effect of the prior art is quite limited. On the other hand, the conventional technique can improve the gold oxide type. The electron mobility of the channel region 301 of the semiconductor transistor, however, since the prior art utilizes the mixed cap layer 516 to reduce the concentration of the germanium dopant of the substrate 309, the hybrid cap layer 516 also reduces the p-type. The Ρ-type dopant of the p-type lightly-doped-drain (PLDD) of the MOS transistor is used to destroy the fabrication of the p-type MOS transistor. . In view of this, the conventional hybrid cover layer 516 is completely unsuitable for P-type MOS transistors. Therefore, how to effectively improve the electron mobility of the channel region is still an important issue in this field. SUMMARY OF THE INVENTION 9 1318005 Accordingly, a primary object of the present invention is to provide a method of fabricating a MOS transistor, which first removes a sidewall of a MOS transistor and forms a stress coating on the surface of the MOS transistor. To change the stress in the channel region, the MOS transistor has better operational efficiency. In accordance with a preferred embodiment of the present invention, the present invention provides a method of fabricating a MOS transistor. First, a semiconductor substrate is provided having a gate structure on the semiconductor substrate. Then forming a shallow junction source extension and a shallow junction drain extension in the half-I conductor substrate on the opposite sides of the gate structure, and forming a liner layer and a sidewall on the opposite sidewalls of the gate structure. An ion implantation process is performed on the semiconductor substrate by using the gate structure and the sidewalls as the implantation mask, thereby forming a source region and a drain region in the semiconductor substrate opposite to the gate structure. After removing the sidewalls, a stress coating is formed over the semiconductor substrate overlying the gate structure, the liner layer, the source region and the drain region. Then, an activation process is performed,
再對應力覆蓋層進行一餘刻製程，使應力覆蓋層成為一自 I 對準金屬^夕化物阻撞層（salicide block，SAB)。然後，進行 一自對準金屬矽化物製程，以於未覆蓋有應力覆蓋層之閘 極結構、源極區域與汲極區域上形成一金屬矽化物層。 根據本發明之另一較佳實施例，本發明另提供一種製 作金氧半導體電晶體的方法。首先，提供一半導體基底， 半導體基底上定義有一第一主動區域、一第二主動區域與 1318005 一第三主動區域，第一、第二與第三主動區域上分別包含 有至少一閘極結構，閘極結構相對二側壁上包含有一襯墊 .層，各閘極結構相對二側之半導體基底中則具有一源極區 域與一汲極區域。之後，於第一、第二與第三主動區域中 之半導體基底上形成一應力覆蓋層，覆蓋於閘極結構、襯 墊層、源極區域與汲極區域。接著，對應力覆蓋層進行一 第一蝕刻製程，以暴露出第二主動區域中之閘極結構、源 極區域與汲極區域，爾後對源極區域、汲極區域與應力覆 Φ 蓋層進行一活化製程，再對應力覆蓋層進行一第二蝕刻製 程，以暴露出第一主動區域中之閘極結構、源極區域與汲 極區域。然後，進行一自對準金屬矽化物製程，以於第一 與第二主動區域中未覆蓋有應力覆蓋層之閘極結構、源極 區域與汲極區域上形成一金屬矽化物層。 - 由於本發明係先去除金氧半導體電晶體之側壁子，再 於金氧半導體電晶體上形成一應力覆蓋層來產生結構上應 胃變，因此可使金氧半導體電晶體可以具有較高的驅動電 .流，藉此提升金氧半導體電晶體的操作效能。 為了使貴審查委員能更進一步了解本發明之特徵及 技術内容，請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與輔助說明用，並非用來對本發明加 λ 以限制者。 1318005 【實施方式】 請參照第7圖至第13圖，其繪示的是本發明之第一較 佳實施例製作金氧半導體電晶體的方法的剖面示意圖，其 中相同的元件或部位仍沿用相同的符號來表示。需注意的 是圖式僅以說明為目的，並未依照原尺寸作圖。此外，在 第7圖至第13圖中對於與本發财關之部分的微影及飯刻 製程由於為該項技藝者以及通常知識者所熟知的，因此 未明示於圖中。 " 本發明係關於一種製作積體電路中的金氧半導體電晶 體的方法，可適用於N型金氧半導體電晶體與p型金氧半 導體電晶體，為了進行詳細說明:’第7圖至第13圖中特別 以位於不同區域之金氧半導體電晶體製程作為說明。如第 7圖所示，首先提供一半導體.基底1〇，例如一矽基底或者 是石夕覆絕緣（silicon-on-insulator ; SOI)基底。半導體基底1〇 上定義有一第一主動區域1、一第二主動區域2與一第三 主動區域3’例如第一主動區域1、第二主動區域2與第二 主動£域3可分別為一核心電路(core circuit)區域、一輸入 或輸出（input/output ; I/O)元件區域與一靜電放電 (electrostatic discharge ; ESD)保護元件區域。而本發明於 第一主動區域1、一第二主動區域2與一第三主動區域3 12 1318005 内所製作之金氧半導體電晶體110、金氧半導體電晶體i2〇 與金氧半導體電晶體130可以為N型金氧半導體電晶體或 - P型金氧半導體電晶體。 首先分別在第一主動區域1、第二主動區域2與第三 主動區域3之半導體基底10上形成一閘極介電層μ以及 一閘極12，構成一閘極結構，其中閘極12通常包含有掺 雜多晶矽(doped polysilicon)等之導電材料，閘極介電層14 •則可為二氧化矽（silicon dioxide ; Si〇2)或氮化矽（silic〇n nitride)等之絕緣材料。接著，在各閘極12二側之半導體基 底10.中分別形成一淺接面源極延伸17以及一淺接面汲極 延伸19 ’而淺接面源極延伸17以及淺接面及極延伸1 $之 間即為金氧半導體電晶體110、；12〇、130之通道區域22。 之後’進行化學氣相沉積製程，以形成二遮蔽層（未 示於圖中）覆蓋於各閘極12和半導體基底1〇上方。然後， 馨 對二遮蔽層進行一非等向性#刻製程(anisotropic etch)，以 使二雖蔽層形成一襯墊層30與一側壁子（spacer)32，襯塾 層30位於各閘極丨2的相對二側壁上，而側壁子32則位於 各襯墊層30上。其中，襯墊層30可以為一偏移側壁子， 材料可包含有氧化矽等，且通常為L型，而側壁子32則可 包含有氮矽化合物或氧矽化合物。 13 1318005 如第8圖所示’於形成側壁子32之後，接著進行一離 子佈植製程，將摻質植入半導體基底10中，藉此於第一主 動區域1、第二主動區域2與第三主動區域3内各形成一 源極區域18以及一汲極區域20。如習知該項技藝者以及 通常知識者所熟知，針對N型金氧半導體電晶體，摻質可 以為砷、銻或磷等N型摻質物種；針對p型金氧半導體電 晶體’摻質則可為硼、鋁等p型換質物種。 _ 此外，在完成源極區域18與汲極區域2〇的摻雜後， 半導體基底10可以選擇性地進行一活化製程，例如一快速 升溫退火或一退火製程，用以活化·淺接面源極延伸17、淺 接面汲極延伸19、源極區域18以及汲極區域2〇内的摻質， 並同時修補半導體基底1〇表面的晶格結構。由於後續製程 中仍會包含有其他的高溫製程，因此此處亦可先不進行活 化製程，而改於應力覆蓋層形成之後再進行此活化製程， 以活化源極區域18以及汲極區域2〇内的摻雜質。Then, the stress coating layer is subjected to a process of etching, so that the stress coating layer becomes a self-alignment metal salicide block (SAB). Then, a self-aligned metal telluride process is performed to form a metal germanide layer on the gate structure, the source region and the drain region which are not covered with the stress cladding layer. According to another preferred embodiment of the present invention, the present invention further provides a method of fabricating a gold oxide semiconductor transistor. First, a semiconductor substrate is provided. The semiconductor substrate defines a first active region, a second active region, and a 1318005-third active region. The first, second, and third active regions respectively include at least one gate structure. The gate structure includes a pad layer on opposite sidewalls, and each of the gate structures has a source region and a drain region in opposite semiconductor substrates. Thereafter, a stress coating layer is formed on the semiconductor substrate in the first, second, and third active regions to cover the gate structure, the pad layer, the source region, and the drain region. Then, a first etching process is performed on the stress covering layer to expose the gate structure, the source region and the drain region in the second active region, and then the source region, the drain region and the stress-covered Φ cap layer are performed. An activation process is followed by a second etching process on the stress cap layer to expose the gate structure, the source region, and the drain region in the first active region. Then, a self-aligned metal telluride process is performed to form a metal germanide layer on the gate structure, the source region and the drain region of the first and second active regions not covered with the stress cladding layer. - Since the present invention first removes the sidewall of the MOS transistor and then forms a stress coating on the MOS transistor to cause structurally gastric transformation, the MOS transistor can have a higher The electric current is driven to enhance the operational efficiency of the MOS transistor. In order to provide a more detailed understanding of the features and technical aspects of the present invention, the following detailed description of the invention and the accompanying drawings. However, the drawings are for reference and auxiliary explanation only, and are not intended to limit the invention to λ. 1318005 Embodiments Referring to FIGS. 7 to 13 , there are shown schematic cross-sectional views showing a method of fabricating a MOS transistor according to a first preferred embodiment of the present invention, in which the same components or parts are still used in the same manner. The symbol to represent. It should be noted that the drawings are for illustrative purposes only and are not mapped to the original dimensions. Further, the lithography and meal processes for the portion of the present invention in Figures 7 through 13 are well known to those skilled in the art and those of ordinary skill, and are therefore not explicitly shown. " The present invention relates to a method for fabricating a MOS transistor in an integrated circuit, which is applicable to an N-type MOS transistor and a p-type MOS transistor, for the sake of detailed description: 'Figure 7 In Fig. 13, the oxynitride transistor process in different regions is specifically described as an illustration. As shown in Fig. 7, first, a semiconductor substrate, such as a germanium substrate or a silicon-on-insulator (SOI) substrate, is provided. A semiconductor active substrate 1 defines a first active region 1, a second active region 2, and a third active region 3'. For example, the first active region 1, the second active region 2, and the second active region 3 may each be a A core circuit region, an input/output (I/O) component region, and an electrostatic discharge (ESD) protection device region. The MOS transistor 110, the MOS transistor i2〇, and the MOS transistor 130 fabricated in the first active region 1, the second active region 2, and the third active region 3 12 1318005. It may be an N-type MOS transistor or a -P-type MOS transistor. First, a gate dielectric layer μ and a gate 12 are formed on the semiconductor substrate 10 of the first active region 1, the second active region 2 and the third active region 3, respectively, to form a gate structure, wherein the gate 12 is usually The conductive material comprising doped polysilicon or the like, and the gate dielectric layer 14 can be an insulating material such as silicon dioxide (Si2) or silicium nitride. Next, a shallow junction source extension 17 and a shallow junction drain extension 19' and a shallow junction source extension 17 and a shallow junction and a pole extension are respectively formed in the semiconductor substrate 10. on both sides of each gate 12. Between 1 $ is the MOS transistor 110, the channel region 22 of 12 〇, 130. Thereafter, a chemical vapor deposition process is performed to form a second shielding layer (not shown) overlying each of the gates 12 and the semiconductor substrate 1A. Then, an anisotropic etch is performed on the two masking layers, so that the second layer forms a liner layer 30 and a spacer 32, and the lining layer 30 is located at each gate. The opposite side walls of the crucible 2 are located on the respective liner layers 30. The liner layer 30 may be an offset sidewall, the material may comprise yttrium oxide or the like, and is generally L-shaped, and the sidewall spacer 32 may comprise a nitrogen ruthenium compound or an oxonium compound. 13 1318005 As shown in FIG. 8 'after forming the sidewall spacers 32, an ion implantation process is then performed to implant dopants into the semiconductor substrate 10, thereby utilizing the first active region 1, the second active region 2, and the first A source region 18 and a drain region 20 are formed in each of the three active regions 3. As is well known to those skilled in the art and those of ordinary skill in the art, for N-type MOS transistors, the dopant may be an N-type dopant species such as arsenic, antimony or phosphorus; for a p-type MOS transistor's dopant It can be a p-type metamorphic species such as boron or aluminum. In addition, after doping of the source region 18 and the drain region 2〇, the semiconductor substrate 10 can be selectively subjected to an activation process, such as a rapid temperature annealing or an annealing process for activating the shallow junction source. The pole extension 17, the shallow junction drain extension 19, the source region 18, and the dopant in the drain region 2〇, and simultaneously repair the lattice structure of the surface of the semiconductor substrate 1 . Since other high-temperature processes are still included in the subsequent process, the activation process may not be performed here, and the activation process may be performed after the stress coating layer is formed to activate the source region 18 and the drain region 2〇. Doping within.
I 如第9圖所示，隨後去除側壁子32，留下閘極12侧 壁上的襯墊層3G。根據本發明之較佳實補，去除側壁子 32之後，則在閘極12側壁上留下約略呈[型的襯塾層％。 然而’習知該項技藝者以及通常知識者應理解襯墊層％不 -定呈L型，而其亦可以進行—較溫和㈣刻製程，略微 蝕刻襯墊層30,以縮減其厚度。而在其它實施例中，概塾 1318005 層30甚至可被完全去除。 h第1G®所不’接著半導體基底iQ上形成—應力覆蓋 層46 ’並覆蓋於襯墊層3〇、問極12、源極區域18與沒極 區域2〇表面。於此較佳實施例中，應力覆蓋層46為-單 I結構’由氧切或氮切所組成，其厚度可介於1〇埃至 3000埃之間。以-魏切之應力覆蓋層46為例，其形 成方式可利用-高溫氧化製程於半導體基底1〇表面全面 髒七成南/皿氧化物（high temperature oxide，HTO)作為應力 覆蓋層46，其亦可利用一次常壓化學氣相沉積 (sub atmospheric pressure chemical vapor deposition » SACVD)製程於半導體基底1〇表面全面沉積一層氧化矽作 為應力覆蓋層46。 針對P型金.氧半導體電晶體，習知該項技藝者以及通常 知識者應理解亦可以於形成應力覆蓋層46..後，再選擇性地 ♦進行-道半導體製程來改變應力覆蓋層 46的應力狀態，減 少應力覆蓋層46的伸張應力，或增加壓縮應力。例如進行 一離子佈植製程’利用鍺離子佈植來改變應力覆蓋層46的 應力狀態。或者’於形成應力覆蓋層46後，再選擇性地進 行一微影暨餘刻製程，以去除p型金氧半導體電晶體上方 的應力覆蓋層46 °此種可於一覆蓋層中結合壓縮應力與伸 ’ 張應力之技術稱之為選擇性應力系統（selective strain 1318005 scheme，SSS) 如第@所71~於本較佳實施例中，由於第二主動區 域2内的金氧半導體電晶體⑽無需進行應力改變，因此 可利用微影暨㈣製程去除位於第二主動區域2内的應力 覆蓋層46 /呆留位於第一主動區域上及第三主動區域3内 的應力覆蓋層46 ’以暴露出第二主動區域2中之閘極12、 源極區域18與汲極區域2〇。 然後對應力t蓋層46 1%行一現場(in_situ)或非現場(_ in situ)的活化製程:，例如進行一紫外線硬化(UVcuring)t 程、-退火製程、-高溫峰值退火(the_l spike_叫製 程或-電子束(e-beam)處理。藉著活化製程把應力記憶入金 氧半導體電晶體Π0與金氧半導體電晶體13〇之中，拉 通道區域22之半導體基底10的晶格排列，進而提升位於 第-主動區域！及第三主動區域3之通道區域U的课 移率以及金氧半導體電晶體U〇與金氧半導體雷曰 之驅動電流。 、曰曰體130 實驗結果顯示’當本發明之應力覆蓋層46 _ 單層結構時，由次常壓化學氣相沉積製程所形為氧化石夕之 蓋層46約可增加N型金氧半導體電晶體 成的應力覆 分比（Ion gain percentage)達 5.3% 左右，而僅 ^ 百 P型金氧半 1318005 … 導體電晶體之開啟電流增益百分比減少了 0.7% ;由高溫氧 化製程所形成應力覆蓋層46約可增加n型金氧半導體電晶 體之開啟電流增益百分比至4.4%左右，而可使P型金氧半 導體電晶體之開啟電流增益百分比增加0.4% 。 根據本發明之一實施例’應力覆蓋層46於沈積時係為 伸張應變(tensile-stressed)狀態。且由於側壁子32已被去 除，因此應力覆蓋層46可與閘極12側壁上的襯塾層3〇直 • 接接壌。在沒有側壁子32阻隔的情況下，應力覆蓋層46 之應力便可更直接地作用於金氧半導體電晶體11()與金氧 半導體電晶體130上。如此，使得金氧半導體電晶體丨1〇 與金氧半導體電晶體130之通道區域22在通道方向上受到 與概塾層30直接接壤的氮化破蓋層46之伸張應力作用， 改變通道區域22的電子遷移率及金氧半導體電晶體之驅 動電流。 > 如第12圖所示，為了於第一主動區域丨與第二主動區 域2心成自對準金屬石夕化物，因此可進行一微啓製 程去除位於第-主動區域！内的應力覆蓋層仏，以暴露出 預定要形成自對準金屬石夕化物之區域，例如第一主動區域 1中之閘極12、源極區域18與汲極區域2〇，未被去除之 應力覆蓋層46則作為後續之自對準金屬矽化物阻擋層。 1318005 隨後進行一自對準金屬矽化物製程，於半導體基底10 表面減鑛一金屬層（未示於圖中），例如一錄金屬層，並覆 蓋在第一主動區域1、第二主動區域2與第三主動區域3 之閘極12、源極區域18、沒極區域20、以及半導體基底 10表面。接著進行一快速升溫退火製程，使金屬層與第一 主動區域1與第二主動區域2之閘極12、源極區域18與 汲極區域20接觸的部分反應成自對準金屬矽化物層42。 最後再利用一選擇性濕式蚀刻，例如以氨水與過氧化氫混 φ 合物(NH4OH/H2O2/H2O，ammonia hydrogen peroxide mixture，APM)或硫酸與過氧化氫混合物(h2S〇4/H202， sulfuric acid-hydrogen peroxide mixture，SPM)來去除未反 應成金屬矽化物之金屬層。. 如第13圖所示，接著再進行一蝕刻製程，去除應办覆 蓋層46。接著，於半導體基底10上沈積一介電層48，前 述之介電層48可以為氧化碎、摻雜氧化石夕或者低介電常數 材料專4。接著進行習知的微影暨敍刻製程，於介電層48 中形成接觸洞52，通達金氧半導體電晶體n〇、金氧半導 體電晶體120與金氧半導體電晶體13〇的閘極12、源極區 域18與汲極區域20。此外，該領域具通常知識者應知曉 本發明亦可結合接觸/同餘刻停止層（c〇ntact etch stop layer ; CESL，未圖示）之技術，亦即在完成前述之製程後， 接著再形成具適當應力之接觸洞姓刻停止層覆蓋於各相對 1318005 應金氧半導體電晶體11〇、金氧半導體電晶體12〇或金氧 半導體電晶體130 ’並使接觸洞蝕刻停止層具有不同的應 . 力狀態’例如P型金氧半導體電晶體上方的接觸洞蝕刻停 「止層係在壓縮應變狀態，而N型金氧半導體電晶體上方内 的接觸洞蝕刻停止層係在伸張應變狀態。 此外’於本發明之另一較佳實施例中，應力覆蓋層46 亦可為一雙層結構。請參考第14圖，第μ圖為本發明之 • 第二較佳實施例具有應力覆蓋層之金氧半導體電晶體的剖 面不意圖’其中相同的元件或部位仍沿用相同的符號來表 示。於此較佳實施例中，應力覆.蓋層46.同時包含有一氧化 矽層462與一氮化矽層464位於氧化矽層462之上。氧化 矽層462可以由一高溫氧化製程或一次常壓化學氣相沉積 製程所形成，其厚度約介於50埃至2〇〇〇埃之間^氮化矽 層464可以由一化學氣相沉積製程所形成，尤其注意的 鲁灭，氮化矽.層464之厚度較佳在1〇〇埃至2〇〇埃之間。需 特別留意的是，本發明之實施例中所述的厚度範圍皆是針 對65奈米製程而定，習知該項技藝者應理解本發明各尺寸 範圍可視實際需求而調整。換句話說，當電晶體的尺寸愈 來愈小時，應力覆蓋層力46的厚度可隨之薄化，以提供適 當之應力值。 當本發明之應力覆蓋層46為雙層結構時，由次常壓化 19 1318005 學氣相沉積製程所形成的氧化石夕層與厚度3〇〇埃左右 化石夕層共同構成的應力覆蓋層40可增加N型金氧半導體 晶體之開啟電流增益百分比達11-4%左右，而使P型金氧 半導體電晶體之開啟電流增益百分比減少約25 5% ;由欠 常麼化學氣相沉積製程所形成的氧化石夕層與厚度約190埃 的氮化石夕層共同構成的應力覆蓋層46約可增加_金氧半 導體電晶體之開啟電流增益百分比至10.8%，而僅使？型 金氧半導體電晶體之開啟電流增益百分比減少9篇。 本發明可以大幅增加N型金氧半導體電晶體之開啟電 流增益效果，且對於p型金氧半導體電晶體之負面影響較 J S至可增加p型金氧半導體電晶體之·電流增益效 果。前述製程亦可再搭配其他半導體製程，藉此達到大幅 增加N型金氧半導體電晶體之開啟電流增益的目的，並且 又不會減低P II金氧半導體電晶體之開啟電流增益。舉例 來說，本發明可先於—金氧半導體電晶體上形成—雙層結 構的應力覆蓋層46，包含有氧化碎層與厚度約190埃的氮 化石夕層’利用微影暨餘刻製程去除位於p型金氧半導體電 晶體上方的應力覆蓋層46，之後再利用活化製程來活化半 ，體，底10 ’使應力狀態記憶人金氧半導體電晶體之中。 1先於金氧半導體電晶體上形成-雙層結構的應 力覆蓋層46 ’包含有氧化石夕層與厚度約⑽埃的氮化矽 再進行離子佈植製程，利用鍺離子佈植來減少P型 20 1318005 金氧半導體電晶體上方的應力覆蓋層46的伸張應力，之後 再利用活化製程將應力記憶入N型金氧半導 型金氧半導體電晶體中。 體 根據本發明之第三較佳實施例，金氧半導體電晶體旁亦 可保留部分之應力覆蓋層46，作為應力側壁子M。請參考 第15圖與第16圖，第15圖至第16圖㈣的是本發明之 第三較佳實施例製作金氧半導體電晶體的方法的剖面示意 圖。於此實施例中’先利用第7圖至第11圖所示各步驟於 半導體基底lGJi形成金氧半導體電日日日體nG、金氧半導體 ，晶體120、金氧半導體電晶體130與應力覆蓋層46，接 著如第15 ®所示’進行—微影暨㈣製程去除第—主動區 蜂1中位於半導體基底1()、閘極12、源極區域】8與沒極 區域20上部分之應力覆蓋層46，並保留位於襯墊層如上 之應力覆蓋層46來作為一應力側壁子54。如此一來，應 力覆蓋層46可暴露出需形成自對準金屬砂化物之區域，而 應力側壁子54可用以保護金氧半導體電晶體11〇。I As shown in Fig. 9, the side wall sub-32 is subsequently removed, leaving the backing layer 3G on the side wall of the gate 12. According to a preferred embodiment of the present invention, after the sidewall spacers 32 are removed, an approximately [type of lining layer % is left on the sidewalls of the gate electrode 12. However, the skilled artisan and the general knowledge should understand that the pad layer % is not L-shaped, but it can also be performed - a milder (four) engraving process to slightly etch the pad layer 30 to reduce its thickness. In still other embodiments, the layer 1318005 layer 30 can even be completely removed. h 1G® does not follow the formation of a stress covering layer 46' on the semiconductor substrate iQ and covers the surface of the pad layer 3, the gate 12, the source region 18 and the non-polar region 2〇. In the preferred embodiment, the stress overburden layer 46 is a single I structure that consists of oxygen or nitrogen cut and may have a thickness between 1 angstrom and 3000 angstroms. Taking the stress-covering layer 46 of Wei-chee as an example, the formation method can be performed by using a high-temperature oxidation process on the surface of the semiconductor substrate 1 to form a full temperature oxide (HTO) as the stress coating layer 46. A layer of yttria may be deposited as a stress coating layer 46 on the surface of the semiconductor substrate 1 by a sub-pressure chemical vapor deposition (SACVD) process. For P-type gold oxide semiconductor transistors, it will be understood by those skilled in the art and those of ordinary skill in the art that after the formation of the stress cladding layer 46., the semiconductor coating process can be selectively performed to change the stress cladding layer 46. The stress state reduces the tensile stress of the stress covering layer 46 or increases the compressive stress. For example, an ion implantation process is performed to change the stress state of the stress coating layer 46 by using cesium ion implantation. Or after selectively forming the stress coating layer 46, a lithography and a remnant process is selectively performed to remove the stress coating layer 46° above the p-type MOS transistor, which can combine the compressive stress in a cap layer. The technique of stretching the tensile stress is called a selective strain system (SSS), as in the preferred embodiment, because of the MOS transistor in the second active region 2 (10). There is no need to make a stress change, so the stress coating layer 46 located in the second active region 2 / the stress covering layer 46 'located on the first active region and the third active region 3 can be removed by the lithography and (4) process to expose The gate 12, the source region 18 and the drain region 2〇 in the second active region 2 are exited. Then, 1% of the stress t cap layer 46 is subjected to an in-situ or off-site activation process: for example, a UV curing process, an annealing process, and a high temperature peak annealing (the_l spike) _called process or electron beam (e-beam) processing. The stress is memorized into the MOS transistor and the MOS transistor 13 by the activation process, and the lattice arrangement of the semiconductor substrate 10 of the channel region 22 is pulled. , thereby increasing the shift rate of the channel region U located in the first active region! and the third active region 3, and the driving current of the MOS transistor U〇 and the MOS semiconductor Thunder. When the stress coating layer 46_ single layer structure of the present invention, the oxide layer formed by the sub-atmospheric pressure chemical vapor deposition process is about to increase the stress coverage ratio of the N-type MOS transistor ( Ion gain percentage) is about 5.3%, and only ^ P-type gold oxide half 1318005 ... the percentage of the opening current gain of the conductor transistor is reduced by 0.7%; the stress coating layer 46 formed by the high-temperature oxidation process can increase the n-type gold oxide Semiconductor power The opening current gain percentage of the body is about 4.4%, and the percentage of the opening current gain of the P-type MOS transistor can be increased by 0.4%. According to an embodiment of the present invention, the stress covering layer 46 is a tensile strain when deposited ( The tensile-stressed state, and since the sidewall sub-32 has been removed, the stressor layer 46 can be aligned with the lining layer 3 on the sidewall of the gate 12. Without the barrier of the sidewall 32, the stress The stress of the cap layer 46 acts more directly on the MOS transistor 11() and the MOS transistor 130. Thus, the channel region of the MOS transistor 金1〇 and the MOS transistor 130 is made. 22 is subjected to the tensile stress of the nitride capping layer 46 directly bordering the schematic layer 30 in the channel direction, and the electron mobility of the channel region 22 and the driving current of the MOS transistor are changed. > In order to make the self-aligned metal cerium compound in the first active region 丨 and the second active region 2, a micro-start process can be performed to remove the stress covering layer 位于 in the first active region! Exposing a region where a self-aligned metallurgical compound is to be formed, such as the gate 12, the source region 18 and the drain region 2〇 in the first active region 1, and the unremoved stress coating layer 46 is used as a follow-up Self-aligned metal telluride barrier layer. 1318005 A self-aligned metal telluride process is then performed to demineralize a metal layer (not shown) on the surface of the semiconductor substrate 10, such as a metal layer, and is covered first. The active region 1, the second active region 2 and the third active region 3 have a gate 12, a source region 18, a gate region 20, and a surface of the semiconductor substrate 10. Then, a rapid thermal annealing process is performed to react the metal layer with the first active region 1 and the gate 12 of the second active region 2, and the portion of the source region 18 in contact with the drain region 20 to form a self-aligned metal telluride layer 42. . Finally, a selective wet etching is used, for example, a mixture of ammonia and hydrogen peroxide (NH4OH/H2O2/H2O, ammonia hydrogen peroxide mixture, APM) or a mixture of sulfuric acid and hydrogen peroxide (h2S〇4/H202, sulfuric) Acid-hydrogen peroxide mixture (SPM) to remove metal layers that are not reacted into metal halides. As shown in Fig. 13, an etching process is then performed to remove the cover layer 46. Next, a dielectric layer 48 is deposited on the semiconductor substrate 10. The dielectric layer 48 may be oxidized, doped with oxidized or a low dielectric constant material. Then, a conventional lithography and lithography process is performed to form a contact hole 52 in the dielectric layer 48, and access to the gate 12 of the MOS transistor n〇, the MOS transistor 120, and the MOS transistor 13〇. The source region 18 and the drain region 20. In addition, those skilled in the art should be aware that the present invention may also incorporate the technique of a contact/de-sequence stop layer (CESL, not shown), that is, after completing the aforementioned process, and then Forming a contact hole with appropriate stress, the stop layer covers each of the opposite 1318005 MOS transistors 11 金, MOS transistor 12 〇 or MOS transistor 130 ′ and makes the contact etch stop layer different The force state 'for example, the contact hole etching above the P-type MOS transistor is stopped in the compressive strain state, and the contact hole etch stop layer in the upper portion of the N-type MOS transistor is in the tensile strain state. In addition, in another preferred embodiment of the present invention, the stress covering layer 46 may also be a two-layer structure. Please refer to FIG. 14 , which is a second preferred embodiment of the present invention having a stress coating layer. The cross-section of the MOS transistor is not intended to mean that the same elements or portions are still denoted by the same reference numerals. In the preferred embodiment, the stress capping layer 46. contains an oxygen at the same time. The ruthenium layer 462 and the tantalum nitride layer 464 are located on the ruthenium oxide layer 462. The ruthenium oxide layer 462 can be formed by a high temperature oxidation process or a one-time atmospheric pressure chemical vapor deposition process, and has a thickness of about 50 angstroms to 2 Å. The tantalum nitride layer 464 can be formed by a chemical vapor deposition process, especially the annihilation, tantalum nitride layer 464 has a thickness of preferably 1 〇〇 to 2 〇〇. It should be noted that the thickness ranges described in the embodiments of the present invention are all for the 65 nm process, and those skilled in the art should understand that the various size ranges of the present invention can be adjusted according to actual needs. In other words, as the size of the transistor becomes smaller, the thickness of the stress overburden 46 can be thinned to provide a suitable stress value. When the stressor layer 46 of the present invention has a two-layer structure, the sub-atmospheric pressure 19 1318005 The oxidized stone layer formed by the vapor deposition process and the stress coating layer 40 formed by the thickness of 3 angstroms or so of the fossil layer can increase the opening current gain percentage of the N-type MOS crystal by 11-4%. P-type MOS semiconductor crystal The opening current gain percentage of the body is reduced by about 25 5%; the stress coating layer 46 formed by the oxidized stone layer formed by the underlying chemical vapor deposition process and the nitriding layer having a thickness of about 190 angstroms can be increased by about _ gold. The percentage of the on-current gain of the oxy-semiconductor transistor is 10.8%, and only the percentage of the on-current gain of the MOS transistor is reduced by 9. The invention can greatly increase the on-current gain effect of the N-type MOS transistor. Moreover, the negative effect on the p-type MOS transistor can increase the current gain effect of the p-type MOS transistor compared to JS. The above process can be combined with other semiconductor processes to achieve a large increase in the N-type MOS. The purpose of the transistor's turn-on current gain is that it does not reduce the turn-on current gain of the P II MOS transistor. For example, the present invention can be formed on a MOS transistor to form a two-layered stress cladding layer 46 comprising an oxidized fragment layer and a nitriding layer having a thickness of about 190 angstroms. The stress capping layer 46 over the p-type MOS transistor is removed, and then the activation process is used to activate the half, body, and bottom 10' to stress state in the MOS transistor. 1 The stress coating layer 46' formed on the MOS transistor is composed of a oxidized stone layer and a tantalum nitride layer having a thickness of about (10) angstroms, and then subjected to an ion implantation process, and the cesium ion implantation is used to reduce P. Type 20 1318005 The tensile stress of the stress coating layer 46 above the MOS transistor, and then the activation process is used to memorize the stress into the N-type MOS semiconductor transistor. According to a third preferred embodiment of the present invention, a portion of the stress cladding layer 46 may remain as a stress sidewall M adjacent to the MOS transistor. Referring to Figs. 15 and 16, and Figs. 15 to 16 (d) are sectional views showing a method of fabricating a MOS transistor according to a third preferred embodiment of the present invention. In this embodiment, the steps of FIGS. 7 to 11 are first used to form a gold oxide semiconductor electric solar cell nG, a gold oxide semiconductor, a crystal 120, a MOS semiconductor transistor 130, and a stress covering on the semiconductor substrate 1GJi. Layer 46, then as shown in Fig. 15', the lithography and (4) process removes the portion of the first active region bee 1 located in the semiconductor substrate 1 (), the gate 12, the source region 8 and the non-polar region 20 The stress coat layer 46 is retained as a stress sidewall 54 at the pad layer 46 as described above. As such, the stressor layer 46 can expose areas where self-aligned metallization is to be formed, and the stress sidewalls 54 can be used to protect the MOS transistor 11A.
Ik後進行-自對準金屬魏物製程，並利用未被去除之 應力覆蓋層46作為自對準金屬魏物阻擔層，於基底1〇 表面濺鍍一金屬層（未示於圖中），並覆蓋在第一主動區域1 與第-主動區域2之閘極12、源極區域18、汲極區域2〇、 以及半導體基底1G表面。接著進行—快速升溫退火製程， 1318005 使金屬層與第一主動區域1、第二主動區域2與第三主動 區域3之閘極12、源極區域18與汲極區域2〇接觸的部分 1 反應成自對準金屬矽化物層42。之後再利用SPM或ApM -去除未反應成金屬石夕化物之金屬層。 如第16圖所示，接著再進行一姓刻製程，去除第三主 動區域3内，位於半導體基底10、閘極丨2、源極區域18 與没極區域20上之應力覆蓋層46，而保留位於金氧半導 • 體電晶體11〇與金氧半導體電晶體130之襯墊層3〇上之應 力覆蓋層46來作為一應力側壁子54。接著，於半導體基 底10上沈積一介電層48,前述之介電層48可以為氧化矽、 捧雜氧化矽或者低介電常數材料等等。接著進行一微影暨 餘刻.製程，於介電層48中形成接觸洞52，通達金氧半導 體電晶體110、金氧半導體電晶體120與金氧半導體電晶 體13 0的閘極12、源極區域18與没極區域2〇。 此外，於本發明之另一較佳實施例中，此處之應力側壁 亦可為-雙層結構。請參考第17圖，第17圖為本發 明之第四較佳實施例具有應力側壁子之金氧半導體電晶體 的剑面示意圖，其中相同的元件或部位仍沿用相同的^號 ，表示。於此較佳實施例中，應力側壁子54同時包含有二 氧化矽層542與一氮化矽層544位於氧化矽層542之上。 氧化矽層542可以由一高溫氧化製程或一次常壓化學氣相 22 1318005 沉積製程所形成，其厚度約介於5〇 氮化石夕層544之厚度較佳在100埃至至2咖埃之間’而 • 矢至200埃之間。 需特別留意的是，應力側壁子54 .切齊(如第Π圖之第-主動區域！ ^與襯墊層30之邊緣 層30之邊緣外（如帛π 之第三主動~^亦可覆蓋於概塾 裸露出襯墊層30之邊緣部分(如第區域3所示），更可 所示）。 圖之第一主動區域1 本發明的特徵在於先去除金氧半 子，再於金氧半導體電晶體上形成，電晶體之側壁 構上應變。由於側壁子已被去除，因來產生結 極側壁上的襯墊層直接接壤。如此：覆盍層可與閘 ,.1吏件通道區域在通道 方向上受到與襯墊層直接接壞的氮化石夕蓋層之鹿力作用。 在沒有側壁子阻隔的情況下，應力覆蓋層之應力將可更直 接地作用於金氧半導體電晶體上，改變通道區域的晶格常 •數，使金氧半導體電晶體可以具有較高的驅動電流，藉此 提升半導體電晶體的操作效能。此外，應力覆蓋層亦可同 時作為後續製程之自對準金屬矽化物阻擋層，使金氧半導 體電晶體之製程簡化。 而且根據上述各實施例之製程，本發明更可針對一半 • 導體基底之不同區域而同時形成多種不同結構的金氧半導 23 1318005 =電曰曰體例如可同時形成一具有應變 屬石夕化物之金氧半導體電晶體、、自對準金 "附屬斷金氧半導體電晶體二不::變而:; 不具自對準金屬魏物之金氧半導體電晶體了因 本發明^旦可同時製作多個金氧半導體電晶體，亦可針對 不同需求而形成多種不同結構之金氧半導體電晶體。 以上所述僅為本發明之較佳實施例，凡依本發明申 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍月。 【.圖式簡單說明】 第！圖至第6圖為f知提升金氧半導體電晶體的驅動電流 之方法示意.圖。 第7圖至第13圖緣示的是本發明之第一較佳實施例製作金 氧半導體電晶體的方法的剖面示意圖。 第14圖為本發明之第二較佳實施例具有應力覆蓋層之金 氧半導體電晶體的剖面示意圖。 第15圖至第16圖繪示的是本發明之第三較佳實施例製作 金氧半導體電晶體的方法的剖面示意圖。 第17圖為本發明之第四較佳實施例具有應力覆蓋層之金 氧半導體電晶體的剖面示意圖。 24 1318005 【主要元件符號說明】After Ik, the self-aligned metal material process is performed, and the uncovered stress coating layer 46 is used as a self-aligned metal material resist layer, and a metal layer (not shown) is sputtered on the surface of the substrate 1 (not shown). The gate 12, the source region 18, the drain region 2A, and the surface of the semiconductor substrate 1G of the first active region 1 and the first active region 2 are covered. Then, a rapid thermal annealing process is performed, and 1318005 reacts the metal layer with the first active region 1, the second active region 2 and the gate 12 of the third active region 3, and the portion 1 where the source region 18 is in contact with the drain region 2〇. The self-aligned metal telluride layer 42 is formed. The SPM or ApM- is then used to remove the metal layer that has not been reacted into the metallurgical compound. As shown in FIG. 16, a further etching process is performed to remove the stress covering layer 46 on the semiconductor substrate 10, the gate electrode 2, the source region 18, and the non-polar region 20 in the third active region 3. The stress cladding layer 46 on the pad layer 3 of the MOS semiconductor body 11 and the MOS transistor 130 is retained as a stress sidewall 54. Next, a dielectric layer 48 is deposited on the semiconductor substrate 10. The dielectric layer 48 may be yttrium oxide, ytterbium oxide or a low dielectric constant material or the like. Then, a lithography and a process is performed to form a contact hole 52 in the dielectric layer 48, and the gate 12 and the source of the MOS transistor 110, the MOS transistor 120, and the MOS transistor 110 are accessed. The pole region 18 and the poleless region 2〇. Furthermore, in another preferred embodiment of the invention, the stress sidewalls herein may also be a two-layer structure. Referring to FIG. 17, FIG. 17 is a schematic cross-sectional view showing a metal oxide semiconductor transistor having a stress sidewall according to a fourth preferred embodiment of the present invention, wherein the same elements or portions are still indicated by the same ^. In the preferred embodiment, the stress sidewalls 54 include both a hafnium oxide layer 542 and a tantalum nitride layer 544 over the hafnium oxide layer 542. The yttria layer 542 may be formed by a high temperature oxidation process or a primary atmospheric chemical vapor phase 22 1318005 deposition process, and has a thickness of about 5 Å. The thickness of the nitride layer 544 is preferably between 100 Å and 2 Å. 'And the vector is between 200 angstroms. It should be noted that the stress sidewalls 54 are aligned (as in the first-active region of the second figure! ^ and the edge of the edge layer 30 of the liner layer 30 (eg, the third active ~^ of 帛π can also be covered) The edge portion of the liner layer 30 is exposed (as shown in the third region), which may be shown.) The first active region 1 of the present invention is characterized in that the gold oxide half is removed first, and then the gold oxide is removed. Formed on the semiconductor transistor, the sidewall of the transistor is strained. Since the sidewall has been removed, the liner layer on the sidewall of the junction is directly bordered. Thus: the cover layer can be connected to the gate. In the direction of the channel, it is subjected to the deer force of the nitride layer which is directly damaged by the liner layer. Without the sidewall spacer, the stress of the stress coating layer can be more directly applied to the MOS transistor. By changing the lattice constant of the channel region, the MOS transistor can have a higher driving current, thereby improving the operational efficiency of the semiconductor transistor. In addition, the stress coating layer can also be used as a self-alignment for subsequent processes. Metal telluride barrier layer, The process of the MOS transistor is simplified. Moreover, according to the processes of the above embodiments, the present invention can simultaneously form a plurality of different structures of MOS semiconductors for different regions of the conductor substrate. 13 1318005 = 曰曰 例如At the same time, a gold-oxygen semiconductor transistor with a strained ceramsite is formed, and a self-aligned gold "subsidiary gold-oxide semiconductor transistor is not changed:: a metal oxide semiconductor device that does not have a self-aligned metal material Crystals According to the present invention, a plurality of MOS transistors can be simultaneously fabricated, and a plurality of different structures of MOS transistors can be formed for different needs. The above description is only a preferred embodiment of the present invention. The equal changes and modifications made by the scope of the present invention should be within the scope of the present invention. [. Brief description of the drawings] The figures from Fig. 6 to Fig. 6 show that the driving current of the MOS transistor is improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 7 to Fig. 13 are schematic cross-sectional views showing a method of fabricating a MOS transistor according to a first preferred embodiment of the present invention. 2 is a schematic cross-sectional view of a MOS transistor having a stress coating layer. FIGS. 15 to 16 are cross-sectional views showing a method of fabricating a MOS transistor according to a third preferred embodiment of the present invention. Figure 17 is a cross-sectional view showing a metal oxide semiconductor transistor having a stress coating layer according to a fourth preferred embodiment of the present invention. 24 1318005 [Explanation of main component symbols]
1 第一主動區域 2 第二主動區域 3 第三主動區域 10 半導體基底 12 閘極 14 閘極介電層 17 淺接面源極延伸 18 源極區域 19 淺接面汲極延伸 20 汲極區域 22 通道區域 30 襯墊層 32 側壁子 42 自對準金屬矽化物層 46 應力覆蓋層 48 介電層 52 接觸洞 54 應力側壁子 110 金氧半導體電晶體 120 金氧半導體電晶體 130 金氧半導體電晶體 300 半導體裝置 301 通道區域 302 主動區域 303 主動區域 304 閘極氧化層 305 多晶矽氧化物 306 多晶珍閘極 309 基底 310 N型摻質 311 偏移側壁子 315 蝴換質區 407 源極區 408 >及極區 412 側壁子 413 側壁子 414 側壁子 462 氧化矽層 464 氮化矽層 516 混合覆蓋層 818 金屬矽化物 542 氧化矽層 25 1318005 544 氮化矽層1 first active region 2 second active region 3 third active region 10 semiconductor substrate 12 gate 14 gate dielectric layer 17 shallow junction source extension 18 source region 19 shallow junction drain extension 20 drain region 22 Channel region 30 pad layer 32 sidewall spacer 42 self-aligned metal germanide layer 46 stress cap layer 48 dielectric layer 52 contact hole 54 stress sidewall 110 MOS transistor 120 MOS transistor 130 MOS transistor 300 Semiconductor device 301 Channel region 302 Active region 303 Active region 304 Gate oxide layer 305 Polycrystalline germanium oxide 306 Polycrystalline gate 309 Substrate 310 N-type dopant 311 Offset sidewall 315 Butter exchange region 407 Source region 408 > And polar region 412 sidewall 413 sidewall 414 sidewall 462 yttrium oxide layer 464 tantalum nitride layer 516 mixed cladding layer 818 metal telluride 542 yttrium oxide layer 25 1318005 544 tantalum nitride layer