1312465 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電腦資訊技術，特別是有關於一 種電腦周邊裝置組態資料最優化循序處理方法及系統，其 可應用於搭載至一電腦平台，且該電腦平台配置有一周邊 連接介面來連結至多個周邊裝置’例如為PCI (Peripheral Component Interconnect)式之周邊連接介面，用以對該電腦 平台提供一周邊裝置組態資料最優化循序處理功能，藉此 ®而讓各個周邊裝置的初始化過程中，可更為有效能地透過 一容量有限的影射式隨機存取記憶體（Shadow RAM，其中 RAM = Random-Access Memory)及依據一最優化之處理順 序來處理各個周邊裝置中的組態唯讀記憶體（Option ROM，或簡化為 OPROM，其中 ROM = Read-Only Memory) 所儲放的組態資料。 【先前技術】 PCI (Peripheral Component Interconnect)為電腦平台 上常採用的一種周邊連接介面，其可用以將電腦平台的中 央處理單元向外搭接至至各式之周邊裝置，例如包括螢幕 顯示器、硬碟裝置、光碟機、網路切換器、等等，藉以讓 中央處理單元可與此些周邊裝置進行資料交流。 PCI周邊裝置中通常内建有一組態唯讀記憶體（Option ，其中R〇M = Read-Only Memory)，用以儲放其所屬 之pci周邊裝置於實際搭接至電腦平台時所需之組態資 料；亦即PCI周邊裝置所搭接之電腦平台可直接從此組態 5 19026 1312465 唯讀記憶體（OPROM)中讀取其中所儲放之組態資料，即可 直接對PCI周邊裝置進行初始化而讓電腦平台可與pci周 邊裝置進行資料交流。基本上，由於隨機存取記憶體 (Random-Access Memory，RAM)的存取速度大於唯讀記 憶體（Read-Only Memory, ROM);因此於具體實施上，為 了增加組態資料的存取速度，電腦平台中的隨機存取記憶 體中通常規劃有一特定之儲存空間，一般稱為影射式隨機 存取記憶體（Shadow RAM) ’藉以用來以影射方式（即複製 方式）暫存PCI周邊裝置中的組態唯讀記憶體中所儲放之 組態資料，以藉此來增進整體之周邊處理效能。 於實際操作時，電腦平台會依據各個周邊裝置的匯流 排被偵測到的先後順序來於影射式隨機存取記憶體中依序 建立一對應之PCI組態影射區塊，用來以影射之複製方式 儲放其所屬之周邊裝置的組態唯讀記憶體中的組態資料； 並接著依序處理此些PCI組態影射區塊所儲放之組態資 籲料。舉例來說，若有5個周邊裝置PCI(l)、PCI(2)、PCI(3)、 PCI(4)、PCI(5)分別安裝於 PCI 匯流排 PCI_BUS(1)、 PCI—BUS(2)、PCI_BUS(3)、PCI—BUS(4)、PCI_BUS(5)， 且其配對方式為PCI(l)安裝至PCI_BUS(3)、PCI(2)安裝至 PCI—BUS(5)、PCI(3)安裝至 PCI_BUS(4)、PCI(4)安裝至 PCI—BUS(l)、以及 PCI(5)安裝至 PCI—BUS(2);貝|J 由於電 腦平台電腦對周邊裝置匯流排的偵測是按照PCI_BUS(1) —PCI—BUS(2 卜 PCI—BUS(3)->PCI—BUS(4)—PCI_BUS(5) 的順序，因此前述之5個周邊裝置被偵測及處理的順序為 6 19026 1312465 PCI(4)—PCI(5)—PCI(l)—PCI(3)—PCI(2)。電腦平台會依 序於影射式隨機存取記憶體中建立5個對應之PCI組態影 射區塊，並即按照 PCI(4)->PCI(5)—PCI(1)—PCI(3)— PCI(2)的順序來依序處理此些PCI組態影射區塊中所影射 的組態資料。 於實際應用上，一般之電腦平台中的影射式隨機存取 記憶體的容量大都僅有128KB(C0000h-DFFFFh)，因此其 僅能有限地支援一定數目的周邊裝置。舉例來說，若有一 鲁必要且最優先的PCI周邊裝置（例如為VGA視訊控制卡） 的OPROM組態資料數碼量為32KB，則其實際執行時將佔 用影射式隨機存取記憶體中的32KB的儲存空間，使得 32KB影射式隨機存取記憶體的可用儲存空間僅剩下 128-32 = 96KB。於此情況下，其它之PCI周邊裝置的處理 順序將影響到電腦平台的整體之周邊處理效能。舉例來 說，假設有4個PCI周邊裝置PCI(l)、PCI(2)、PCI(3)、 籲PCI(4)的OPROM原始組態資料的數碼量分別為64KB、 ‘ 64KB、32KB、和24KB，但其於初始化過程中被實際執行 • 時之數碼量僅分別為6KB、32KB、32KB、和16KB ;則如 下表所示，於影射式隨機存取記憶體僅剩96KB的情況 下，若此4個PCI周邊裝置按PCI(lhPCI(2) —PCI(3) —PCI(4)的處理順序，則此4個PCI周邊裝置均可被處理 到。 瓦邊裊置~丨原始組熊資[#際埶行日^ lShad〇wRAM剩^ 7 19026 13124651312465 IX. Description of the invention: [Technical field of the invention] The present invention relates to a computer information technology, and more particularly to a method and system for optimizing the configuration of a computer peripheral device configuration data, which can be applied to a computer a platform, and the computer platform is configured with a peripheral connection interface to connect to a plurality of peripheral devices, such as a peripheral interface of a PCI (Peripheral Component Interconnect) type, to provide a peripheral device configuration data optimization sequence processing function for the computer platform. By using this, the initialization process of each peripheral device can be more effectively transmitted through a limited amount of shadow random access memory (Shadow RAM, RAM = Random-Access Memory) and according to an optimization. The processing sequence is used to process the configuration data stored in the configuration read-only memory (Option ROM, or simplified to OPROM, where ROM = Read-Only Memory) in each peripheral device. [Prior Art] PCI (Peripheral Component Interconnect) is a peripheral connection interface commonly used on computer platforms. It can be used to connect the central processing unit of the computer platform to various peripheral devices, such as a screen display and hard. A disk device, a CD player, a network switcher, etc., so that the central processing unit can communicate with such peripheral devices. PCI peripheral devices usually have a built-in read-only memory (Option, where R〇M = Read-Only Memory), which is used to store the group of pci peripheral devices it belongs to when it is actually connected to the computer platform. State data; that is, the computer platform connected by the PCI peripheral device can directly read the configuration data stored therein from the configuration 5 19026 1312465 read-only memory (OPROM), and can directly initialize the PCI peripheral device. And let the computer platform exchange data with the peripheral devices of the pci. Basically, since the access speed of the random access memory (RAM) is larger than that of the read-only memory (ROM), in order to increase the access speed of the configuration data. In the random access memory in the computer platform, a specific storage space is generally planned, which is generally referred to as a shadow random access memory (Shadow RAM), which is used to temporarily store the PCI peripheral device in a mapping manner (ie, copy mode). The configuration in the read-only memory stores the configuration data to improve the overall peripheral processing performance. In actual operation, the computer platform sequentially creates a corresponding PCI configuration mapping block in the mapped random access memory according to the detected order of the bus bars of each peripheral device, for mapping The copy mode stores the configuration data in the configuration read-only memory of the peripheral device to which it belongs; and then sequentially processes the configuration information stored in the PCI configuration mapping block. For example, if there are five peripheral devices PCI (1), PCI (2), PCI (3), PCI (4), PCI (5) installed in the PCI bus PCI_BUS (1), PCI - BUS (2) ), PCI_BUS (3), PCI-BUS (4), PCI_BUS (5), and its pairing mode is PCI (1) installed to PCI_BUS (3), PCI (2) installed to PCI - BUS (5), PCI ( 3) Installation to PCI_BUS (4), PCI (4) installation to PCI-BUS (l), and PCI (5) installation to PCI-BUS (2); Bay | J due to the computer platform computer to the peripheral device bus The measurement is in the order of PCI_BUS (1) - PCI - BUS (2 PCI - BUS (3) -> PCI - BUS (4) - PCI_BUS (5), so the above five peripheral devices are detected and processed. The order is 6 19026 1312465 PCI(4)-PCI(5)-PCI(l)-PCI(3)-PCI(2). The computer platform will create 5 corresponding PCIs in the mapped random access memory. The mapping blocks are configured, and the PCI configuration mapping blocks are sequentially processed in the order of PCI(4)->PCI(5)-PCI(1)-PCI(3)-PCI(2). The configuration data that is mapped. In practical applications, the capacity of the mapped random access memory in the general computer platform is only 128KB (C0000h-DFFFFh). Therefore, it can only support a limited number of peripheral devices. For example, if there is a necessary and highest priority PCI peripheral device (for example, a VGA video control card), the OPROM configuration data is 32 KB. The actual execution will occupy 32KB of storage space in the mapped random access memory, so that the available storage space of the 32KB mapped random access memory is only 128-32 = 96KB. In this case, other PCI peripherals The processing sequence of the device will affect the overall peripheral processing performance of the computer platform. For example, suppose there are 4 PCI peripheral devices PCI (1), PCI (2), PCI (3), PCI (4) OPROM original The digital quantities of the configuration data are 64KB, '64KB, 32KB, and 24KB, respectively, but they are actually executed during the initialization process. The digital quantities are only 6KB, 32KB, 32KB, and 16KB respectively; as shown in the following table, In the case of only 96 KB of the mapped random access memory, if the four PCI peripheral devices are in PCI (lhPCI (2) - PCI (3) - PCI (4) processing order, then the four PCI peripheral devices Can be processed to. Tile side set ~ 丨 original group bear capital [ #际埶日^ lShad〇wRAM left ^ 7 19026 1312465
處理順序 料數碼量 數碼量 空間 順序1: PCI⑴ 64KB 6KB 96 - 6 = 90KB (>64KB) 順序2 : PCI(2) 64KB 32KB 90 - 32 = 58KB (>32KB) 順序3 : PCI(3) 32KB 32KB 58-32 = 26KB (>24KB) 順序4 : PCI⑷ 24KB 16KB 26-16= 10KB 反之，如下表所示，若上述之4個PCI周邊裝置的處 •理順序改為 PCI(2hPCI(3) —PCI(4) —PCI(l)，則僅能處 理到前面3個PCI周邊裝置。Processing sequence material digital quantity digital space order 1: PCI(1) 64KB 6KB 96 - 6 = 90KB (>64KB) Order 2: PCI(2) 64KB 32KB 90 - 32 = 58KB (>32KB) Sequence 3: PCI(3) 32KB 32KB 58-32 = 26KB (>24KB) Sequence 4: PCI(4) 24KB 16KB 26-16= 10KB Conversely, as shown in the following table, if the above four PCI peripheral devices are changed to PCI (2hPCI (3) ) - PCI(4) - PCI(l), only the first three PCI peripherals can be processed.
周邊裝 置處理 順序 原始組態資料 數碼量 實際執行時之 數碼量 Shadow RAM 剩餘空間 順序1 : PCI(2) 64KB 32KB 96 - 32 = 64KB (>32KB) 順序2 : PCI(3) 32KB 32KB 64 - 32 = 32KB (>24KB) 順序3 : PCI(4) 24KB 16KB 32 - 16 = 16KB (< 64 KB) 順序4 : PCI(l) 64KB X X 如上表所示，當順序3的PCI(4)被處理時，影射式 隨機存取記憶體的可用儲存空間僅剩下16KB，因此其將 不足夠用來載入順序4之PCI(l)的64KB的原始組態資 料。 8 19026 1312465 【發明内容】 曰鑒於以上所述習知技術之缺點，本發明之主要目的便 疋在於提供一種電腦周邊裝置組態資料最優化循序處理方 法^系統，其可令一固定容量的影射式隨機存取記憶體可 同時較先前技術支援數目更多的周邊裝置。 吹，發明之另一目的在於提供一種電腦周邊裝置組態 貧=最優化循序處理方法及系統，其可讓影射式隨機存取 ⑩纪憶體之儲存空間的利用更為具有彈性及有效率。 本發明之電腦周邊裝置組態資料最優化循序處理方 2及系統錢計來應用於搭餘—電腦平台，且該電腦平 =己置有-周邊連接介面來連結至多個周邊裂置，例如為 式^周邊連接介面，用以對該電腦平台提供一周邊震 =貝枓最優化循序處理功能，藉此而讓各 ^刀始化過程中，可更為有效能地透過 = 式，存取記憶體（ShadowRAM)及依據 ^射 所儲放的組態資料。置令的組態唯頃記憶體（⑽〇M) 法至周邊裝置組態資料最優化循序處理方 安二二:開機事件而讀取該電腦平台當前所 始組態資料；⑺對組悲唯讀記憶體所儲放之原 資料分別執行—執行3士貝 <各個周邊裝置的原始組態 各個周邊裝置的朴：=:量計算程序，藉此而計算出 量；（3)依擄初始化時的二二=純時的執行時間數碼 才間數碼量來為該些周邊裝置 19026 9 1312465 -始組，資料於初始化過程中的執行時間數碼量，並據以定 '出:最優化之處理順序來將各個周邊裝置的原始組態資料 於貫際進行初始化程序時暫存至影射式隨機存取記憶體。 相較於先前技術，此特點可讓電腦平台同時支援數目更多 的周邊裝置，並可讓影射式隨機存取記憶體之儲存空間的 利用更為具有彈性及有效率。 【實施方式】 • '下17配&所附之圖式，詳細揭露本發明之電腦周邊 裝置組態資料最優化循序處理方法及系統之實施例。 第1圖即顯示本發明之電腦周邊裝置組態資料最優化 循序處理系統（如標號100所指之方塊）的應用方式。如圖 所不，本發明之電腦周邊裝置組態資料最優化循序處理系 統100於實際應用上係搭載至一電腦平台1〇，例如為桌'上 型個人電腦、筆記型電腦、或網路飼服器，且該電腦平台 10須至少配置有-巾央處理單元（CentralPn>eessing㈣口 ♦ cpupo、-影射式隨機存取記憶體（Shad〇wRAM，並中 RAM = Random_Access Mem〇ry) 3〇、和一特定型式的周邊 連接介面40 ;其中該周邊連接介面4〇例如為一 (Pedphera! Component Interc〇nnect)式之周邊連接介面 40,可用以向外搭接至一或多個周邊裝置（第}圖所示之實 鈿例中，例如為搭接至4個周邊裝置41、42、43、及一 VGA視訊控制卡45，·但於實際應用上，其可搭接之周邊 裝置的數目係視影射式隨機存取記憶體 t 且其中每一個搭接上的周邊震置41、42、43、:4里均而=内 π 19026 1312465 建有一組態唯讀記憶體（Option ROM，或簡化為OPROM， 其中 ROM = Read-Only Memory) 51、52、53、54，用以分 別預先儲放其所屬之周邊裝置41、42、43、44的一組與開 機有關的組態資料（以下稱為"原始組態資料"）。 於實際操作時，本發明之電腦周邊裝置組態資料最優 化循序處理系統100即可對該電腦平台10所搭接上之所 有的周邊裝置4卜42、43、44提供一電腦周邊裝置組態資 料最優化循序處理功能，藉此而讓該電腦平台1 〇可更為有 肇效能地令其中央處理單元20與各個周邊裝置4卜42、43、 44之間進行資料交流，並可讓使用者可安裝更多數目的周 邊裝置至該電腦平台10。 如第2圖所示，本發明之電腦周邊裝置組態資料最優 化循序處理系統100的物件導向元件模型（object-oriented component model)的基本架構至少包含：(A)—原始組態資 料讀取模組110 ; (B)—執行時間數碼量計算模組120 ; (C) 籲一處理順序訂定模組130 ;以及（D)—組態資料影射模組 140。於具體實施上，本發明之電腦周邊裝置組態資料最優 — 化循序處理系統100可完全以電腦程式來實現，並將此電 腦程式例如以一附加模組（add-on module)方式整合至該電 腦平台 10 中的 BIOS(Basic Input/Output System)基本輸出 入系統或作業系統，並藉由該電腦平台10的中央處理單元 20來執行而提供所需之電腦周邊裝置組態資料最優化循 序處理功能。 以下即首先分別說明本發明之電腦周邊裝置組態資 12 19026 1312465 1 最優化猶序處理“⑽中的各個構成模組110、120、 30、14〇的個別屬性及功能 始組態資料讀取模組110可回應該電腦平台⑺上 二―^ _機事件2G1 (亦即使用者啟動該電腦平台 仃-開機程序)而讀取該電腦平台10 ==邊裝置41、42、43、44中的組_,: 54所分別儲放之原始組態資料。 料心:寺:’數碼量計算模組120可對上述之原始組態資 4二取核1 且110所讀取出之各個m周邊褒置41、42、43 序組”料分職行—執行時間數碼量計算程 ^而叶异出各個PCI周邊裝置41、42、43、44的 、且心'貝料的執行時間（runtime)數碼量，亦即於#射a α 中實際被執行時的數碼量==機周 其實際之執Μ日I”、44的原始組態資料於初始化過程中， 料幻口仃扦間數碼量通常會小於原來之原始組態資 為刪，則•、有^衣置的原始組態資料的數碼量 可能僅剩下2〇κΓ 過程中的實際之執行時間數石馬量 處理料訂㈣組13Q可依據上述 计异模組120所p AA y μ j 了间数碼罝 42、43、44定^ /异結果來首先為該些周邊裝置4卜 最優化之處理:序—Γ憂化之處理順序。於具體實施上，此 周邊震置為第4=始:時:執行時間數妈量最少的 理，依此類推。1:=里：少的周邊裝置為第二優先處 有個或2個以上之周邊裝置之執行時 19026 13 1312465 間數碼量為相等，則以其原始組態資料之數碼量較大者作 為優先；但若此些周邊裝置之原始組態資料數碼量亦為相 等，則例如以其安裝順序較前者作為優先。舉例來說，假 設周邊裝置{PCI(l), PCI(2), PCI(3)，PCI(4)} 41、42、43、 44的OPROM原始組態資料的數碼量分別為64KB、 64KB、32KB、和24KB，但其初始化時的執行時間數碼量 僅分別需要6KB、32KB、32KB、和16KB ;則其最優化之 處理順序將訂定為 PCI(1>PCI(4)->PCI(2)—PCI(3)。 ® 組態資料影射模組140可依據上述之處理順序訂定模 組130所訂定之最優化之處理順序來依序將各個周邊裝置 41、42、43、44的原始組態資料影射（即複製）至該影射式 隨機存取記憶體30，令各個周邊裝置41、42、43、44的 原始組態資料可於該影射式隨機存取記憶體30中被處理 而令各個周邊裝置41、42、43、44完成初始化程序。 以下即利用一應用實例來說明本發明之電腦周邊裝 籲置組態資料最優化循序處理系統1〇〇於實際應用時的操作 方式。於此應用實例中，假設電腦平台1 〇的影射式隨機存 取記憶體30的容量僅為128KB，而PCI周邊連接介面40 預先搭接上有一原始組態資料為32KB的VGA視訊控制卡 45，隨後使用者又另搭接上了 4個周邊裝置41、42、43、 44，且其中之組態唯讀記憶體5 1、52、53、54所儲存之原 始組態資料的數碼量分別為為64KB、64KB、32KB、和 24KB，但其於初始化過程中被實際執行時之數碼量僅分別 為 6KB、32KB、32KB、和 16KB。 14 19026 1312465 請同時參閱第i圖和第2圖，於， 用者啟動該電腦平台10來yy"彳’母當使 開機事件⑽時)，其即可致使原發出- 回應地讀取該電腦平台10當前：之所·::模組m 置41、42、“ w h 我上之所有的周邊裝 3、44中的組態唯讀記憶體51、52、53、54 斤为別儲放之原始組態資料；並接著 算輕細1 ? n / 莉4订日可間數碼量計 Γ 置41、42、43、44的原始組態資 1個二=:ΤΓ媽量計算程序，藉此而計算出各 執行am. 、44的原始組態資料於初始化時的 執行時、 15杈、'且130接著即可依據該 == 計算模組120所求得的計算結果來首先為 該些=置41、42、43、44定出_最優化之處理順先序為 於此貫施例中’由於周邊裝置{PCI(1) :)’=4)}41、42、43、44轉雇原始組態資料 私碼里勿別為64ΚΒ、64ΚΒ、32Κβ、和2彻，但盆初 始化時的執行時間數碼量僅分別為6KB、32ΚΒ、32Κβ、 和16KB’因此其最優化之處理順序即被訂定為 pci(1>pci⑷4Ρα(2)4Ρα(3)。 《接著組態資料影射模組140可依據該處理順序訂定模 ^ 斤°丁疋之表優化之處理順序來依序將各個周邊裝置 2 43 44的原始組態資料影射至該影射式隨機存取 ^憶體3〇 ’令各個周邊裝置41、42、43、44的原始組態 貝料可於该影射式隨機存取記憶體3〇中被處理而令各個 周邊扁置41、42、43、44完成初始化程序。 19026 15 1312465 總而言之，本發明提供了—種電腦周邊裝置組 =化循序處理方法及系統，其可搭載至—電腦平台，、用 卢電腦平台提供—電腦周邊裝置組態資料最優化循序 =理功能，·且其特點在於預先對該電腦平台麟接之所有 二周邊裝置中的組態唯讀記憶體所儲放的原始組態資料執 仃-執行時間數碼量計算程序，藉以計算出各個周邊裝置 、、原七組態^料於初始化過程中的執行時間數碼量，並據 =定出-最優化之處理順序來將各個周邊裝置的原始組^ 貧料於實際進行初始化程序時暫存至影射式隨機存取記憶 體。相較於先前技術，此特點可讓電腦平台同時支援數目 更多的周邊裝置，並可讓影射式隨機存取記憶體之儲存介 間的利用更為具有彈性及有效率。本發明因此料前技ς 具有更佳之進步性及實用性。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容的範圍。本發明之實質技術内容< 係廣義地定義於下述之申請專利範圍中。若任何他人所完 成之技術實體或方法與下述之申請專利範圍所定義者為= 全相同、或是為一種等效之變更，均將被視為涵蓋於本發 明之申請專利範圍之中。 χ 【圖式簡單說明】 第1圖為一應用示意圖’用以顯示本發明之電腦周邊 裝置組態資料最優化循序處理系統搭載至一電腦平台的應、 用方式； σ心 弟2圖為一糸統架構示意圖’用以顯示本發明之電腦 19026 16 1312465 周邊裝置組態資料最優化循序處理系統的物件導向元件模 型的基本架構。 【主要元件符號說明】 ίο 電腦平台 20 中央處理單元（CPU) 30 影射式隨機存取記憶體（Shadow RAM) 40 周邊連接介面（PCI) 41 第一周邊裝置 *42帛二周邊裝置 43 第三周邊裝置 44 第四周邊裝置 45 VGA視訊控制卡 51 組態唯讀記憶體（OPROM) 52 組態唯讀記憶體（OPROM) 53 組態唯讀記憶體（OPROM) φ54 組態唯讀記憶體（OPROM) 100 本發明之電腦周邊裝置組態資料最優化循序處理系統 110 原始組態資料讀取模組 120 執行時間數碼量計算模組 130 處理順序訂定模組 140 組態資料影射模組 201 開機事件 17 19026Peripheral device processing sequence Original configuration data Digital quantity Actual execution digital amount Shadow RAM Remaining space order 1: PCI(2) 64KB 32KB 96 - 32 = 64KB (>32KB) Order 2 : PCI(3) 32KB 32KB 64 - 32 = 32KB (>24KB) Sequence 3: PCI(4) 24KB 16KB 32 - 16 = 16KB (< 64 KB) Sequence 4: PCI(l) 64KB XX As shown in the above table, when PCI 3 in sequence (4) When processed, the available storage space for the mapped random access memory is only 16KB, so it will not be enough to load the 64KB original configuration data of the PCI (1) of the sequence 4. 8 19026 1312465 SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a system for optimizing the configuration data of a computer peripheral device, which can make a fixed capacity mapping The random access memory can simultaneously support a larger number of peripheral devices than the prior art. Blowing, another object of the invention is to provide a computer peripheral device configuration lean = optimal sequential processing method and system, which can make the utilization of the storage space of the shadow random access memory more flexible and efficient. The computer peripheral device configuration data optimization step-by-step processing method 2 and the system money meter of the invention are applied to the redundancy-computer platform, and the computer flat=has a peripheral connection interface to connect to a plurality of peripheral cracks, for example The peripheral connection interface is used to provide a peripheral vibration=beauty optimization sequence processing function for the computer platform, thereby enabling more efficient access to the memory during the initial process. Body (ShadowRAM) and configuration data stored in accordance with the ^ shot. The configuration of the command is only the memory ((10) 〇 M) method to the peripheral device configuration data optimization step-by-step processing Fangan 22: boot event and read the current configuration data of the computer platform; (7) The original data stored in the read memory is executed separately—execution of 3 士<the original configuration of each peripheral device, the PC:=: quantity calculation program of each peripheral device, thereby calculating the amount; (3) 掳 initialization The second two = pure time execution time digital digital quantity for the peripheral devices 19026 9 1312465 - the starting group, the data in the initialization process, the execution time digital quantity, and according to the definition: out: optimization processing The original configuration data of each peripheral device is sequentially stored in the image random access memory when the initialization process is performed continuously. Compared with the prior art, this feature allows the computer platform to support a larger number of peripheral devices at the same time, and makes the use of the storage space of the mapped random access memory more flexible and efficient. [Embodiment] The embodiment of the computer peripheral device configuration data optimization sequence processing method and system of the present invention is disclosed in detail in the following drawings. Fig. 1 is a view showing the application of the configuration data of the peripheral device of the present invention to optimize the sequential processing system (e.g., the block indicated by reference numeral 100). As shown in the figure, the computer peripheral device configuration data optimization sequential processing system 100 of the present invention is applied to a computer platform in a practical application, for example, a desktop type PC, a notebook computer, or an internet feed. The server platform 10, and the computer platform 10 must be configured with at least a central processing unit (CentralPn>eesing (4) port ♦ cpupo, - mapping random access memory (Shad〇wRAM, and RAM = Random_Access Mem〇ry) 3〇, And a specific type of peripheral connection interface 40; wherein the peripheral connection interface 4 is, for example, a (Pedphera! Component Interc〇ectect) type of peripheral connection interface 40, which can be used to lap to one or more peripheral devices (first In the example shown in the figure, for example, it is connected to four peripheral devices 41, 42, 43 and a VGA video control card 45, but in practical applications, the number of peripheral devices that can be overlapped is Vision-shot random access memory t and each of the laps on the periphery of the oscillating 41, 42, 43, 4: = π 19026 1312465 built a configuration read-only memory (Option ROM, or simplified For OPROM, where ROM = Read-On Ly Memory) 51, 52, 53, 54 for pre-reserving a set of configuration data related to the booting of the peripheral devices 41, 42, 43, 44 to which they belong (hereinafter referred to as "Original Configuration Data";) In actual operation, the computer peripheral device configuration data optimization sequential processing system 100 of the present invention can provide a computer peripheral for all peripheral devices 4, 42, 43, 44 of the computer platform 10 The device configuration data optimizes the sequential processing function, thereby enabling the computer platform 1 to more effectively exchange data between the central processing unit 20 and each peripheral device 4, 42, 43, 44, and The user can install a greater number of peripheral devices to the computer platform 10. As shown in FIG. 2, the computer peripheral device configuration data of the present invention optimizes the object-oriented component of the sequential processing system 100. The basic architecture of the model) includes at least: (A) - the original configuration data reading module 110; (B) - the execution time digital quantity calculation module 120; (C) a processing sequence setting module 130; D) - configuration data shadow The module 140. In a specific implementation, the computer peripheral device configuration data of the present invention is optimal—the sequential processing system 100 can be implemented entirely by a computer program, and the computer program is, for example, an add-on module. The method is integrated into the BIOS (Basic Input/Output System) of the computer platform 10 to be input into the system or the operating system, and is executed by the central processing unit 20 of the computer platform 10 to provide the required computer peripheral device configuration. Data optimization step-by-step processing. In the following, the computer peripheral device configuration of the present invention is first described separately. 12 19026 1312465 1 Optimized sequence processing "The individual attributes of the constituent modules 110, 120, 30, 14〇 in (10) and the reading of the function configuration data are respectively read. The module 110 can be read back to the computer platform 10 == side devices 41, 42, 43, 44 in the computer platform (7) on the second machine event 2G1 (that is, the user starts the computer platform 开机-boot program) Group _,: 54 original configuration data stored separately. Material Center: Temple: 'Digital quantity calculation module 120 can take the above-mentioned original configuration 4 2 to take the core 1 and 110 read each m Peripheral devices 41, 42, 43 sequence group "division line - execution time digital calculation process ^ and leaves different PCI peripheral devices 41, 42, 43, 44, and the heart's execution time (runtime) The digital quantity, that is, the digital quantity when it is actually executed in #αα== the actual configuration date of the machine week I", 44 the original configuration data in the initialization process, the material The amount is usually smaller than the original original configuration, and the digital quantity of the original configuration data is available. Only 2 〇 Γ 剩下 实际 实际 实际 石 石 石 石 石 石 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 13 13 13 13 13 13 13 13 13 The different results are firstly optimized for the peripheral devices 4: the order of processing - the worry processing. In the specific implementation, the surrounding shock is the 4th = start: when: the execution time is the least amount of mother , and so on. 1:=里: The number of peripheral devices is the second priority. If there is one or more peripheral devices, when the digital quantity is equal between 19026 13 1312465, the digital quantity of the original configuration data is used. The larger one is preferred; however, if the digital configuration of the original configuration data of these peripheral devices is also equal, for example, the installation order is preferred over the former. For example, suppose the peripheral device {PCI(l), PCI(2) ), PCI(3), PCI(4)} The digital quantities of OPROM original configuration data of 41, 42, 43, and 44 are 64KB, 64KB, 32KB, and 24KB, respectively, but the digital execution time at initialization is only Requires 6KB, 32KB, 32KB, and 16KB; then the optimal processing order will be set to PCI (1>PCI(4)-> PCI(2)-PCI(3). The configuration data mapping module 140 can sequentially set the peripheral devices 41, 42, 43 according to the processing sequence specified by the module 130. The original configuration data of 44 is mapped (i.e., copied) to the in-line random access memory 30, so that the original configuration data of each peripheral device 41, 42, 43, 44 is available in the in-line random access memory 30. The middle is processed to cause the peripheral devices 41, 42, 43, 44 to complete the initialization process. In the following, an application example will be used to explain the operation mode of the computer peripheral mounting configuration data optimization sequential processing system 1 of the present invention in practical applications. In this application example, it is assumed that the capacity of the mapped random access memory 30 of the computer platform is only 128 KB, and the PCI peripheral connection interface 40 is pre-lapped with a VGA video control card 45 with a original configuration data of 32 KB. Then the user connects another four peripheral devices 41, 42, 43, 44, and the digital quantities of the original configuration data stored in the configuration read-only memory 5 1 , 52 , 53 , 54 are respectively It is 64 KB, 64 KB, 32 KB, and 24 KB, but the digital quantities when they are actually executed during the initialization process are only 6 KB, 32 KB, 32 KB, and 16 KB, respectively. 14 19026 1312465 Please also refer to the i-figure and the second diagram, in which the user activates the computer platform 10 to yy"彳's mother to make the boot event (10)), which can cause the original to send out - responsively read the computer Platform 10 Current: Where::: Module m is set to 41, 42, "Wh, all the peripheral devices in my 3, 44 configuration read-only memory 51, 52, 53, 54 kg for storage The original configuration data; and then calculate the light and thin 1 n / Li 4 set the date between the digital meter Γ set the original configuration of 41, 42, 43, 44 1 = 2: the amount of calculation program for the mother And the execution time of each original configuration data of each execution am. 44 is calculated, 15杈, 'and 130, and then the calculation result obtained by the calculation module 120 can be firstly determined according to the == Set 41, 42, 43, and 44 to determine the optimal processing order for this example. In this example, 'because peripheral devices {PCI(1):)'=4)}41, 42, 43, 44 The original configuration data private code should not be 64ΚΒ, 64ΚΒ, 32Κβ, and 2, but the implementation time of the basin initialization is only 6KB, 32ΚΒ, 32Κβ, and 16KB' respectively. The processing sequence is set to pci(1>pci(4)4Ρα(2)4Ρα(3). The configuration data mapping module 140 can then determine the processing order of the table optimization according to the processing sequence. The original configuration data of each peripheral device 2 43 44 is sequentially mapped to the mapping random access memory 3', so that the original configuration of each peripheral device 41, 42, 43, 44 can be used in the mapping The random access memory 3 is processed to complete the initialization process for each of the peripheral flats 41, 42, 43, 44. 19026 15 1312465 In summary, the present invention provides a computer peripheral device group=chemical sequential processing method and system, It can be carried to the computer platform, and provided by the Lu computer platform - the computer peripheral device configuration data is optimized for the sequence = rational function, and its characteristic is that the configuration of all the two peripheral devices connected to the computer platform in advance is only Read the original configuration data stored in the memory - the execution time digital quantity calculation program, in order to calculate the execution time digital quantity of each peripheral device, the original seven configuration materials in the initialization process, and determine according to = -most Optimized processing sequence to temporarily store the original group of each peripheral device to the in-line random access memory when actually performing the initialization process. Compared with the prior art, this feature allows the computer platform to simultaneously support a larger number of The peripheral device can make the utilization of the storage medium of the in-line random access memory more flexible and efficient. Therefore, the present invention has better advancement and practicability. The above description is only the present invention. The preferred embodiments are not intended to limit the scope of the technical content of the invention. The technical contents of the present invention are broadly defined in the following claims. If any other person's technical entity or method is defined as the same as or as an equivalent change to the scope of the patent application below, it is considered to be included in the scope of the patent application of the present invention. χ [Simple description of the drawing] Fig. 1 is an application schematic diagram for displaying the configuration method of the computer peripheral device configuration data optimization program of the present invention to be applied to a computer platform; σ心弟2 is a picture Schematic diagram of the structure of the object-oriented component model for optimizing the sequential processing system of the computer 19026 16 1312465 peripheral device configuration data of the present invention. [Main component symbol description] ίο Computer platform 20 Central processing unit (CPU) 30 Shadow random access memory (Shadow RAM) 40 Peripheral connection interface (PCI) 41 First peripheral device * 42 2 Peripheral device 43 Third periphery Device 44 Fourth Peripheral Device 45 VGA Video Control Card 51 Configuration Read Only Memory (OPROM) 52 Configuration Read Only Memory (OPROM) 53 Configuration Read Only Memory (OPROM) φ54 Configuration Read Only Memory (OPROM) 100 computer peripheral device configuration data optimization sequential processing system 110 original configuration data reading module 120 execution time digital quantity calculation module 130 processing sequence setting module 140 configuration data mapping module 201 boot event 17 19026