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九、發明說明： 【發明所屬之技術領域】 , 本發明係關於一種 SPI(Serial Peripheral Interface，串 列週邊介面）設備通訊電路。 【先前技術】 在電腦系統中，SPI係一種允許在兩種設備（一種稱主 設備，另一種稱從設備）之間進行串列資料交換之介面。SPI 最常應用於電腦系統之CPU(Central processing unit，中央 處理器）與週邊晶片之間之通訊電路系統中，例如電能計量 晶片（Energy Metering 1C)就是透過SPI傳輸電壓、電流等 資料給CPU的。 請參閱第一圖，當CPU10’（主設備）需要透過SPI與複 數週邊晶片（從設備，此處以四個週邊晶片20’舉例說明） 進行通訊時，通常之做法為：先將每一週邊晶片20,之SPI 分別與SB匯流排30’相連’然後再將SPI匯流排30’與 CPU10’之SPI匯流排控制單元12f相連，而CPU10’之晶片 選通單元If與每一週邊晶片20’之選通端相連，用以控制 該等週邊晶片20’以使需要與CPU10’通訊之週邊晶片20’ 與CPU1CT進行通訊，CPUUV之晶片選通單元14’一般係使 用複數 CPU10’之 GPIO(General purpose input/output，通用 輸入輸出）引腳，所使用之GPI0引腳之數量與該等週邊 晶片20’之數量相同，即為四個（圖中用A’、B，、C，、D▼表 示)，每一 GPI0引腳分別控制一週邊晶片2CV。 惟，該種SPI設備通訊電路之SPI匯流排30,由於並聯 了複數週邊晶片20’，則SPI匯流排301需同時驅動該等週 邊晶片20’，這就有可能會超過SPI匯流排30’之驅動能力， 使CPU10’與週邊晶片20f之間之通訊受到影響。而且，該 等週邊晶片之間相互並聯，很有可能在工作時造成彼 此之間相互干擾，同樣影響了與CPU10’之間之通訊。當該 等週邊晶片20’數量很多時，就需要應用較多之GPI0引IX. Description of the Invention: [Technical Field] The present invention relates to a SPI (Serial Peripheral Interface) device communication circuit. [Prior Art] In a computer system, SPI is an interface that allows serial data exchange between two devices (one called a master device and the other called a slave device). SPI is most commonly used in the communication circuit between the central processing unit (CPU) of the computer system and the peripheral chip. For example, the energy metering chip (Energy Metering 1C) transmits the voltage, current and other data to the CPU through the SPI. . Referring to the first figure, when the CPU 10' (master device) needs to communicate with a plurality of peripheral chips (from the device, here exemplified by four peripheral chips 20') through the SPI, the usual method is: first, each peripheral chip 20, the SPI is respectively connected to the SB bus 30' and then the SPI bus 30' is connected to the SPI bus control unit 12f of the CPU 10', and the wafer gating unit If of the CPU 10' and each peripheral chip 20' The strobes are connected to control the peripheral chips 20' to communicate with the CPU 1CT of the peripheral chip 20' that needs to communicate with the CPU 10'. The chip strobe unit 14' of the CPUUV generally uses the GPIO of the plurality of CPUs 10' (General purpose) Input/output, general-purpose input/output) pin, the number of GPI0 pins used is the same as the number of the peripheral chips 20', that is, four (in the figure, A', B, C, D▼ ), each GPI0 pin controls a peripheral chip 2CV. However, in the SPI bus 30 of the SPI device communication circuit, since the plurality of peripheral chips 20' are connected in parallel, the SPI bus 301 needs to simultaneously drive the peripheral chips 20', which may exceed the SPI bus 30' The driving capability affects communication between the CPU 10' and the peripheral wafer 20f. Moreover, the peripheral wafers are connected in parallel with each other, which is likely to cause mutual interference with each other during operation, and also affects communication with the CPU 10'. When the number of the peripheral wafers 20' is large, it is necessary to apply more GPI0 leads.
1304534 腳，無疑浪費了 CPU10,有限之GPIO引腳資源，可能會使 電腦系統之其它部件由於無可利用之GPIO引腳資源而使 其設計變得複雜，從而造成電腦系統設計成本提高。 因是，實有必要對習知之SPI設備通訊電路進行改 良’以消除上述缺失。 【發明内容】 鑒於以上内容，有必要提供一種SPI設備通訊電路， 以消除SH匯流排驅動能力不足之問題、減小從設備之間 相互干擾以及減少晶片選通單元之引腳使用數量。 • 一種串列週邊介面（SPI)設備通訊電路，包括一主設 備、複數從設備及一 SH匯流排，該等從設備透過該spi 匯流排與該主設備之間進行通訊，該等從設備與該SPI匯 流排之間還連接一多工器，該主設備與該多工器之選通端 相連，該主設備透過該多工器來控制該等從設備之選通， 以使需要之從設備與該主設備之間進行通訊。 相較於習知技術，在該等從設備與該SH匯流排之間 連接該多工器，使該等從設備與SPI匯流排完全斷開，spj 匯流排將不會出現驅動能力不足之情況。同時利用該多工 器同一時間只允許一從設備與主設備進行通訊，從而減小 ® 了該等從設備之間之相互干擾。而且應用該多工器亦減少 了晶片選通單元之引腳使用數量，一定程度上簡化了電腦 系統之設計，進而降低了設計成本。 【實施方式】 請參閱第二圖，本發明SPI設備通訊電路之較佳實施 方式包括一主設備（如電腦系統中之CPU10)、複數從設備 (如電腦系統中透過SPI與CPU10通訊之週邊晶片2〇)、SPI 匯流排30及一多工器40,這裡以四個週邊晶片2〇為例加 以說明。 . 該CPU10具有一 SPI匯流排控制單元12，用以接收 透過SPI匯流排30傳輸給CPU10之資料；該CPUl〇還具 6The 1304534 pin undoubtedly wastes CPU10, limited GPIO pin resources, which may complicate the design of other parts of the computer system due to the lack of available GPIO pin resources, resulting in increased computer system design costs. Therefore, it is necessary to improve the conventional SPI device communication circuit to eliminate the above-mentioned missing. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide an SPI device communication circuit to eliminate the problem of insufficient SH bus drive capability, reduce mutual interference between devices, and reduce the number of pins used by the chip gating unit. • A serial peripheral interface (SPI) device communication circuit comprising a master device, a plurality of slave devices, and a SH bus bar, the slave devices communicating with the master device through the spi bus bar, the slave devices and A multiplexer is further connected between the SPI busbars, and the master device is connected to the strobe terminal of the multiplexer, and the master device controls the strobes of the slave devices through the multiplexer, so as to The device communicates with the master device. Compared with the prior art, the multiplexer is connected between the slave devices and the SH bus bar, so that the slave devices are completely disconnected from the SPI bus bar, and the spj bus bar will not have insufficient driving capability. . At the same time, the multiplexer allows only one slave device to communicate with the master device at the same time, thereby reducing the mutual interference between the slave devices. Moreover, the application of the multiplexer also reduces the number of pins used in the chip gating unit, which simplifies the design of the computer system to a certain extent, thereby reducing the design cost. [Embodiment] Referring to the second figure, a preferred embodiment of the communication circuit of the SPI device of the present invention includes a master device (such as the CPU 10 in the computer system) and a plurality of slave devices (such as a peripheral chip that communicates with the CPU 10 through the SPI in the computer system). 2 〇), SPI bus 30 and a multiplexer 40, here are four peripheral wafers 2 〇 as an example to illustrate. The CPU 10 has an SPI bus control unit 12 for receiving data transmitted to the CPU 10 through the SPI bus 30; the CPU 10 has 6
1304534 .有一晶片選通單元14,用以控制該等週邊晶片20之選通， 4 以使需要之週邊晶片20與該CPU10之間進行通訊，該晶 ； 片選通單元14包括複數CPU10之GPIO引腳。 v 其中，每一週邊晶片20之SPI均與該多工器40之輸 入端相連，該多工器40之輸出端透過該SPI匯流排30與 該CPU10之SPI匯流排控制單元12相連，該CPU10之晶 片選通單元14與該多工器40之選通端相連。設週邊晶片 20之數量為m，所需之GPIO引腳數量為η，則m、η滿 足關係式： m ( m>2 ) • 由於該等週邊晶片20為四個，則該晶片選通單元14 利用之CPU10之GPIO引腳僅為兩個即可（圖中用A、B表 示），其中 Α=Β=0;Α=0 且 且 B=0 及 A=B=1(0 代 表低電位，1代表高電位）為選通訊號，上述四種選通訊號 分別用以控制該多工器40選通對應一週邊晶片20與該 CPU10之間進行通訊。 工作時，當某一週邊晶片20需要與該CPU10進行通 訊時，該CPU10首先透過晶片選通單元14(即GPIO引腳 A、B)發出與上述週邊晶片20對應之選通訊號給該多工器 φ 40，這時多工器40將控制該被選通之週邊晶片20與該 CPU10之間進行通訊，而其它週邊晶片20將不會與該 CPU10之間進行通訊。同理，當其它某一週邊晶片20需 要與該CPU10進行通訊時，只要透過CPU10之晶片選通 單元14發出與其對應之選通訊號給該多工器40即可。 由於該等週邊晶片20係透過多工器40後再經過SPI 匯流排30與CPU10進行通訊的，該SPI匯流排30將不會 出現驅動能力不足之情況。而且利用多工器40同一時間 只允許一週邊晶片20與CPU10進行通訊，那麼該等週邊 晶片20之間就不會造成相互干擾。同時，由於利用了多 工器40之選通功能，僅需要較少之GPIO引腳就可控制多 7 1304534 .工器40對該等週邊晶片20之選通控制，如果週邊晶片20 < 之數量愈多這種優勢亦就愈明顯（如該等週邊晶片20之數 ； 量為八個時，僅需使用三個GPIO引腳即可滿足要求），大 ’ 大減少了使用GPIO引腳之數量，一定程度上簡化了電腦 系統之設計，進而降低了設計成本。 以上實施方式僅以CPU10及透過SPI與CPU10通訊 之週邊晶片20來舉例說明本發明SPI設備通訊電路，其它 類似應用SPI設備之間之通訊電路均可按照此方式設計， 這裡就不一 一詳細說明。 綜上所述，本發明符合發明專利要件，爰依法提出專 ®利申請。惟，以上所述者僅為本發明之較佳實施方式，舉 凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 第一圖係習知之SPI設備通訊電路之原理框圖。 第二圖係本發明SPI設備通訊電路之較佳實施方式之 原理框圖。 【主要元件符號說明】 [習知] CPU 10? SH匯流排控制單元12’ SPI匯流排 30’ [本發明] CPU 10 SH匯流排控制單元12 SH匯流排 30 晶片選通單元14’ 週邊晶片 20’ GPIO 引腳 A’、B’、C’、D’ 晶片選通早元14 週邊晶片 201304534. There is a chip gating unit 14 for controlling the gating of the peripheral chips 20, 4 to enable communication between the peripheral chip 20 and the CPU 10, and the chip gating unit 14 includes the GPIO of the plurality of CPUs 10. Pin. The SPI of each peripheral chip 20 is connected to the input end of the multiplexer 40. The output end of the multiplexer 40 is connected to the SPI bus bar control unit 12 of the CPU 10 through the SPI bus 30, the CPU 10 The wafer gating unit 14 is connected to the strobe terminal of the multiplexer 40. Let the number of peripheral wafers 20 be m, and the number of required GPIO pins is η, then m, η satisfy the relationship: m (m> 2) • Since the peripheral wafers 20 are four, the wafer gating unit 14 The CPU10 has only two GPIO pins (represented by A and B in the figure), where Α=Β=0; Α=0 and B=0 and A=B=1 (0 represents low potential) , 1 represents a high potential) is a selection communication number, and the above four selection communication numbers are respectively used to control the communication between the multiplexer 40 strobe corresponding to a peripheral wafer 20 and the CPU 10. In operation, when a peripheral chip 20 needs to communicate with the CPU 10, the CPU 10 first issues a selected communication number corresponding to the peripheral chip 20 to the multiplex through the chip strobe unit 14 (ie, GPIO pins A, B). The φ 40, at which time the multiplexer 40 will control the communication between the gated peripheral wafer 20 and the CPU 10, while the other peripheral wafers 20 will not communicate with the CPU 10. Similarly, when some other peripheral chip 20 needs to communicate with the CPU 10, the wafer strobe unit 14 of the CPU 10 sends a corresponding communication number to the multiplexer 40. Since the peripheral chips 20 are transmitted through the multiplexer 40 and then communicated with the CPU 10 via the SPI bus 30, the SPI bus 30 will not exhibit insufficient driving capability. Moreover, by using the multiplexer 40 to allow only one peripheral wafer 20 to communicate with the CPU 10 at the same time, the peripheral wafers 20 do not interfere with each other. At the same time, since the strobe function of the multiplexer 40 is utilized, only a small number of GPIO pins are needed to control the multi-channel 1 1304534. The strobe control of the peripheral wafers 20 of the workpiece 40, if the peripheral wafer 20 < The greater the number, the more obvious this advantage (such as the number of peripheral chips 20; when the amount is eight, only three GPIO pins are required to meet the requirements), the large 'large reduction of the use of GPIO pins The quantity simplifies the design of the computer system to a certain extent, thereby reducing the design cost. In the above embodiment, only the CPU 10 and the peripheral chip 20 communicating with the CPU 10 through the SPI are used to illustrate the communication circuit of the SPI device of the present invention. The communication circuits between other similar application SPI devices can be designed in this manner, and the details are not described here. . In summary, the present invention complies with the requirements of the invention patent, and the application for the exclusive application is made according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims. [Simple description of the diagram] The first diagram is a block diagram of the conventional SPI device communication circuit. The second figure is a block diagram of a preferred embodiment of the SPI device communication circuit of the present invention. [Main component symbol description] [Generally known] CPU 10? SH bus bar control unit 12' SPI bus bar 30' [Invention] CPU 10 SH bus bar control unit 12 SH bus bar 30 Chip gating unit 14' Peripheral wafer 20 'GPIO pins A', B', C', D' chip strobe early 14 peripheral wafer 20
GPIO 引腳 A、B 8 40 1304534 多工器GPIO pin A, B 8 40 1304534 multiplexer