TWI280603B - Manufacturing system of semiconductor device and manufacturing method of semiconductor device - Google Patents

Manufacturing system of semiconductor device and manufacturing method of semiconductor device Download PDF

Info

Publication number
TWI280603B
TWI280603B TW093126536A TW93126536A TWI280603B TW I280603 B TWI280603 B TW I280603B TW 093126536 A TW093126536 A TW 093126536A TW 93126536 A TW93126536 A TW 93126536A TW I280603 B TWI280603 B TW I280603B
Authority
TW
Taiwan
Prior art keywords
processing
quality
inspection
information
semiconductor
Prior art date
Application number
TW093126536A
Other languages
Chinese (zh)
Other versions
TW200512794A (en
Inventor
Yukihiro Ushiku
Hidenori Kakinuma
Tatsuo Akiyama
Shunji Shuto
Masahiro Abe
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of TW200512794A publication Critical patent/TW200512794A/en
Application granted granted Critical
Publication of TWI280603B publication Critical patent/TWI280603B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/41875—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by quality surveillance of production
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67276—Production flow monitoring, e.g. for increasing throughput
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Automation & Control Theory (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • General Factory Administration (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The object of the present invention is to properly manage a maintenance interval of a processor and to shorten a manufacturing process period of a semiconductor device. The solution of the present invention comprises a processor 14 for executing process treatment using a semiconductor substrate 17, a self-diagnostic system 11a for receiving device information from the processor 14 and performing self-management of the processor 14, an inspection device 19 for inspecting the result of the process treatment, and a computer 11 that judges whether or not to automatically restore the processor 14 based on the inspection result, and maintains a parameter of the self-diagnostic system 11a when the judgment result is valid and changes a parameter of the self-diagnostic system 11a when the judgment result is invalid.

Description

1280603 (1) 九、發明說明 【發明所屬之技術領域】 本發明係關於半導體裝置的製造系統及半導體裝置的 製造方法，特別是關於製造裝置之控制方法、及使用彼等 之半導體裝置之製造工程的模擬方法及模擬裝置。 【先前技術】 習知上，藉由半導體製造裝置而反覆進行基板段差形 成、井形成、絕緣、電晶體形成、位元線形成、電容器形 成、配線形成，以製造dram(動態隨機存取記憶體）等之 半導體裝置。這·些半導體製造製程係適當地組合：微影處 理、蝕刻處理、熱處理（氧化、退火、擴散）、離子植入 處理、薄膜形成處理（CVD、濺鍍、蒸鍍）、洗淨處理 (光阻去除、藉由溶液之洗淨）、檢查處理等而構成。 另外，一般雖在維持控制種種之處理室之環境下，將 基板搬入搬出處理室而進行工程處理，但是，也存在有檢 查處理後之基板，將所獲得之測量檢查資料傳送給中央控 制系統，進行基板或處理室之履歷管理或記錄，進行各處 理室或製造裝置之自我診斷，以輸出適切之指示之系統 (參考專利文獻1 )。 習知之半導體裝置之製造裝置係具備：實行熱製程之 氧化爐，及控制此氧化爐之氧化爐控制器，及連接於氧化 爐及氧化爐控制器，實行製程控制之氧化膜厚控制器。 此氧化膜厚控制器係具有：具氧化膜厚計算功能之氧 -5- 1280603 (2) 化膜厚計算部’及具計算膜厚判定功能之計算膜 部，在進行利用熱化學反應之特定的半導體製造製 依據預先所設定的製程實行起始設定’開始半導體 程，以特定的時間間隔測量及解析熱化學反應正進 特定系統之環境狀態與其之變化’將此解析結果反 導體製造製程（參考專利文獻2 )。 但是，在此種習知的半導體裝置之製造裝置中 可以實行個個之製程處理裝置的自我診斷或製程模 進行半導體基板上之氧化膜厚度或配線寬度或不純 濃度之控制，但是，以經過複數之製程處理裝置所 晶圓的探針測試而實際測量之半導體裝置的產品率 擬所獲得之產品率之間會產生差異。因此，需要調 體裝置之生產計畫與顧客之訂購個數，頻繁重複藉 之繁雜的追加生產計畫，晶圓之檢查工程增加，半 置的製造工程期間變長。 [專利文獻1]國際公開 W096/25 760號公報 頁第25行至第37頁第2行） [專利文獻2]日本專利特開2002-2993 3 6號公 11欄，第5行至第48行，第1圖） 【發明內容】 本發明在於提供：適切地管理各製程處理裝置 間隔’延長各製程處理裝置之稼動時間，也削減在 體製造製程結束階段所實施之晶圓檢查工程，可使 厚判定 程時， 製造製 行著之 饋給半 ，即使 擬，以 物擴散 完成之 與以模 整半導 由人手 導體裝 (第36 報（第 之維護 各半導 半導體 -6 - 1280603 (3) 裝置之製造工程期間縮短之半導體裝置之製造系統及半導 體裝置之製造方法。 本發明之一形態，其要旨爲一種具備：實行半導體裝 置之製程處理之處理裝置，及控制處理裝置之處理控制裝 置，及令半導體裝置之製程處理進行，監視處理裝置之狀 態，積分處理裝置的內部資訊，實行製程處理之模擬，藉 由製程處理以推測半導體基板之處理的進行之即時模擬器 之半導體裝置之製造系統。 本發明之一形態，其要旨爲具備：實行使用半導體基 板之製程處理之處理裝置，及由處理裝置收訊裝置資訊， 算出製程處理之推測品質値之自我診斷系統，及檢查製程 處理的結果之檢查裝置，及比較檢查結果與推測品質値， 在判定推測品質値爲有效時，維持自我診斷系統之參數， 在判定推測品質値無效時，變更自我診斷系統之參數之比 較器之半導體裝置之製造系統。 本發明之一形態，其要旨爲具備：實行使用半導體基 板之製程處理之處理裝置，及由處理裝置收訊裝置資訊， 進行處理裝置之自我管理之自我診斷系統，及檢查製程處 理的結果之檢查裝置，及依據檢查結果，判定是否自動修 復處理裝置，在判定結果爲有效判定時，維持自我診斷系 統之參數，在判定結果爲無效判定時，變更自我診斷系統 之參數之比較器之半導體裝置之製造系統。 本發明之一形態，其要旨爲具備：實行半導體裝置之 製程處理之處理裝置，及依據自我診斷參數以診斷處理裝 1280603 (4) 置之自我診斷裝置，及檢查製程處理之檢查裝置，及連接 於自我診斷裝置及檢查裝置，在半導體基板之檢查結果爲 有效時，維持自我診斷參數，在檢查結果爲無效時，變更 自我診斷參數之比較器之半導體裝置之製造系統。 本發明之一形態，其要旨爲具備：實行半導體基板之 製程處理之處理裝置，及取得處理裝置之裝置資訊，推測 半導體基板之品質之品質推測部，及進行經過製程處理之 半導體基板的品質檢查之品質檢查裝置，及比較品質推測 部之推測品質資料與品質檢查裝置所實際測量之品質管理 資訊之比較器之半導體裝置之製造系統。 本發明之一形態，其要旨爲具備：實行半導體基板之 製程處理之處理裝置，及取得處理裝置之裝置資訊，輸出 半導體基板之推測品質資訊之品質推測部，及輸出經過處 理之半導體基板之品質資訊之品質檢查裝置，及實行推測 品質資訊與品質資訊之品質相關處理之推測品質管理部， 及依據由推測品質管理部所輸出的推測品質資訊，實行模 擬，預測半導體裝置之產品率之產品率預測裝置，及經過 處理裝置之處理，至少檢查完成晶圓工程之半導體裝置之 產品率之產品率檢查裝置；實行比較產品率預測裝置之產 品率與產品率檢查裝置之產品率之產品率相關處理之半導 體裝置之製造系統。 本發明之一形態，其要旨爲具備：實行半導體基板之 製程處理之處理裝置，及輸出經過處理之半導體基板之品 質資訊之品質檢查裝置，及依據來自品質檢查裝置之品質 -8- 1280603 (5) 資訊，實行模擬，預測半導體裝置之產品率之產品率預測 裝置，及經過處理裝置之處理，至少檢查完成晶圓工程之 半導體裝置的產品率之產品率檢查裝置；實行比較產品率 預測裝置之產品率與產品率檢查裝置之產品率之產品率相 關處理之半導體裝置之製造系統。 本.發明之一形態，其要旨爲具備：實行半導體基板之 製程處理之處理裝置，及監視處理裝置之裝置資訊，輸出 半導體基板之推測品質資訊之品質推測部，及輸出經過處 理之半導體基板之品質資訊之品質檢查裝置，及實行推測 品質資訊與品質資訊之品質相關處理之推測品質管理部， 及實行基於來自品質檢查裝置之品質資訊之模擬，預測半 導體裝置之產品率之第1產品率預測裝置，及依據來自推 測品質管理部之推測品質資訊，實行與第1產品率預測裝 置之模擬不同之另外的模擬，預測半導體裝置之產品率之 第2產品率預測裝置，及經過半導體製造製程，至少檢查 完成晶圓工程之半導體裝置之產品率之產品率檢查裝置； 實行比較第1產品率預測裝置之產品率與產品率檢查裝置 之產品率之第1產品率相關處理，及比較第2產品率預測 裝置之產品率與產品率檢查裝置之產品率之第2產品率相 關處理之半導體裝置之製造系統。 本發明之一形態，其要旨爲具備：實行半導體基板之 製程處理之處理裝置，及比較檢測處理裝置之裝置資訊， 由檢測値中抽出處理之非控制値，予以特徵量化之特徵 量，及藉由範圍分類將固有之缺陷影像予以數値化，預先 -9- 1280603 (6) 加以記憶之相關表內之特徵量，在判定該特徵量化之特徵 量與該相關表內之特徵量爲相同程度化値之階段，中斷處 理，將半導體基板當成不良批次而加以報告之品質檢測部 之半導體裝置之製造系統。 本發明之一形態，其要旨爲具備：在具有與藉由範圍 分類將固有之缺陷影像予以數値化，預先加以記憶之相關 表內之特徵量無法相同程度化之新的特徵量的不良批次被 .檢測出時，依據該不良批次之半導體基板的製程履歷資 訊，抽出顯示該半導體基板之不良批次產生時之處理裝置 之狀態的裝置資訊，自動地將該裝置資訊反饋給品質推測 部之推測品質自動更新手段之半導體裝置之製造系統。 本發明之一形態，其要旨爲：藉由處理裝置，實行半 導體基板之製程處理，使半導體基板之製程處理進行，監 視處理裝置之狀態，積分處理裝置之內部資訊，實行製程 處理之模擬，藉由製程處理，以推測半導體基板之處理的 進行之半導體裝置之製造系統。 本發明可以提供：適切地管理各製程處理裝置之維護 間隔，延長各製程處理裝置之稼動時間，也削減在各半導 體製造製程結束階段所實施之晶圓檢查工程，可使半導體 裝置之製造工程期間縮短之半導體裝置之製造系統及半導 體裝置之製造方法。 【實施方式】 (第1實施形態） •10- 1280603 (7) 如第1圖所示般，關於本發明之第1實施形態之半導 體裝置之製造系統係具備：對於半導體基板之晶圓1 7或 者其表面之薄膜實行處理之處理裝置14，及作爲藉由設 備工程系統EES(以下，稱爲「EES」）以進行處理裝置14 之自我^理之自我診斷系統之電腦1 1 a，及經過處理之半 導體基板之晶圓1 7之藉由檢查裝置1 9的檢查結果，判定 是否自動修復處理裝置〗4，在判定結果爲有效判定（或 者適當）時，維持自我診斷系統之參數之係數（或者加以 微調整），在判定結果爲無效判定（或者不適當）時，作 爲變更启我診斷系統之參數（例如，增加檢查次數）之參 數調適裝置的電腦1 可以調整半導體製造製程階段之 .檢查頻度的系統。 此處’所謂「E E S」係由處理裝置1 4取得裝置資 訊，統計性地分析裝置資訊之資料，以判定處理裝置】4 之狀態爲正常或異常之系統。 E S S係在作爲自我診斷裝置系統之電腦丨丨a上實行， 即時取得處理晶圓1 7之處理裝置1 4的內部狀態。處理裝 置1 4的內部狀態可以推測故，所以也可以即時取得在內 部所處理之晶圓1 7的製程狀態。 作爲自我診斷系統之電腦1 1 a係可使處理裝置1 4實 行之製程的時間經過變化與晶圓1 7相對應而記憶在資料 庫 1 3 a。 即半導體裝置之製造系統1 〇係具備：控制此製造系 統整體之電腦1 1，及連接於電腦1 1，記憶關於半導體製 -11 - 1280603 (8) 造製程之資料處理演算法之記憶裝置1 2，及連接於電腦 1 1，記憶 APC(先進製程控制，以下，單單略記爲 「APC」）或 MES(製造執行系統，以下，單單略記爲 「Μ E S」）所使用之資料之主資料庫1 3，及處理作爲半導 體基板之晶圓1 7的處理裝置1 4，及檢查在此處理裝置1 4 所處理之晶圓17之檢查裝置19。 此處，所謂之「APC」係意指因應在處理裝置14所 處理之晶圓1 7的處吝容，電腦1 1變更半導體製造製程之 系統。以檢查裝置1 9檢查晶圓1 7之結果，在沒有達到期 待之品質的情形，則一面參照過去之製程條件，一面將處 .理裝置1 4之製程條件變更爲新的製程條件。另外，所謂 之「MES」係意指在以處理裝置14處理複數批次之晶圓 17時，電腦11實行半導體裝置之生產管理，將所選擇之 一個批次之晶圓1 7搬運於處理裝置1 4，令處理裝置1 4 實行處理，也令檢查裝置1 9實行檢查之系統。 圖示之處理裝置1 4爲了簡單化故，雖舉例顯示單單 一個，但是，由現在的LSI(大規模積體電路）之製造工程 可以容易理解般’半導體裝置之製造系統1 0 —般係設置 有10台以上之複數台的處理裝置14。而且，由複數之處 理裝置1 4藉由訊號線1 4 a而連接於電腦丨I a，可令實行 藉由EES之自我管理。另外，複數之處理裝置14可直接 或藉由電腦1 1 a而連接於電腦1丨，能過送訊處理裝置！ 4 之裝置資訊，電腦1 1依據收訊之裝置資訊，在APC、 MES之管理下，可統合性地管理半導體製造系統整體。 -12- 1280603 (9) 另外，處理裝置1 4可以對應加工處理半導體裝 各種處理裝置，例如，當然可以能應用在：實行薄膜 製程之薄膜形成處理裝置、不純物之擴散處理裝置、 CVD之薄膜堆積膜裝置、迴焊（熔化）PSG膜、 膜、BPSG膜（絕緣膜）等之加熱爐裝置、調整CVD 膜等之.密度量、矽化金屬膜（電極）厚度等之熱化學 處理裝置、堆積金屬配線層之濺鍍裝置或真空蒸鍍裝 進而電鍍之電鍍處理裝置、化學機械硏磨半導體基 CMP處理裝置、蝕刻半導體基板表面之乾式或濕式 處理裝置、微影處理相關之旋轉塗佈處理裝置、步進 之曝光處理裝置、將經過切割之小片狀的半導體裝置 極連接於導線架之焊線處理裝置等各種半導體製造製 處理裝置爲對象。 另外，本發明之半導體裝置之製造系統10不管 次式裝置或者葉片式裝置之任何一者都可以適用。關 後敘述之全部的實施形態，同樣地使用批次式裝置或 式裝置都沒有關係。 電腦1 1 a矽使製造製程資料記憶在內部的資 1 3 a ’逐次地更新與晶圓1 7的批次號碼有關之處理內 料或與晶圓17之製程履歷有關之處理內容資料，可 面對處理裝置1 4提供現在時間點（即時）之最好製 態’ 一面檢測處理2 1在處理裝置1 4的內部發生何事 於半導體製造製程反饋內部狀態。 例如’在處理裝置1 4爲具有真空處理系統之薄 置之 形成 藉由 BSG 氧化 反應 置、 板之 蝕刻 機等 之電 程之 是批 於之 葉片 料庫 容資 以一 程狀 ，對 膜形 -13- 1280603 (10) 成處理裝置、擴散處理裝置、薄膜堆積膜裝置般之處理室 的處理裝置之情形，則依據決定爐內複數處之溫度、感應 器溫度、處理室外壁複數處之溫度、表示處理室之真空度 之壓力、氣體之流量、控制氣體流量之閥門的開度等之諸 條件之各種參數，以實行半導體製造製程。 另外，在處理裝置1 4爲具有電漿處理系統之乾蝕刻 裝置、離子植入裝置般之電極的處理裝置之情形，在前述 之真空處理系統之各種參數以外，依據RF(射頻）之匹配 位置、RF電壓（進行波電壓、反射波電壓）、晶圓之位 置資訊之各種參數，以實行半導體製造製程。 進而，在處理裝置1 4爲大氣壓處理系統之濕蝕刻處 理裝置、旋轉塗佈處理裝置、步進機曝光處理裝置、焊線 處理裝置之情形，則依據處理時間或晶圓或晶片之位址資 訊之各種參數，以實行半導體製造製程。 進而，半導體裝置之製造系統10在處理裝置14使用 如薄膜形成處理裝置、擴散處理裝置、薄膜堆積膜裝置之 氣體或化學藥品之情形，則該氣體或化學藥品係藉由閘門 閥】6所供給，將供給之氣體或化學藥品之直接材料或由 容器之間接材料所成之直接材料間接材料1 5予以數値化 而作爲材料模型之資料記錄在主資料庫1 3而進行自我管 理。藉由此材料模型化，可以即時地判定處理2 2是否會 由氣體或化學藥品之類的材料對半導體製造製程造成影 響。 晶圓1 7係與處理裝置1 4連結1 8，在通過特定之處 -14 - 1280603 (11) 理工程時，藉由感測器/檢查裝置1 9，依據膜厚N G或圖 案缺陷之有無，進行晶圓1 7上之現象判定2 3。此檢查結 果係成爲晶圓1 7之以批次或片單位來管理之關鍵的資 訊，藉由電腦1 1而收集資訊，供應給即時監視器/ Q C之 判定處理2 4。 電腦11係由檢查裝置19及處理裝置14或電腦11a 取得品質資訊或裝置資訊或直接材料間接材料資訊，藉由 即時模擬處理裝置1 4之狀態或由此處理裝置1 4所搬出之 批次的晶圓1 7爲哪種品質（例如，膜厚），即使省略中 間處理工程之檢查，也可以充分掌握半導體裝置之品質。 另外，電腦1 1可以將品質資訊反饋給半導體製造製 程而做處理，或者對於下一工程以後之處理裝置（未圖示 •出）實行前饋處理，每處理複數之批次，則比較由檢查裝 置1 9側所送訊之品質資訊與由電腦1 1 a所送訊之推測品 質資訊，在電腦1 1上模擬半導體製造製程，可以提高品 質資訊之精確度。 進而，電腦1 1也管理在微影處理所使用之光罩20 (標度線）之設計資訊25，以即時監視器/ QC之判定處 理24在晶圓上發現特定之缺陷處的情形，也可以判定處 理光罩20是否設計不良。 如前述般，關於本發明之實施形態之半導體裝置之製 造系統1 〇係模型化處理裝置1 4、直接材料間接材料1 5、 晶圓17之製程，構成藉由電腦1 1之APC系統故，可以 實行即時之品質管理，可以實施TCAD(技術電腦輔助設 1280603 (12) 計）或 YMS (產品率管理系統）故，具有即使在結束最終工 程前之中間處理工程中，也可以預測最終之半導體裝置的 產品率之優點。以下，使用第1至第7實施形態，說明關 於本發明之實施形態之半導體裝置之製造系統1 0的特 徵。 第.2圖係說明關於本發明之第1實施形態之半導體裝 置之製造方法的模型流程圖。半導體裝置之製造系統3 0 之半導體製造製程順序爲，一面依序經過晶圓之批次投入 I程42、對於作爲半導體基板之晶圓或其之表面的薄 膜’實行藉由處理裝置之加工A處理之第1處理工程 43、實行藉由第1檢查裝置之線上qC處理之第丨檢查工 程44、進行藉由第2檢查裝置之表面圖案的缺陷檢查處 理之第2檢查工程45、對於晶圓或者其表面之薄膜，實 行藉由處理裝置之加工B處理之第2處理工程4 6、進而 省略圖示之第3處理工程、第4處理工程、第3檢查工程 等之複數的處理工程或檢查工程，直到以晶圓狀態所完成 之批次完成工程4 7。形成在此批次完成工程4 7之晶圓的 複數之半導體裝置係在D/S(晶片分類）處理工程48 (以 下，單單略記爲「D/S處理工程」）中，藉由產品率檢查 裝置之半導體裝置的產品率受到檢查。藉此D/S處理，晶 片之電氣特性被以探針檢查，而被區分爲良品或不良品， 可在不良品之晶片加上油墨之標記而加以辨識。 第1處理工程4 3係藉由批次投入工程4 2而將晶圓搬 入內部，依循事先設定之半導體製造製程順序，處理加工 -16- 1280603 (13) A。此加工A係可以適用薄膜處理、氧化處理、電黎處 理、濕式處理、C MP處理、焊接處理等種種之製程。 例如’在實行加工A之第1處理工程4 3爲薄膜形成 製程之情形’ 一面對晶圓施加氣體之注入、溫度管理、壓 力管理、RF電壓處理、氣體之排氣等之一連串的薄膜處 理，一面將處理裝置之氣體壓力、溫度、RF電壓、火花 之有無 '堆積物量等之裝置資訊4 3 a送訊給自我診斷系統 3卜 另外，在第1處理工程43爲CMP製程之情形，一面 監控硏磨劑之量、硏磨台之旋轉數、硏磨台之劣化狀態， 一面施以晶圓之硏磨處理，將對於處理裝置之硏磨劑的供 給、硏磨台之更換時期等之裝置資訊43a送訊給自我診斷 系統3 1。 此自我診斷系統3 1爲了即時而全數檢查晶圓，可以 複數配置在處理裝置之壓力檢測器、或溫度檢測器、或火 花檢測器、或堆積膜厚檢測器等構成，也可設置對應半導 體製造製程之複數的檢測器，收訊顯示處理裝置之裝置狀 態之檢測訊號而構成。 另外’將在第1處理工程43所使用之處理裝置之維 護時期、洗淨時期、零件更換時期之事件資訊4 3 b送訊給 貫fj加工B處理之弟2處理工程4 6的自我診斷系統3 4。 依據此事件資訊43b，可以推測現在時間點（即時）之在 第1處理工程43所處理中的批次係以哪種狀態（或特 性）由第2處理工程4 6所繼續。 -17- 1280603 (14) 自我診斷系統3 1係依據半導體製造製程之進行，以 特疋之時間間隔（例如，1秒間隔）測量及解析在第1圖 所不之處理裝置1 4的內部所積蓄或堆積或消耗之物質的 量’在此物質之量到達特定量之階段產生自動修復要求訊 號。此自動修復要求訊號係當成QC資訊3 1 a而被送訊給 警告裝置32。在半導體裝置之製造系統30稼動之初期階 段中，響應Q C資訊3 1 a所包含之自動修復要求訊號，警 告裝置32對於在第1處理工程43稼動之如氧化爐之處理 裝置1 4送訊自動修復之時序指示資訊3 2 a。 如舉例進行加工A之第1處理工程4 3爲實行熱化學 反應製程之情形，則依據特定之時間間隔（例如，1秒間 隔）測量及解析作爲處理裝置1 4之氧化爐的內部所堆積 之氧化堆積物量，在此氧化堆積物量到達特定之堆積量之 階段，產生自動修復要求訊號。此自動修復要求訊號係當 成QC資訊31a而被送訊給警告裝置32。半導體裝置之製 造系統3 0響應Q C資訊3 1 a所包含之自動修復要求訊 號，警告裝置3 2對於氧化爐送訊自動修復之時序指示資 訊32a而構成。 所舉之氧化爐雖收訊自動修復之時序指示資訊32a， 但是，在實行第1處理工程43之階段中，可以令自動修 復處理待機，直到1單位之半導體製造製程結束爲止，在 目前時間點所處理中之晶圓的批次處理結束，將晶圓搬出 於氧化爐外後，對於氧化爐內部導入淸潔氣體。 在此情形下，搬出之晶圓接著藉由第1檢查工程44 -18- 1280603 (15) 而實施線上QC處理，將包3產生在晶圓上之膜厚資訊的 QC資訊44a送訊給參數調適裝置33。 在第1檢查工程4 4線上Q C處理結束之晶圓，在第2 檢查工程45中，藉由第2檢查裝置，檢查晶圓上之圖案 缺陷之有無，將包含缺陷檢查結果之Q C資訊4 5 a送訊給 參數調.適裝置33。在此「線上QC」中，主要進行薄膜之 膜厚測量等之厚度方向的參數之測量。另外，所謂「缺陷 檢查」主要係在藉由微影工程所形成之平面圖案上的缺陷 之檢查。 參數調適裝置3 3係調適前述之自我診斷系統3 1的模 型及其之參數。本實施形態之調適係意指將產生依據自我 診斷系統3 1在特定之時間間隔（例如，1秒間隔）所收 訊之來自處理裝置的裝置資訊43a之自動修復要求訊號之 時序變更爲適當之時期或再構成（例如，3批次連續收訊 處理裝置不佳訊號，開始產生自動修復要求訊號）之功 tb 。 在自我診斷系統3 1之模型及其參數並不適當之情 形，即使在裝置資訊43 a中含有於處理裝置之氧化製程產 生不當之不當參數，於目前時間點處理中之批次結束處 理，由處理裝置被搬出，藉由第1檢查工程44之檢查結 果進入正常値。另外，藉由第2檢查工程45之檢查結果 也進入正常値。因此，由處理裝置所發訊之裝置資訊43a 中的不當參數本身爲錯誤，可以判定爲信賴性低之參數。 在本實施形態中，爲了提高包含信賴性低之不當參數 -19 - (16) 1280603 之裝置資訊4 3 a的精確度，將發出不當參數之時間點的晶 圓之批次做品質檢查，統計性地求得裝置資訊4 3 a與晶圓 之狀態是否一致，由參數調適裝置3 3對於自我診斷系統 3 1反饋修正之參數3 3 a等而構成。 典型上，可以通過第1檢查工程44及第2檢查工程 45而取得過去10批次之晶圓的QC資訊44a及QC資訊 45a，一面比較裝置資訊43a之不當參數，一面逐次變更 自我診斷系統3 1之模型的參數3 3 a而做控制。 如以使用薄膜處理裝置之半導體裝置之製造系統爲 例，也可以在第1檢查工程44使用膜厚檢查裝置，施以 膜厚檢查，在第2檢查工程45使用圖案缺陷檢查裝置， 施以缺陷檢查，取得各檢查結果資訊，比較裝置資訊4 3 a 之不當參數，逐次變更自我診斷系統 3 1之模型的參數 3 3 a而做控制。 自我診斷系統3 1係在半導體裝置之製造系統3 0稼動 之間，一面修正自我診斷系統3 1的模型之參數，一面實 行處理裝置之自我診斷。即監控處理裝置之狀態，響應不 當訊號之收訊，產生精確度高之QC資訊31a。此QC資 訊3 1a係對於位在下流之MES進行警告發訊之警告裝置 32，敦促自動修復之時序指示資訊32a之送訊的訊號。 警告裝置32響應QC資訊31a之收訊，對於處理裝 置送訊進行維護之指示的自動修復之時序指示資訊3 2a之 警告資訊。在此情形，維護之頻度一增加，半導體裝置之 製造系統3 0的稼動率降低故，特別是自動修復之時序指 -20- 1280603 (17) 示資訊32a的正確性，當然對於品質管理及量產效果會有 影響。 例如，第1圖所示之處理裝置1 4爲薄膜形成處理裝 置之情形，使淸潔爐內部之氣體的導入次數適當化，可以 一面減少淸潔次數，可以一面防止品質降低，能夠增加半 導體裝.置之製造量。 .另外，警告裝置32響應QC資訊31a之收訊，發訊 維護資訊3 2b，對於操作員通報自動修復發生。例如，可 以做設置在潔淨室內之處理裝置的附近所配置之警告的點 滅通報，或在潔淨室外監控半導體製造製程整體之操作員 的監視器顯示維護指示畫面3 8。 進而，警告裝置3 2響應以別的管道所收訊之檢查頻 .度修正指示資訊33b，控制前述之第1檢查工程44或第2 檢查工程4 5之處理次數，可以調整晶圓之批次檢查頻 度。即半導體製造製程沿著學習曲線，品質穩定，即時/ 全數檢查之必要性變低之階段，響應來自參數調適裝置 3 3之檢查頻度修正指示資訊3 3 b，省略藉由第1檢查工程 44或第2檢查工程45之品質檢查，以自動地再構成半導 體製造製程，減少檢查工程，可以增加作爲半導體裝置之 晶圓的產出。 進而，參數調適裝置3 3產生以特定之批次所發生之 新的缺陷發現之報告資訊3 3 c，可以對於在潔淨室外活動 之技術人員的缺陷發現報告部3 9報告中間工程之晶圓的 新缺陷發現之事實。 -21 - 1280603 (18) 另一方面，完成結果/產品率收集部36係取得D/S 處理工程48檢查批次完成工程47之晶圓的產品率資訊 4 8 a，例如，在判定產品率降低之情形，即刻自動地強化 品質管理體制而將顯示產品率降低之產品率資訊3 6a送訊 給完成結果/產品預測系統3 5。 完成結果/產品預測系統3 5即時地處理晶圓之品質 管理，一面比較從前之產品率資訊與目前時間點之產品率 .資訊3 6b，一面預測產品率之傾向（增加或減少）。藉由 將顯示此產品率之傾向的產品率之預測資訊3 5 a送訊給前 述之參數調適裝置33，可由參數調適裝置33對於警告裝 置32送訊檢查頻度修正指示資訊33b。 前述之檢查頻度修正指示資訊33b雖被自動調整，舉 其之控制手法之例。典型上，可以使用在第1處理工程 43動作之處理裝置的工程能力指數Cp而自動調整檢查頻 度。此處，將形成在晶圓之膜厚或者不純物擴散深度或者 蝕刻率等當成目標値而事先規定各變數。儲存：對於此目 標値，增加特定量之處理裝置的上限規格Sii、對於此目 標値，減少特定量之處理裝置的下限規格S1、平均數批 次處理之實測値之處理裝置的平均値X、表示對於此平均 値之各實測値的偏差之處理裝置的標準偏差D，算出處理 裝置的工程能力指示Cp之情形，依據上限規格S U，工程 能力指數Cp係有：（Su-x ) /3D之關係，另外，依據下 限規格 S1，工程能力指數Cp係有：（x-Sl ) /3D之關 係。 -22- 1280603 (19) 前述之工程能力指數Cp，例如在低於1 · 3 3之狀態 (Cp< 1.33 )時，增加檢查頻度而再構成半導體製造製 程。另外，工程能力指數Cp例如在1 .33以上，且低於 1 .67之狀態（1 ·33 S Cp<l ·67 )時，維持檢查頻度而控制 爲不做變更。進而，工程能力指數Cp例如在1 .6 7以上之 狀態（.1 .67 S Cp )時，減少檢查頻度而再構成半導體製造 製程，可以如此地做自動控制。 另外，也可以由處理裝置所搬出之批次的過去1 0次 份之膜厚或不純物擴散深度或蝕刻率等之檢查結果，依據 處理裝置的檢查平均値X，與處理裝置之上限規格Su，或 者處理裝置的下限規格S1，算出處理裝置的工程能力指 .數。在此情形，即使對應工程能力指數Cp而將檢查頻度 變更爲目前時間點之2倍、1倍、及〇. 5倍，也可以實行 與前述之檢查頻度的控制同等之半導體製造製程管理。 另外，如舉處理裝置之氧化爐爲例，在設當成目標値 之膜厚爲1 〇nm之情形，可以進行以上限規格 Su爲 1 2 n m、下限規格S 1爲8 n m之檢查頻度的控制。 進而，完成結果/產品率收集部3 6係將產品率資訊 3 6a送訊給GDS資料取出要求部37，敦促將取出微影工 程所使用之光罩資料的一部份之光罩資訊3 7a送訊給前述 之參數調適裝置33。例如，在左右半導體裝置之產品率 的晶圓上之缺陷部位顯示局部性之情形，會有對於自我診 斷系統3 1之模型的調適效果有利地作用之情形。 -23- 1280603 (20) (第2實施形態） 參考第2圖，說明關於本發明之第2實施形態之半導 體裝置之製造系統3 0的動作流程。另外，與前述之第！ 實施形態重複之構件或工程之說明，則予以使略。 半導體裝置之製造系統30係具備：處理藉由第1處 理工程4 3所搬入之晶圓之第1處理工程4 3，及進行在第 1處理工程43所處理之晶圓的檢查之第1檢查工程44， 及進行經過第1檢查工程44之晶圓的檢查之第2檢查工 程4 5，及處理經過第2檢查工程4 5之晶圓之第2處理工 手壬46’經過複數之處理工程與檢查工程，在晶圓內完成 半導體裝置之批次完成工程47，及檢查晶圓之D/S處理 工程4 8。 半導體裝置之製造系統30進而具備：自我診斷第1 處理工程43之自我診斷系統31，及自我診斷第2處理工 程46之自我診斷系統34，及收訊在D/S處理工程48取 得之產品率資訊4 8 a之完成結果/產品率收集部3 6，及 連接於此完成結果/產品率收集部3 6，預測半導體裝置 之完成結果/產品率之完成結果/產品率預測系統3 5。 半導體裝置之製造系統30係藉由D/S處理工程48檢 查通過前述之批次完成工程4 7之晶圓，將產品率資訊 4 8 a送訊給完成結果/產品率收集部3 6，產生新的產品率 資訊3 6b，送訊給完成結果/產品率預測系統3 5而構 成。 另外，半導體裝置之製造系統3 〇係使上流之半導體 -24- 1280603 (21) 製造製程之狀態反映於下流之半導體製造製程，每 地預測晶圓中之半導體裝置之產品率。即管理配置 工程之處理裝置之現象，將更換薄膜形成處理裝置 品之維護時期、薄膜形成處理裝置之洗淨時期、薄 處理裝置之零件更換時期之事件資訊4 3 b轉送給連 下流工程之第2處理工程46動作之別的半導體製 用之蝕刻處理裝置之自我診斷系統3 4，可將在第 工程43動作之薄膜形成處理裝置之狀態即時地反 第2處理工程46所實行之半導體製造製程。 進而，配置在上流工程之自我診斷系統3 1係 配置在下流工程之自我診斷系統3 4，送訊關於藉 裝置所處理之晶圓的品質管理之批次資訊4 9。 自我診斷系統3 4係綜合地數値性地評估前述 資訊43b與批次資訊49，藉由第2處理工程46所 晶圓的批次是否通過處理裝置狀態良好之上流工程 理裝置狀態之劣化的上流工程，依據數値對比等客 定品質，依據由在第2處理工程46對於晶圓施以 之處理之處理裝置所即時送來之裝置資訊46a，可 精度高之自我診斷處理。 另外，自我診斷系統3 4利用事件資訊4 3 b、 訊49、及在第2處理工程46實行製程之處理裝置 資訊46a，運算經過第2處理工程46之晶圓的 (例如，數1 0%之產品率）後，將此運算結果送訊 預測部40。 一批次 在上流 之消耗 膜形成 接於在 造製程 1處理 映給在 連接於 由處理 之事件 處理之 ，或處 觀地判 加工B 以實行 批次資 的裝置 產品率 給交貨 -25- 1280603 (22) 在此情形下，基於第1處理工程43之不當製程之缺 陷部位在第2處理工程46無法修復故，愈往半導體製造 製程之下流工程進展，則晶圓內的產品率愈爲降低故，交 貨預測部40可以在半導體製造製程的中間工程預測或判 定最終成爲良品之半導體裝置的數量。 交·貨預測部4 0係對於作成半導體裝置之製造系統3 0 之稼動計畫的未圖示出之生產計畫用電腦，可自動地實行 晶圓投入量控制特快申請處理4 1，比起在晶圓的最終檢 查發現缺陷產品，可以早期地將可修復批次流向晶圓工程 故，能夠期待企業體之半導體製造商的現金流量之最大 化。 (第3實施形態） 在第3實施形態說明之半導體裝置之製造系統5 1係 可對應加工處理半導體裝置之各種處理裝置，例如，當然 可以以能應用在：實行薄膜形成製程之薄膜形成處理裝 置、不純物之擴散處理裝置，藉由CVD(化學氣象沈積）之 薄膜堆積膜裝置、迴焊（熔解）PSG膜、BSG膜、BPSG 膜（絕緣膜）等之加熱爐裝置、調整CVD氧化膜等之密 度量、矽化金屬膜（電極）厚度等之熱化學反應處理裝 置、堆積金屬配線層之濺鍍裝置或真空蒸鍍裝置、進而電 鍍之電鍍處理裝置、化學機械硏磨半導體基板之CMP處 理裝置、蝕刻半導體基板表面之乾式或濕式蝕刻處理裝 置、微影處理相關之旋轉塗佈處理裝置、步進機等之曝光 -26- 1280603 (23) 處理裝置、將經過切割之小片狀的半導體裝置之電極^g g 於導線架之焊線處理裝置等各種半導體製造製程之處@ ^ 置爲對象。 第3圖係本發明之第3實施形態之半導體裝置之製造 系統5 1的模型方塊圖。半導體裝置之製造系統5 1例如具 備：實行使用熱化學反應之熱製程之製程處理部之氧化爐 54，及作爲製程處理部控制裝置之氧化爐控制器52，及 控此氧化爐控制器5 2之動作及不動作，以及動作狀態之 電腦1 1，及計算配置在此電腦1 1與氧化爐5 4之間之晶 圓上的氧化膜厚量之氧化膜厚度即時模擬器5 3。另外， 此氧化膜厚度即時模擬器5 3在本實施形態中，構造上雖 與氧化爐控制器52爲另外之裝置，但是，也可以在氧化 .爐控制器5 2的內部作爲其功能的一部份而構成爲一體。 此氧化膜厚度即時模擬器5 3係響應由氧化爐控制器 52被送往氧化爐54之開始訊號，內部的氧化膜厚計算部 5 6依據顯示由氧化爐5 4即時所送訊之爐內部的溫度或壓 力之裝置內部資訊，開始形成在搬入氧化爐5 4之晶圓的 氧化膜厚之計算。此氧化膜厚之計算値係即時地送訊給電 腦1 1，使用於利用ME S之工廠的生產管理。 電腦Π係依據記憶在內部的資料庫之MES之控制資 訊，在氧化膜厚之計算値到達特定的氧化膜厚値之階段’ 對於氧化爐控制器5 2送訊控制訊號。氧化爐控制器5 2響 應此控制訊號，對於氧化爐54送訊令氧化處理停止之停 止訊號。此停止訊號倂同由氧化膜厚度即時模擬器5 3的 -27- 1280603 (24) 內部的氧化膜厚計算部5 6所監控，可即時地令氧化膜厚 度即時模擬器5 3檢知移往氧化處理停止之時序。 在習知的半導體裝置之製造裝置中，氧化膜厚計算部 不監控令體化處理停止之停止訊號故，目前時間點之裝置 內部資訊是否爲顯示停止訊號被送訊後之爐內部狀態，並 無法做.判別，但是，第3圖所示本實施形態之半導體裝置 之製造系統5 1係以氧化膜厚度即時模擬器5 3監控由氧化 爐控制器52所送訊之停止訊號故，依據由令氧化處理停 止之時間點之顯示氧化爐5 4的內部溫度或壓力之下降的 裝置內部資訊，可繼續即時地處理氧化膜厚計算。 氧化膜厚計算部5 6在收訊由氧化爐控制器5 2所送訊 之開始訊號後，依據裝置內部資訊，開始形成在氧化爐 54內部的晶圓之氧化膜厚之計算，在特定之製程期間 後，收訊由氧化爐控制器52所送訊之停止訊號，進而直 到經過特定時間，即時地繼續氧化膜厚之計算。 藉由氧化膜厚計算部5 6之氧化膜厚之計算値係顯示 裝置內部資訊由氧化爐5 4所送訊之每一時間點所計算之 瞬間値，此瞬間値係依循藉由實驗計畫法之D Ο E (實驗設 s十法）f旲型5 9 ’由開始訊號接收時間點經過令氧化製程完 了之停止訊號接收而至經過特定時刻之期間，逐步實行積 分處理’可以算出形成在晶圓之氧化膜整體之厚度。 另外，藉由氧化膜厚度即時模擬器53之半導體裝置 之製造系統5 1與習知之製造裝置不同處爲，電腦1 1對於 處理之E E S資料6 0附加處理室N 0資訊，例如，氧化爐 1280603 (25) 之 計 訊 時 護 以 成 造 相 理 裝 有 視 之 裝 工 查 對 5 4內部以複數之處理室構成之情形，令對應這些複數 每一處理室不同之EES資料60，可以提升氧化膜厚之 算精度。而且’即時地取得每一處理室之裝置內部資 故’當然在批次處理之氧化膜厚真實模擬變得有利。 在本實施形態中，將氧化爐5 4之時間經過要素即 地加在.熱化學反應製程故，例如，收訊更換消耗品之維 時期或氧化爐5 4之洗淨時期之類的事件資訊，關於其 後之經過時間，藉由氧化膜厚度即時模擬器5 3也可達 進行積分處理之積分功能。因此，與以同樣的半導體製 製程條件處理全部批次之習知的半導體裝置之製造裝置 比，可以施以精密之品質管理。 另外，雖將半導體裝置之製造系統5 1當成氧化處 裝置而進行說明，但是，本發明並不限定於氧化處理 置。例如，對於蝕刻裝置等之處理裝置，也可以構築具 作爲第3圖之即時模擬器之構成要素所舉例之「端點監 器+蝕刻率推測」之類的即時模擬器功能之半導體裝置 製造系統。 (第4實施形態） 第4圖係說明關於本發明之第4實施形態之半導體 置之製造方法之模型流程圖。實行加工A之第1處理 程43、實行線上QC之第1檢查工程44、實行缺陷檢 之第2檢查工程45、實行加工B之第2處理工程46、 於技術人員之缺陷發現報告部39a、QC資訊44a、45a -29- 1280603 (26) 維護資$ 2 b係與前述之第1實施形態相同，省略重複說 明。 本貫施形態所示之半導體裝置之製造系統，係利用推 測品質官理値與實測値之差異，以診斷各處理裝置、各種 感測器、自我診斷系統之模型而構成。品質推測部6 1係 由在第.1處理工程43實行製程之處理裝置接受包含複數 之變數X之裝置資訊43 a(例如，EES資料），依據以函數 f所表示之自我診斷系統的模型及其之參數a、參數b與 包含在即時接收之裝置資訊43a之複數的變數X，算出包 含在對應目則時間點之熱化學反應製程中的批次之複數的 輸出Y資料之推測品質資料6 1 a，將此推測品質資料6 1 a 送訊給作用爲異常檢知裝置之比較器6 2。 在此推測品質資料6 1 a係包含有晶圓之氧化膜厚之面 內分布’或氧化膜厚之平均値之#資料、顯示氧化膜厚之 偏差的標準偏差値之D資料，可以對於實行連接在比較 器6 2之ME S的控制之電腦1 1提供即時之半導體裝置之 品質資訊。 此電腦1 1係連接在實行第1檢查工程44之線上QC 處理裝置或實行第2檢查工程45之缺陷檢查裝置，依據 分別比較推測品質資料6 1 a與藉由第1檢查工程44之QC 資訊44a或藉由第2檢查工程45之QC資訊45a之差異 資訊，對於線上QC處理裝置或缺陷檢查裝置輸出第1檢 查工程44或第2檢查工程45之檢查頻度之最佳化資訊 64，可以省略第1檢查工程44或第2檢查工程45，能夠 -30- 1280603 (27) 縮短半導體裝置之製造工程期間。 品質推測部6 1例如係接受依據作爲儲存在QC資料 庫65之品質管理資料之馬哈朗諾比斯距離（Mahalanobis distance )之自我診斷系統之模型及參數資訊63，藉由在 隨時間變化之第1處理工程43實行製程處理之氧化爐內 部的狀態之運算處理，以算出推測品質資料6 1 a。推測品 質資料6 1 a係如前述般，雖被送訊給比較器62，但是也 當成反饋資訊6 1 a被送訊給並行在第1處理工程4 3實行 製程之氧化爐，作爲前餽資訊6 1 c而被送訊給在位於此第 1處理工程4 3之下流工程的第2處理工程4 6處理加工B 之蝕刻處理裝置或微影處理裝置之類的實行氧化處理製程 以外之半導體製造製程之處理裝置。 比較器62係收訊：來自品質推測部6 1之推測品質資 料61a，及來自實行第1檢查工程44之檢查裝置之QC資 訊44a，及來自實施第2檢查工程45之檢查裝置之QC資 訊45a，及來自警告裝置32之維護資訊32b而構成。 如此，比較器62收訊運算處理來自品質推測部6丨之 裝置資訊4 3 a與模型及參數資訊6 3之推測品質資料 61a，可以由在第1檢查工程44及第2檢查工程45實行 製程處理之各檢查裝置收訊實測値，一面比較關於品質管 理之推測値與實測値，一面可以進行自我診斷系統之參數 的推測。即一面令所推測之自我診斷系統的參數近似於實 測値，一面由比較器62對於品質推測部6 ]送訊補正之自 我診斷系統的參數a '參數b。 -31 - 1280603 (28) 將由品質推測部6 1所輸出之推測品質Ys反饋給第1 處理工程4 3之半導體製造製程，可使品質穩定的同時， 藉由將推測品質Ys前饋給第2處理工程46，可事先令實 行第2處理工程4 6之製程處理之處理裝置的參數與推測 品質Ys —致，在目前時間點，第1處理工程43中之批次 於搬入第2處理工程4 6之階段’可令貫行依據推測品質 Ys之製程處理。 進而，比較器62如前述般，取得推測品質資料6 1 a 與作爲實測値之QC資訊44a、45a故，在推測値與實測 値之間發生乖離之階段，可以早期地判定第1處理工程 43之處理裝置、第1檢查工程44之檢查裝置、第2檢查 工程45之檢查裝置之何者，或者全部產生不當，不能做 精度高之品質管理之狀態。 比較器62在依據推測品質資料6 1 a，檢測出顯示第！ 處理工程43之處理裝置、第1檢查工程44之檢查裝置、 或者第2檢查工程45之檢查裝置產生不當之訊號時，將 裝置/感測器異常檢知訊號62a送訊給警告裝置32及作 業員之監視器，令半導體製造製程停止’可令作業員之維 護指示畫面3 8顯示目前時間點之品質管理資訊。 (第5實施形態） 第5圖係說明本發明之第5實施形態之半導體裝置之 製造方法的模型流程圖。批次投入工程42、第1處理工 程43、第1檢查工程44、第2處理工程46、批次完成工 -32- 4 1280603 (29) 程47、D/S處理工程48、品質推測部61係與前述之第 實施形態相同，省略重複說明。 依據本實施形態之半導體裝置之製造方法係具備： 置在半導體製造製程之上流之例如藉由薄膜形成處理裝 之第1處理工程43，及配置在此第1處理工程43之下 之第2處理工程4 6，及檢查形成在經過批次完成工程 之複數的半導體裝置之裝置性能及產品率之D/S處理工 48 ° 處理加工A之第1處理工程43係將實行製程處理 處理裝置的裝置資訊43a送訊給品質推測部61，品質 測部6 1依據裝置資訊43 a，將推測品質資料6 1 a送訊 推測品質管理部66。此推測品質管理部66在目前時間 ’被施以加工A之批次的處理結束後，將藉由第1檢查 程44之晶圓的線上QC處理結果當成比較資料67予以 得，可與推測品質資料6 1 a比較故，能夠判定推測品質 料6 1 a之精度。 例如，推測品質管理部6 6 —面比較品質推測部6 1 推測之推測品質資料6 1 a與在第1檢查工程44所實測 實測値，一面逐次實行裝置資訊4 3 a與實測値之相關 理。此處，本實施形態之相關處理係意指使藉由品質推 部6 1所推測之推測品質資料6〗a近似實測値之處理， 在各批次所獲得裝置資訊43a反饋給第1處理工程43 半導體製造製程，在處理下一批次之階段，補正裝置資 4 3 a可使接近實測値。因此，藉由相關處理，可以適當 配 置 流 47 程 之 推 給 點 工 取 資 所 之 處 測 將 之 訊 地 -33- 1280603 (30) 修正品質推測部6 1之推測品質資料6 1 a的算出模型之參 數。 例如，實行1 0批次之相關處理後之推測品質資料 6 1 a與實測値之乖離減少爲第1檢查工程44 (線上QC ) 或第3檢查工程44c(線上QC)變成不需要之程度，對於連 接在推.測品質管理部66之製程及裝置模擬裝置69a轉送 在第1處理工程4 3施以加工A之批次的產品率資訊，推 .測品質管理部6 6可以預測在處理工程4 3所被處理之批次 的產品率。 同樣地，處理加工B之第2處理工程46將實行第2 處理工程46之製程處理之裝置資訊送訊給品質推測部 68，品質推測部68依據所收訊之裝置資訊，將作爲推測 品質資料之QC資訊68a送訊給推測品質管理部66a。此 推測品質管理部66a在目前時間點被施以加工b之批次的 處理結束後，將作爲藉由第3檢查工程44c之晶圓的檢查 結果資料的QC資訊44d骯成比較資料67a而取得，可以 與QC資訊68a比較。 推測品質管理部6 6 a —面比較品質推測部6 8所推測 之Q C資訊6 8 a與在第3檢查工程44 c所實測之q c資訊 44d，一面逐次實行裝置資訊與實測値之相關處理。 例如，實行1 〇批次之相關處理後之QC資訊68a與 實測値之乖離減少爲檢查由施以加工B之第2處理X程 4 6所搬出之晶圓的第3檢查工程4 4 c (線上Q c )變成不需 要之程度，對於連接在推測品質管理部66a之製程及裝置 -34- 1280603 (31) 模擬裝置69a轉送在第2處理工程46施以加工B之批次 的產品率資訊，推測品質管理部66a可以預測在處理工程 4 6所被處理之批次的產品率。 製程及裝置模擬裝置69a依據上流工程之第1處理工 程43的產品率資訊與下流工程之第2處理工程46的產品 率資訊.，實行半導體製造製程及作爲半導體裝置之裝置的 模擬，將各批次之推測產品率資訊送訊給下一段之裝置性 能產品率預測部7〇a。 前述之裝置性能產品率預測部70a雖依據推測品質管 理部66及推測品質管理部66a所推測之資訊以預測半導 體裝置之產品率，但是，進而在本實施形態中，收集藉由 .線上QC處理之第1檢查工程44的QC資訊44a，及第3 檢查工程44c之QC資訊44d，依據實測値，可在中間處 理工程之階段預測半導體裝置之產品率。 製程及裝置模擬裝置 69結合藉由配置在上流工程 (或前段工程）之第1檢查工程44之QC資訊44a，及配 置在下流工程（或後段工程）之第3檢查工程44c的QC 資訊44d，實行製程及裝置之模擬，將模擬結果之產品率 資訊送訊給下一段之裝置性能產品率預測部70。 裝置性能產品率預測部70將各批次之產品率預測資 訊72送訊給前述之裝置性能產品率預測部70a。裝置性 能產品率預測部70a比較推測產品率資訊與產品率預測資 訊72，藉由實行半導體裝置之產品率預測處理75，可以 提供更高精度之產品率預測，與產品率預測處理 75並 -35- 1280603 (32) 行，可再設定（例如，檢查之省略或部份省略）藉由第1 檢查工程44與第3檢查工程44c之線上QC的頻度。 進而，依據本實施形態之半導體裝置之製造系統雖係 由依據配置在第1處理工程43及第2處理工程46之各工 程的處理裝置之裝置資訊之推測品質，預測半導體裝置之 產品率.的同時，依據由各處理工程所搬出之晶圓的檢查結 果，預測半導體裝置之產品率，但是，也可以與此預測之 產品率並行，對於批次完成工程4 7之晶圓，以藉由探針 檢查裝置之D/S處理工程48可以求得裝置性能產品率。 比較處理71藉由D/S處理工程48所實測之產品率與 裝置性能產品率預測部7 0之產品率，由其之差異也可補 正裝置性能產品率預測部7 0之模擬精度，比較處理7 3藉 由D/S處理工程4 8所實測之產品率與裝置性能產品率預 測部70a之產品率，由其之差異也可以補正裝置性能產品 率預測部70a之模擬精度。即可以適當地修正製程及裝置 模擬裝置69、69a之模擬模型的參數。 如依據在本實施形態所示之半導體裝置之製造系統， 依據實測之半導體裝置之產品率，如一面補正各產品率預 測，一面重複半導體製造製程，可以進行精度高之產品率 預測，例如，具有可以省略作爲品質管理用之晶圓的 NPW(無產品晶圓），也可以省略作爲線上 QC之檢查工 程，也可實行各批次之半導體製造製程批次模擬之優點。 (第6實施形態） -36- 1280603 (33) 第6圖係說明界定關於本發明之第6實施形態之半導 體裝置之使產生不良批次之製造裝置之方法圖。圖中之半 導體裝置之處理工程雖使用氧化爐爲例，但是，本發明之 第1處理工程4 3所使用之處理裝置並不限定於氧化爐， 當然也可以適用於實行其他的半導體製程之處理裝置。 如氧化工程之第1處理工程43係在處理裝置內部的 處理室，藉由熱化學反應製程，使在晶圓上形成氧化膜。 另外，第1處理工程43所使用之處理裝置係由配置在連 接於測定裝置7 7之處理室內部的複數之檢知器對於測定 裝置7 7即時地送訊壓力、溫度、電壓、閥門開度之類的 裝置資訊。 測定裝置7 7依據收訊之各種檢知資料，判定半導體 製造製程中的晶圓之狀態。例如，由實行第1處理工程 43之半導體製造製程之處理裝置的內部之處理室收集複 數的資料，可以界定以每一半導體製造製程之處理程式所 處理之晶圓的批次。 另外，測定裝置77具有即時之資料收集能力，例 如，將在特定的時間間隔同時檢測之9種的類比資料轉換 爲數位資料，將此數位資料每一批次地以時間序列加以記 錄及解析。圖中央之直方圖係將在測定裝置7 7所收集之 處理室內部的狀態以時間序列予以記憶，將此記憶之時間 序列資料轉換爲標量（scalar )，作爲檢測値79 (檢測） 而加以顯示。能在顯示器上確認在此檢測値7 9之中，以 可製程控制之低波高値與高波高値所示之無法製程控制之 -37- 1280603 (34) 非控制値8 0 (無法控制）。 測定裝置7 7依據以非控制値8 0所示之標量 理對應處理工程4 3之特定的處理時刻之處理室 曲線表示特徵量化8 1 (區域化）處理室內部的 之數値資訊。此特徵量化8 1係顯示處理中的批 個晶圓的特定處所是否存在哪種缺陷。例如，依 非控制値8 0，將當成處理室內部的特徵量（或 訊）之參數A的値當成0.78，參數B的値當成-算處理，存取在測定裝置7 7的內部或外部記錄 化81之數位資訊之未圖示出的特徵量資料庫， 即時之缺陷辨識處理之相同程度化處理82 識）。 前述之相同程度化處理8 2所使用的特徵量 以圖中的相關表8 3之形式加以管理，可以使用 爐之處理工程43之裝置狀態的修正（correcti 如，對應在相關表8 3之左邊欄位所示之缺陷參 分類號碼的欄位所示之 XI之右邊欄位序 (Α = 0·8/Β = -0·6)，及測定裝置77運算處理之 參數Α0.78、參數Β-0.63被做相同程度化處理 形’晶圓的批次狀態係如具有同左上所示之缺陷 另犬態84般，以奇數與偶數之順序記錄良品多數 ^少數晶圓被搬出之統計性資料。在此統計性資 半導體製造製程之處理程式資訊或TEG資訊， 及半導體裝置之分類資訊也可包含在資料中。 ，解析處 狀態，以 要素資訊 次之第幾 據檢測之 者要素資 0.63而運 此特徵量 實行作爲 (錯誤辨 資料庫係 於如氧化 on) 〇 例 數的缺陷 丨特徵量 特徵量之 8 2之情 部的批次 晶圓與良 料也包含 檢查履歷 -38- 1280603 (35) 另外’藉由對應相關表之左邊欄位的χ 1之右側欄位 之特徵値所界定的晶圓之處理，在如氧化工程之處理工程 43中，會有在複數之處理室間，某種之EES訊號之差被 檢測出之情形，可以界定處理裝置之推測不良模式。 藉由在相關表8 3的左側欄位所示之缺陷形式之缺陷 分類號.碼之X2而被相同程度化處理82之晶圓的批次狀 態.，在作爲記億於特徵量資料庫之特徵量的參數A之値 爲0.2，參數B之値爲〇. 7之小數點以下以1位數表示之 數値資訊被讀出，與經過特徵量化8 1之資料比較而近似 之情形，此晶圓之批次狀態係依據如圖左中段所示之批次 狀態8 5般，以隨機狀態，良品少數晶圓被搬出之統計性 資料而評估處理工程43。 同樣地，藉由在相關表8 3的左側欄位所示之缺陷形 式之缺陷分類號碼之X3而被相同程度化處理82之晶圓 的批次狀態，在作爲記憶於特徵量資料庫之特徵量的參數 A之値爲0.4，參數B之値爲-0 · 3之小數點以下以1位數 表示之數値資訊被讀出，與經過特徵量化8 1之資料比較 而近似之情形，此晶圓之批次狀態係依據如圖左中段所示 之批次狀態8 6般，批次之前半存在良品少數晶圓，批次 之後半存在良品多數晶圓之批次被搬出之統計性資料而評 估處理工程43。另外，對應X3之缺陷分類號碼之批次的 晶圓例如藉由處理工程43之爐內溫度逐漸上升時，缺陷 消滅之修復工程，可以令產品率提升。 測定裝置77係如前述般，即時地檢測處理工程43之 -39- 1280603 (36) 處理室狀態，予以特徵量化8 1，逐次進行相同程度化處 理8 2故，在藉由相同程度化處理8 2發現不良多數之批次 的階段，可以自動地界定變成不良原因之處理工程4 3。 因此，在不良多數之批次被發現時，即刻停止產生不良批 次之處理工程 43，報告作業員以實施維護而構成。另 外，被特徵量化8 1爲新形式之批次係分配圖中右下所示 之「新記號」，對於前述之特徵量資料庫記憶該特徵量或 .顯示晶圓之批次狀態之資訊。 (第_7實施形態） 第7圖係說明關於本發明之第7實施形態之半導體裝 置之製造方法的模型流程圖。批次投入工程42、第1處 理工程43、第1 .檢查工程44、第3檢查工程44c、第2 處理工程4 6、批次完成工程4 7、D / S處理工程4 8、品質 推測部6 1、推測品質管理部6 6、檢測値7 9、非控制値 80、特徵量化81、相同程度化處理82、相關表83、及新 記號係與前述之實施形態相同，省略重複說明。 半導體裝置之製造系統係使對應具有與既知的特徵量 化8 1之資訊相關連之缺陷部8 4 b之晶圓1 7 b，或具有缺 陷部84a之晶圓17c之缺陷參數XI、χ2、X3之分類號碼 與複數之特徵量記憶於特徵量資料庫，藉由將被特徵量化 8 1之批次予以相同程度化處理8 2，得以發現不良批次， 即使相同之缺陷部8 4 a存在，作爲未知之不良形式，對於 晶圓1 7 a經過處理之批次，批次排除處理及維護處理也有 -40- 1280603 (37) 困難。 相對於此，在本實施形態中’由實施處理工程4 3之 處理裝置使即時收集之裝置資訊對應各批次而送訊給品質 推測部6 1，之後，結束下流工程，將經過批次完成工程 4 7之晶圓1 7 a藉由D / S處理工程4 8加以檢查’得以界定 最終之.缺陷部84a。 D / S處理工程4 8係記憶或輸出批次號碼、缺陷部之 位址故，半導體裝置之製造系統係以此批次號碼爲線索， 檢索處理此批次之加工A之處理工程43所使用之裝置的 裝置資訊（例如，參考第2圖之43a )，令品質推測部61 將檢索之裝置資訊4 3 a當成不良批次資訊予以監控，控制 .自動地更新品質推測部6 1內部之參數。推測品質管理部 66係如前述般，由品質推測部6 1接受推測品質資料，推 測半導體裝置之產品率故，在目前時間點後之半導體製造 製程中，可早期地由半導體裝置之製造系統之生產線排除 具有如晶圓1 7a之缺陷形式之批次，可以有效地防止消耗 無謂之化學藥品等。 另外，半導體裝置之製造系統當然也可將新發現之不 良形式之特徵量資訊當成相關表83中的缺陷參數之缺陷 分類號碼X4而分配新記號》自動地登錄在特徵量資料 庫0 (第8實施形態） 如第8圖所示般，關於本發明之第8實施形態之半導 -41 - 1280603 (38) 體裝 14a， 之處 置於 置在 圓1 19b， 之檢 處理 之電 1實 與其 自我 訊， 1 7a〜 檢查 圓中 結果 深度 憶裝 晶圓 置之製造系統係具備：處理晶圓〗7 &之處理裝置 及處理晶圓17b之處理裝置14b，及處理晶圓i7c 理裝置14c，及處理晶圓17d之處理裝置14d，及設 各處理裝置14a〜14d之自我診斷裝置5a〜5(1，及設 各自我診斷裝置5a〜5d之資料庫13a〜13d，及檢查晶 7a之檢查裝置19a，及檢查晶圓17b之檢查裝置 及檢查晶圓17c之檢查裝置19c，及檢查晶圓i7d 查裝置19d，及連接在自我診斷裝置5a〜5d，收訊各 裝置14a〜14d所處理之各晶圓i7a〜17d的推測品質値 腦1 1。 第8實施形態所使用之自我診斷裝置5 a〜5 d可以與第 施形態所使用之自我診斷系統11a同等之硬體資源及 協同動作之軟體所構成。因此，作爲自我診斷系統之 診斷裝置5a〜5d係收訊處理裝置之裝置資 實行自我診斷。 電腦1 1係與自我診斷裝置5 a〜5 d連接，將全部晶圓 1 7d之推測品質値記憶在記憶裝置1 2，另外，在每次 時序中，由從檢查裝置19a〜19d所送訊之數批次的晶 ，收訊所選擇之批次的晶圓之檢查結果，使依據檢查 之檢查品質値（例如’膜厚、蝕刻率、不純物之擴散 、熔解狀態）與批次號碼、晶圓號碼對應，記憶在記 置12。 藉由電腦11之品質管理，在選擇之批次存在複數的 之情形，則檢查裝置19a〜19d只檢查代表晶圓’使檢 -42- 1280603 (39) 查結果與批次號碼、代表晶圓號碼對應，電腦1 1加以收 訊。沒有檢查之晶圓則推測爲與代表晶圓具有相同品質， 電腦1 1使其與批次號碼及晶圓號碼對應，每一批次及晶 圚進行品質管理。 因此，電腦1 1使用記憶在主資料庫13之APC、MES 之資料，管理製造系統整體，對於複數之處理裝置 14a〜14d，令實行不同之製程。例如，處理裝置14a對於 晶圓17a，實行氧化膜形成製程，處理裝置14b對於晶圓 17b，實行蝕刻製程，處理裝置14c對於晶圓17c，實行 不純物擴散製程，處理裝置14d例如對於晶圓17d，實行 迴焊（或者熔解）而進行控制。 但是，圖示之處理裝置14a〜14d爲了簡單化，雖舉4 台爲例，但是，由目前之LSI之製造工程可以容易理解， 半導體裝置之製造系統一般相同種類之處理裝置係設置有 複數台，整體配置有10台以上之處理裝置。 各處理裝置14a〜14d係通過各種感測器而輸出表示內 部狀態之裝置資訊，例如，如係電漿製程之裝置，將處理 室內部之壓力、溫度、高頻電力値、匹配高頻之阻抗之電 容器値、導入處理室內之氣體的流量等各製程所決定之裝 虞資訊輸出給個別設置之自我診斷裝置5a〜5 d。 自我診斷裝置5a係連接於保存裝置資訊之資料庫 13a，由藉由ESS處理晶圓17a之處理裝置14a收訊裝置 資訊，依據裝置資訊，算出對應晶圓1 7a之推測品質値 (例如，設處理裝置1 4 a爲氧化爐時，形成在晶圓1 7 &上 -43- 1280603 (40) 之膜厚），將此推測品質値送訊給電腦11之同 晶圓1 7a而在資料庫1 3a記憶推測品質値。 另外，例如處理裝置1 4a如設爲氧化爐，所 品質値」係意指將由處理裝置1 4a所收訊之裝置 入膜厚形成模型之式子（例如，Ye = aX + b )，算 厚値Y e之形成在晶圓1 7 a上之膜厚的推測値。 X可以爲加熱器溫度，也可以爲氣體之流量，資 就每一裝置資訊記憶膜厚形成模型之式子，自我 5a將裝置資訊輸入膜厚形成模型之式子，算出 値。 自我診斷裝置 5b係連接於保存裝置資訊 13b，由藉由ESS處理晶圓17b之處理裝置14b 資訊，依據裝置資訊，算出對應晶圓1 7b之推 (例如，處理裝置1 4b爲乾蝕刻裝置時，爲蝕刻 此推測品質値送訊給電腦1 1之同時，對應晶圓 資料庫1 3b記憶推測品質値。 自我診斷裝置5 c係連接於保存裝置資訊 13c，由藉由ESS處理晶圓17c之處理裝置14c 資訊’依據裝置資訊，算出對應晶圓1 7c之推 (例如，處理裝置1 4c如設爲擴散爐，爲不純物 度）’將此推測品質値送訊給電腦1 1之同時， 17c而在資料庫i3c記億推測品質値。 自我診斷裝置5d係連接於保存裝置資訊 13d’由藉由ESS處理晶圓17d之處理裝置Md 時，對應 謂「推測 資訊X帶 出推測膜 裝置資訊 料庫1 3 a 診斷裝置 推測品質 之資料庫 收訊裝置 測品質値 率），將 1 7b而在 之資料庫 收訊裝置 測品質値 之擴散深 對應晶圓 之資料庫 收訊裝置 1280603 (41) 資訊，依據裝置資訊，算出對應晶圓1 7d之推測品質値 (例如，處理裝置1 4 d如設爲退火爐，爲絕緣膜之熔解狀 態），將此推測品質値送訊給電腦1 1之同時，對應晶圓 1 7d而在資料庫1 3d記憶推測品質値。 參考第8圖及第9圖，在晶圓之製造製程中，舉蝕刻 爲例而說明半導體裝置之製造系統的動作。在製造系統 中’抽出進入期待値之範圍的檢查品質値 Y q，比較推測 品質値Y e與檢查品質値Y q，沿著下一流程更新推測品質 値Ye之模型。 此處，所謂「期待値」係意指，時間序列地排列記憶 在記憶裝置1 2之過去的檢查品質値Yq，算出檢查品質値 Y q之傾向，在目前時間點可適當期待之檢查品質値。 (再檢查流程） 在以下中，以處理裝置14a、處理裝置14b、處理裝 置14c、處理裝置l4d中之乾蝕刻裝置的處理裝置14b爲 例而加以說明。 (a )電腦1 1在開始步驟9 0 (以下，將步驟略記爲 「S」）中，收訊檢查裝置19b定期地檢查在處理裝置 14b所處理之晶圓17b的檢查結果之階段，移往異常檢查 S 9 1。電腦1】將檢查結果轉換爲檢查品質値γ q，比較檢 查口α資値與記憶在記憶裝置1 2之期待値，判定檢查品質 値Yq是否異常。在異常判定之情形，往再測量S 92分 岔’對檢查裝置1 9 b送訊再測量指令。 1280603 (42) (b )檢查裝置1 9 b於再測量S 9 2再度測量晶圓 1 7b，將再測量之檢查結果再度送訊給電腦1 1 ° (c )電腦1 1在再測量S 9 2，將再測量之檢查結果轉 換爲檢查品質値Yq，與期待値比較，爲異常判定之情 形，移往郵件送訊S 9 3，對於製程擔任人員發送電子郵 件，通.知晶圓17b之異常發生。 (d )電腦1 1移往履歷更新S 9 4，於記憶裝置1 2記 錄晶圓1 7b之異常，與晶圓之號碼、晶圓之批次、處理晶 圓之處理裝置1 4b相對應而更新資料庫。 (實測値比較流程） .(a )電腦1 1於再測量S92中，將收訊之再測量之檢 查品質値Yq與期待値比較而爲適當判定之情形，使再測 量之履歷與檢查裝置1 9b及晶圓1 7b相對應而記憶於記憶 裝置12之同時，經由節點95而移往推測品質比較S96。 (b)電腦11在異常檢查S91中，即使檢查品質値Yq 也判定爲適當之情形，也移往推測品質比較S96。 (c )電腦1 1在推測品質比較S96中，比較自我診斷 裝置5b算出之推測品質値Ye與檢查品質値Yq，判定是 否與判定基準·一致。判定基準係推測品質値Ye存在於推 測品質値Ye與檢查品質値Yq之回歸直線的可靠區間內 之情形，則判定爲一致，在偏離可靠區間時，判定爲不一 致。 (d )電腦1 1在推測品質比較S96中，做了不一致判 -46- 1280603 (43) 定之情形，移往要素判定處理S 9 7，修正自我診斷參數。 例如，自我診斷參數係以下式（1 )所表示。1280603 (1) Inventive Description of the Invention The present invention relates to a manufacturing system of a semiconductor device and a method of manufacturing a semiconductor device, and more particularly to a method of controlling a manufacturing device and a manufacturing process using the same. Simulation method and simulation device. [Prior Art] Conventionally, substrate step formation, well formation, insulation, transistor formation, bit line formation, capacitor formation, and wiring formation are performed by a semiconductor manufacturing apparatus to manufacture a dram (Dynamic Random Access Memory). And other semiconductor devices. These semiconductor manufacturing processes are suitably combined: lithography, etching, heat treatment (oxidation, annealing, diffusion), ion implantation, thin film formation (CVD, sputtering, evaporation), cleaning (light) It is formed by blocking removal, washing by solution, inspection treatment, and the like. In addition, generally, in the environment in which various types of processing chambers are maintained and controlled, the substrate is carried into the carrying-out processing chamber for engineering processing. However, the substrate after the inspection process is also present, and the obtained measurement inspection data is transmitted to the central control system. A system for managing or recording the history of the substrate or the processing chamber, and self-diagnosis of each processing chamber or manufacturing device to output an appropriate instruction (refer to Patent Document 1). The manufacturing apparatus of the conventional semiconductor device includes an oxidation furnace that performs a hot process, an oxidation furnace controller that controls the oxidation furnace, and an oxide film thickness controller that is connected to the oxidation furnace and the oxidation furnace controller to perform process control. The oxide film thickness controller includes an oxygen-5-1280603 (2) film thickness calculation unit having an oxide film thickness calculation function and a calculation film portion having a calculation film thickness determination function, and is specified by utilizing a thermochemical reaction. The semiconductor manufacturing system performs the initial setting 'starting the semiconductor process according to the preset process, and measures and analyzes the thermochemical reaction to advance the environmental state of the specific system at a specific time interval and the change thereof'. This analysis results the reverse conductor manufacturing process ( Refer to Patent Document 2). However, in such a conventional semiconductor device manufacturing apparatus, a self-diagnosis of a process processing apparatus or a process mode can be performed to control the thickness of the oxide film or the wiring width or impure concentration on the semiconductor substrate, but There is a difference between the product rate of the semiconductor device that is actually measured and the product rate of the actual measured semiconductor device. Therefore, the number of production plans of the tuning device and the number of customers ordered are required, and the complicated additional production plan is frequently repeated, and the inspection work of the wafer is increased, and the manufacturing period of the half is longer. [Patent Document 1] International Publication No. WO 96/25 760, page 25, page 37, line 2) [Patent Document 2] Japanese Patent Laid-Open No. 2002-2993 No. 3, No. 11 column, line 5 to 48 SUMMARY OF THE INVENTION The present invention provides a method for appropriately managing the interval of each process processing device to extend the processing time of each process processing device, and also to reduce the wafer inspection process performed at the end of the manufacturing process. When the thick judgment process is made, the manufacturing feed is given to the half, even if it is intended to be diffused by the material and the semiconductor conductor is mounted by the mandrel (the 36th report (the maintenance of each semiconductor semiconductor -6 - 1280603 ( 3) A manufacturing system of a semiconductor device and a method of manufacturing a semiconductor device which are shortened during the manufacturing process of the device. One aspect of the present invention provides a processing device for performing a process of processing a semiconductor device, and a process control of the control processing device The device, and the process of processing the semiconductor device, monitoring the state of the processing device, integrating the internal information of the processing device, performing simulation of the process processing, and processing by the process A manufacturing system of a semiconductor device for estimating an operation of a semiconductor substrate by an instant simulator. One aspect of the present invention provides a processing device for performing a process for using a semiconductor substrate, and information for receiving the device by the processing device. The self-diagnosis system for calculating the estimated quality of the process, and the inspection device for checking the results of the process, and the comparison check result and the estimated quality 値, when determining the estimated quality 値 is effective, maintaining the parameters of the self-diagnosis system, and determining the estimation A manufacturing system of a semiconductor device in which a comparator of a parameter of a self-diagnosis system is changed when the quality is not effective. One aspect of the present invention provides a processing device for performing a process for using a semiconductor substrate, and a receiving device for the processing device Information, a self-diagnosis system for self-management of the processing device, and an inspection device for checking the results of the process processing, and determining whether to automatically repair the processing device based on the inspection result, and maintaining the parameters of the self-diagnosis system when the determination result is valid. The result of the judgment is In the case of the effect determination, a manufacturing system of a semiconductor device that changes the parameters of the self-diagnosis system. One aspect of the present invention provides a processing device for performing a process of processing a semiconductor device, and a diagnostic processing device based on self-diagnostic parameters 1280603 (4) The self-diagnostic device and the inspection device for checking the process processing, and the self-diagnostic device and the inspection device are connected, and when the inspection result of the semiconductor substrate is valid, the self-diagnosis parameter is maintained, and when the inspection result is invalid, A manufacturing system of a semiconductor device in which a comparator of a self-diagnosis parameter is changed. An aspect of the present invention provides a processing device for performing a process for processing a semiconductor substrate, and obtaining device information of the processing device, and estimating the quality of the quality of the semiconductor substrate A semiconductor device manufacturing system that is a quality inspection device that performs quality inspection of a semiconductor substrate that has undergone processing, and a comparator that compares the estimated quality data of the quality estimation unit with the quality management information actually measured by the quality inspection device. According to one aspect of the present invention, there is provided a processing apparatus for performing a process for processing a semiconductor substrate, and a device for obtaining device information of the processing device, outputting a quality estimation unit for estimating quality information of the semiconductor substrate, and outputting a quality of the processed semiconductor substrate A quality inspection device for information, a speculative quality management unit that performs quality-related processing for estimating quality information and quality information, and a simulation rate for predicting the product rate of the semiconductor device based on the estimated quality information output by the estimated quality management unit. a predicting device, and a processing device, and at least a product rate checking device for checking a product rate of a semiconductor device that completes a wafer engineering; and a product rate of a product rate of a comparison product rate predicting device and a product rate of a product rate checking device A manufacturing system for a semiconductor device. An aspect of the present invention provides a processing apparatus for performing a process for processing a semiconductor substrate, and a quality inspection device for outputting quality information of the processed semiconductor substrate, and a quality according to the quality inspection device-80-1280603 (5) Information, a product rate prediction device that performs simulation, predicts the product rate of a semiconductor device, and a product rate inspection device that processes at least the product rate of the semiconductor device that completes the wafer engineering after processing the processing device; and implements a comparison product rate prediction device The manufacturing system of the semiconductor device in which the product rate is related to the product rate of the product rate of the product rate inspection device. An aspect of the invention provides a processing device for performing a process for processing a semiconductor substrate, and device information for monitoring the processing device, a quality estimation portion for outputting estimated quality information of the semiconductor substrate, and outputting the processed semiconductor substrate A quality inspection device for quality information, a pre-estimated quality management unit that performs quality-related processing for estimating quality information and quality information, and a simulation of predicting the product rate of semiconductor devices based on simulation of quality information from quality inspection devices. The device and the second product rate prediction device that predicts the product rate of the semiconductor device by performing another simulation different from the simulation of the first product rate prediction device based on the estimated quality information from the estimated quality management unit, and the semiconductor manufacturing process. A product rate inspection device that at least checks the product rate of the semiconductor device that completes the wafer engineering; performs a first product rate comparison process comparing the product rate of the first product rate prediction device with the product rate of the product rate inspection device, and compares the second product Rate prediction device product rate and product The second product of the rate of product inspection apparatus of the related manufacturing process of the semiconductor device system. An aspect of the present invention provides a processing device for performing a process for processing a semiconductor substrate, and a device information for comparing the detection processing device, and a feature quantity for characterizing and subtracting the non-control 値 of the extraction process The inherent defect image is counted by the range classification, and the feature quantity in the correlation table memorized in advance -9- 1280603 (6) is determined to be the same as the feature quantity in the correlation table. At the stage of smashing, the manufacturing system of the semiconductor device of the quality detecting unit that interrupts the processing and reports the semiconductor substrate as a defective batch. According to one aspect of the present invention, there is provided a defective batch having a new feature amount that cannot be equalized in a related table in which a defect image that is inherently classified by a range is counted and stored in advance When the detection is performed, the device information indicating the state of the processing device at the time of occurrence of the defective batch of the semiconductor substrate is extracted based on the process history information of the semiconductor substrate of the defective batch, and the device information is automatically fed back to the quality estimation. A manufacturing system for semiconductor devices that is based on the automatic quality update method. According to one aspect of the present invention, a process of a semiconductor substrate is performed by a processing device, a process of a semiconductor substrate is performed, a state of the processing device is monitored, and internal information of the integration processing device is simulated, and a process simulation is performed. A manufacturing system of a semiconductor device that is processed by a process to infer the progress of processing of a semiconductor substrate. The invention can provide: appropriately manage the maintenance interval of each process processing device, prolong the processing time of each processing device, and reduce the wafer inspection engineering performed at the end of each semiconductor manufacturing process, so that the manufacturing process of the semiconductor device can be performed A manufacturing system for shortening a semiconductor device and a method for manufacturing the semiconductor device. [Embodiment] (First Embodiment): 10 - 1280603 (7) As shown in Fig. 1, a manufacturing system of a semiconductor device according to a first embodiment of the present invention includes a wafer for a semiconductor substrate. Or the processing device 14 for processing the film on the surface thereof, and the computer 1 1 a as a self-diagnostic system for performing the self-processing of the processing device 14 by the equipment engineering system EES (hereinafter referred to as "EES"), and The wafer 17 of the processed semiconductor substrate is determined by the inspection result of the inspection device 19 to determine whether or not the automatic repair processing device 4 is used, and when the determination result is valid (or appropriate), the coefficient of the parameter of the self-diagnosis system is maintained ( Or, if it is slightly adjusted, when the judgment result is invalid (or inappropriate), the computer 1 as a parameter adjustment device that changes the parameters of the diagnostic system (for example, increasing the number of inspections) can adjust the semiconductor manufacturing process stage. Frequency system. Here, "E E S" is a system in which the processing device 14 obtains device information and statistically analyzes the device information to determine whether the state of the processing device 4 is normal or abnormal. The E S S is implemented on a computer 丨丨a as a self-diagnostic device system, and the internal state of the processing device 14 for processing the wafer 17 is instantly acquired. Since the internal state of the processing device 14 can be estimated, the process state of the wafer 17 processed inside can be obtained in real time. The computer 1 1 a, which is a self-diagnostic system, allows the processing time of the process performed by the processing device 14 to be changed in the database 1 7 and stored in the database 1 3 a. That is, the manufacturing system 1 of the semiconductor device includes: a computer 1 that controls the entire manufacturing system, and a memory device 1 that is connected to the computer 1 and memorizes the data processing algorithm for the manufacturing process of the semiconductor system -11 - 1280603 (8) 2, and connected to the computer 1, 1, memory APC (advanced process control, hereinafter, simply abbreviated as "APC") or MES (manufacturing execution system, hereinafter, simply abbreviated as "Μ ES") 1 3, and a processing device 14 for processing the wafer 17 as a semiconductor substrate, and an inspection device 19 for inspecting the wafer 17 processed by the processing device 14. Here, the term "APC" means a system in which the computer 11 changes the semiconductor manufacturing process in response to the contents of the wafers 17 processed by the processing device 14. As a result of inspecting the wafer 1 7 by the inspection device 19, if the quality of the desired quality is not achieved, the process conditions of the processing device 14 are changed to the new process conditions while referring to the past process conditions. In addition, the term "MES" means that when a plurality of wafers 17 are processed by the processing device 14, the computer 11 performs production management of the semiconductor device, and transports the selected one of the wafers 17 to the processing device. 1 4, the processing device 1 4 is executed, and the inspection device 19 is also subjected to the inspection system. In order to simplify the illustration, the processing device 1 shown in the figure is exemplified as a single one. However, the manufacturing process of the current LSI (large-scale integrated circuit) can be easily understood. There are more than 10 processing units 14 of a plurality of units. Moreover, the connection of the plurality of devices 14 to the computer 藉I a by the signal line 14 a can enable self-management by the EES. In addition, the plurality of processing devices 14 can be connected to the computer 1 直接 directly or by the computer 1 1 a, and can pass the communication processing device! 4 device information, computer 1 1 according to the device information received, under the management of APC, MES, can comprehensively manage the semiconductor manufacturing system as a whole. -12- 1280603 (9) In addition, the processing device 14 can be equipped with various processing devices for processing semiconductors. For example, it can be applied to, for example, a thin film forming processing device that performs a thin film process, a diffusion processing device for impurities, and a thin film deposition of CVD. A thermal processing device such as a membrane device, a reflow (melted) PSG film, a film, a BPSG film (insulating film), a thermochemical treatment device for adjusting a density such as a CVD film, a thickness of a deuterated metal film (electrode), and a stacked metal A sputtering device for a wiring layer, a plating device for vacuum evaporation and electroplating, a chemical mechanical honing semiconductor-based CMP processing device, a dry or wet processing device for etching a surface of a semiconductor substrate, and a spin coating process for lithography processing A device, a stepwise exposure processing device, and a semiconductor processing device such as a wire bonding device that connects a diced semiconductor device pole to a lead frame. Further, the manufacturing system 10 of the semiconductor device of the present invention can be applied regardless of either the sub-device or the vane device. In the entire embodiment described later, it does not matter whether a batch type device or a device is used in the same manner. The computer 1 1 a 矽 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐 逐Facing the processing device 14 to provide the best state of the current point in time (instant), one side of the detection process 2 1 occurs inside the processing device 14 in the semiconductor manufacturing process feedback internal state. For example, 'the processing device 14 is a thin film with a vacuum processing system, and the electric field of the BSG oxidation reaction, the etching machine of the plate, etc. is the batch of the blade material reservoir, and the film shape is formed. 13- 1280603 (10) In the case of a treatment device such as a treatment device, a diffusion treatment device, or a thin film deposition membrane device, the temperature of the plurality of furnaces, the temperature of the inductor, and the temperature of the plurality of external walls of the treatment chamber are determined. Various parameters such as the pressure of the vacuum in the processing chamber, the flow rate of the gas, and the opening degree of the valve for controlling the gas flow rate are performed to carry out the semiconductor manufacturing process. In addition, in the case where the processing device 14 is a processing device having a dry etching device of a plasma processing system or an electrode like an ion implantation device, in addition to various parameters of the vacuum processing system described above, a matching position according to RF (Radio Frequency) is used. Various parameters such as RF voltage (wave voltage, reflected wave voltage) and wafer position information are used to implement the semiconductor manufacturing process. Further, in the case where the processing device 14 is a wet etching processing device, a spin coating processing device, a stepper exposure processing device, or a wire bonding device of the atmospheric pressure processing system, the processing time or the address information of the wafer or the wafer is used. Various parameters to implement the semiconductor manufacturing process. Further, in the case where the processing device 10 of the semiconductor device uses a gas or a chemical such as a thin film forming processing device, a diffusion processing device, or a thin film deposition film device, the gas or chemical is supplied by a gate valve 6 The direct material of the supplied gas or chemical or the direct material indirect material 15 formed by the material of the container is counted and recorded as a material model in the master database 13 for self-management. By modeling the material, it is immediately possible to determine whether the treatment 2 2 will affect the semiconductor manufacturing process by materials such as gases or chemicals. The wafer 1 7 is connected to the processing device 14 and is connected to the processing device 14 by a specific factor 14 - 1280603 (11), by the sensor/inspection device 9, according to the film thickness NG or the presence or absence of a pattern defect. , the phenomenon determination 2 3 on the wafer 1 is performed. This check result is a key resource for managing the wafers in batches or slices, and the information is collected by the computer 11 and supplied to the instant monitor/Q C for the determination process 24 . The computer 11 obtains quality information or device information or direct material indirect material information from the inspection device 19 and the processing device 14 or the computer 11a, by simulating the state of the processing device 14 or the batch moved by the processing device 14 The quality of the wafer 17 (for example, the film thickness) can fully grasp the quality of the semiconductor device even if the inspection of the intermediate processing is omitted. In addition, the computer 11 can feed back the quality information to the semiconductor manufacturing process for processing, or perform feedforward processing for the processing device (not shown and output) after the next project, and compare the batches for each processing. The quality information sent by the device on the side of the device and the speculative quality information sent by the computer 1 1 a simulate the semiconductor manufacturing process on the computer 1 to improve the accuracy of the quality information. Further, the computer 11 also manages the design information 25 of the reticle 20 (scale line) used in the lithography process, and detects the specific defect on the wafer by the instant monitor/QC determination process 24, It can be determined whether the processing mask 20 is poorly designed. As described above, the manufacturing system 1 of the semiconductor device according to the embodiment of the present invention, the process of the direct modeling material processing device 14 , the direct material indirect material 15 , and the wafer 17 constitutes the APC system of the computer 1 1 . Real-time quality management can be implemented, and TCAD (Technical Computer Aided 1280603 (12) Meter) or YMS (Product Rate Management System) can be implemented, and the final semiconductor can be predicted even in the intermediate processing project before the final project is completed. The advantage of the product rate of the device. Hereinafter, the features of the manufacturing system 10 of the semiconductor device according to the embodiment of the present invention will be described using the first to seventh embodiments. Fig. 2 is a model flow chart for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention. The manufacturing process of the manufacturing system of the semiconductor device 30 is performed by sequentially processing the wafers into the I process 42 and performing the processing of the processing device on the wafer as the semiconductor substrate or the surface thereof. The first processing item 43 of the processing, the second inspection item 44 processed by the line qC of the first inspection apparatus, the second inspection item 45 for performing the defect inspection processing by the surface pattern of the second inspection apparatus, and the wafer Or the film of the surface is subjected to the second processing project of the processing B of the processing apparatus, and the processing engineering or inspection of the third processing project, the fourth processing project, and the third inspection project are omitted. Engineering, until the batch completed in wafer state completes the project 47. The semiconductor device forming the plurality of wafers in this batch of completed projects is in the D/S (wafer sorting) processing project 48 (hereinafter, simply abbreviated as "D/S processing project"), and the product rate check is performed. The product rate of the semiconductor device of the device is checked. By this D/S processing, the electrical characteristics of the wafer are examined by a probe, and are classified as good or defective, and can be identified by adding a mark of the ink to the wafer of the defective product. In the first processing project, the wafer is transferred into the inside by the batch input process 4, and the processing is processed in accordance with the semiconductor manufacturing process sequence set in advance -16-1280603 (13) A. This processing A system can be applied to various processes such as film processing, oxidation treatment, electric treatment, wet treatment, CMP treatment, and welding treatment. For example, 'the first processing project in the processing A 4 is a film forming process'. A series of thin film processing such as gas injection, temperature management, pressure management, RF voltage processing, gas exhaust, etc. On the other hand, the device information of the gas pressure, the temperature, the RF voltage, and the spark of the processing device is sent to the self-diagnostic system 3, and the first processing project 43 is the CMP process. Monitor the amount of the honing agent, the number of revolutions of the honing table, and the deterioration state of the honing table, and apply the honing treatment of the wafer, the supply of the honing agent to the processing device, and the replacement period of the honing table. The device information 43a is sent to the self-diagnosis system 3 1. The self-diagnosis system 31 can detect the wafer in order to be instantaneous, and can be configured by a pressure detector, a temperature detector, a spark detector, or a stacked film thickness detector disposed in the processing device, or can be provided with a corresponding semiconductor manufacturing. The detector of the plurality of processes is configured to receive a detection signal indicating the state of the device of the processing device. In addition, the event information 4 3 b of the maintenance period, the cleaning period, and the part replacement period of the processing apparatus used in the first processing item 43 is sent to the self-diagnosis system of the processing of the processing of the processing of the processing. 3 4. Based on the event information 43b, it can be inferred which state (or characteristic) of the batch processed in the first processing item 43 at the current time point (instant) is continued by the second processing project 46. -17- 1280603 (14) The self-diagnostic system 3 1 measures and analyzes the inside of the processing device 14 in Fig. 1 at a special time interval (for example, one second interval) according to the semiconductor manufacturing process. The amount of material accumulated or accumulated or consumed 'generates an automatic repair request signal when the amount of the substance reaches a certain amount. This automatic repair request signal is sent to the warning device 32 as QC information 3 1 a. In the initial stage of the manufacturing process of the semiconductor device manufacturing system 30, in response to the automatic repair request signal included in the QC information 3 1 a, the warning device 32 automatically transmits the processing device 1 to the processing device such as the oxidation furnace in the first processing project 43 Repair timing instructions 3 2 a. The first processing of the processing A is exemplified as a case where the thermochemical reaction process is performed, and the inside of the oxidation furnace as the processing apparatus 14 is measured and analyzed according to a specific time interval (for example, a one-second interval). The amount of oxidized deposits, at which the oxidized deposit reaches a certain amount of accumulation, produces an automatic repair request signal. This automatic repair request signal is sent to the warning device 32 as the QC information 31a. The manufacturing system 30 of the semiconductor device responds to the automatic repair request signal included in the Q C information 3 1 a, and the warning device 3 2 is configured for the timing indication information 32a of the automatic repair of the oxidation furnace. Although the oxidizing furnace is configured to receive the timing information 32a for automatic repair, the automatic repair processing may be performed in the stage of the first processing operation 43 until the end of one unit of the semiconductor manufacturing process, at the current time point. After the batch processing of the wafer being processed is completed, the wafer is carried out of the oxidizing furnace, and the cleaning gas is introduced into the inside of the oxidizing furnace. In this case, the unloaded wafer is then subjected to online QC processing by the first inspection project 44 -18- 1280603 (15), and the QC information 44a of the film thickness information generated on the wafer by the packet 3 is sent to the parameter. Adaptation device 33. In the second inspection project 45, the second inspection project 45 checks the presence or absence of a pattern defect on the wafer, and the QC information including the defect inspection result is 5 5 . a is sent to the parameter adjustment device 33. In this "on-line QC", measurement of parameters in the thickness direction such as film thickness measurement of a film is mainly performed. In addition, the "defect inspection" mainly refers to the inspection of defects on a planar pattern formed by lithography. The parameter adapting device 3 3 adapts the model of the self-diagnostic system 3 1 described above and its parameters. The adaptation of the present embodiment means that the timing of the automatic repair request signal from the device information 43a of the processing device received by the self-diagnosis system 31 at a specific time interval (for example, one second interval) is changed to an appropriate one. The period or reconstitution (for example, 3 batches of continuous reception processing device poor signal, start to generate automatic repair request signal) tb. In the case where the model of the self-diagnosis system 31 and its parameters are not appropriate, even if the device information 43a contains improper parameters for the oxidation process of the processing device, the batch processing at the current time point processing ends. The processing device is carried out, and the inspection result of the first inspection project 44 enters the normal state. In addition, the inspection result of the second inspection project 45 also enters the normal state. Therefore, the inappropriate parameter in the device information 43a transmitted by the processing device itself is an error, and can be determined as a parameter having low reliability. In the present embodiment, in order to improve the accuracy of the device information 4 3 a including the improper parameter -19 - (16) 1280603, the batch of the wafer at the time when the inappropriate parameter is issued is checked for quality. The device information 4 3 a is determined to be consistent with the state of the wafer, and is configured by the parameter adaptation device 3 3 for feedback correction of the parameter 3 3 a of the self-diagnosis system 3 1 . Typically, the QC information 44a and the QC information 45a of the past ten batches of wafers can be obtained by the first inspection project 44 and the second inspection project 45, and the self-diagnosis system 3 is sequentially changed while comparing the improper parameters of the device information 43a. The parameter of the model of 3 is controlled by 3 3 a. For example, in the manufacturing system of the semiconductor device using the thin film processing apparatus, the film thickness inspection device may be used in the first inspection project 44, and the film thickness inspection may be performed, and the pattern defect inspection device may be used in the second inspection project 45 to apply the defect. Check, obtain the information of each inspection result, compare the improper parameters of the device information 4 3 a, and change the parameters 3 3 a of the model of the self-diagnosis system 3 1 to control. The self-diagnosis system 3 1 performs self-diagnosis of the processing device while correcting the parameters of the model of the self-diagnosis system 3 1 between the manufacturing systems of the semiconductor device. That is, the state of the monitoring device is monitored, and the QC information 31a with high accuracy is generated in response to the reception of the inappropriate signal. The QC information 3 1a is a warning device 32 that is instructed to send a warning to the downstream MES, and urges the automatic repair timing instruction information 32a to transmit the signal. The warning device 32 responds to the receipt of the QC information 31a, and provides warning information for the automatic repair timing indication information 3 2a of the maintenance instruction of the processing device. In this case, as the frequency of maintenance increases, the utilization rate of the manufacturing system 30 of the semiconductor device decreases, and in particular, the timing of the automatic repair refers to the correctness of the information 32a, which is of course the quality management and quantity. Production effects will have an impact. For example, in the case where the processing apparatus 14 shown in Fig. 1 is a thin film forming processing apparatus, the number of times of introduction of the gas inside the cleaning furnace can be made appropriate, and the number of cleaning can be reduced, and the quality can be prevented from being lowered, and the semiconductor package can be increased. The manufacturing volume. In addition, the warning device 32 responds to the reception of the QC information 31a, and transmits the maintenance information 3 2b to notify the operator that the automatic repair has occurred. For example, it is possible to perform a warning notification of a warning placed in the vicinity of the processing device in the clean room, or to monitor the monitor display maintenance screen 38 of the operator of the entire semiconductor manufacturing process in the clean room. Further, the warning device 32 can control the number of processes of the first inspection project 44 or the second inspection project 45 in response to the inspection frequency correction instruction information 33b received by another pipe, and can adjust the batch of wafers. Check the frequency. That is, the semiconductor manufacturing process follows the learning curve, the quality is stable, and the necessity of the immediate/full number of inspections becomes low, and the inspection frequency correction instruction information 3 3 b from the parameter adjustment device 3 3 is omitted, and the first inspection project 44 or The quality inspection of the second inspection project 45 automatically reconfigures the semiconductor manufacturing process, reduces the inspection process, and increases the yield of the wafer as the semiconductor device. Further, the parameter adapting device 3 3 generates a new defect discovery report information 3 3 c generated in a specific batch, and can report the intermediate engineering wafer to the defect discovery report portion 39 of the technician who is working outdoors in the clean room. The fact that new defects are discovered. -21 - 1280603 (18) On the other hand, the completion result/product rate collection unit 36 acquires the product rate information of the wafer of the D/S processing project 48 inspection batch completion project 47, for example, in determining the product rate. In the case of reduction, the quality management system is automatically strengthened immediately, and the product rate information 3 6a showing the reduced product rate is sent to the completion result/product prediction system 35. Completion of the results / product forecasting system 3 5 Instantly handle the quality management of the wafer, while comparing the previous product rate information with the product rate at the current time point. Information 3 6b, the tendency to predict product rate (increasing or decreasing). By transmitting the prediction information 3 5 a of the product rate indicating the tendency of the product rate to the parameter adjustment device 33 described above, the parameter adjustment device 33 can send the inspection frequency correction instruction information 33b to the warning device 32. The above-described inspection frequency correction instruction information 33b is automatically adjusted, and an example of the control method thereof is given. Typically, the inspection frequency can be automatically adjusted using the engineering capability index Cp of the processing device operating in the first processing operation 43. Here, the thickness of the wafer or the diffusion depth of the impurity or the etching rate is set as a target 値, and each variable is defined in advance. Storage: For this target, the upper limit specification Sii of the processing device is increased by a certain amount, and the lower limit specification S1 of the processing device for a certain amount is reduced, and the average value of the processing device of the average number of batch processes is 値X, The standard deviation D of the processing device indicating the deviation of each of the average measured turns is calculated. The calculation of the engineering capability indication Cp of the processing device is based on the upper limit specification SU, and the engineering capability index Cp is: (Su-x) / 3D Relationship, in addition, according to the lower limit specification S1, the engineering capability index Cp has a relationship of (x-Sl) / 3D. -22- 1280603 (19) The aforementioned engineering capability index Cp, for example, in a state below 1 · 3 3 (Cp < 1.33), the inspection frequency is increased to constitute a semiconductor manufacturing process. In addition, the engineering capability index Cp is, for example, above 1.33, and is lower than the state of 1.67 (1 · 33 S Cp When <l · 67 ), the inspection frequency is maintained and the control is not changed. Further, the engineering capability index Cp is, for example, one. 6 7 or more status (. 1 . In the case of 67 S Cp ), the frequency of inspection is reduced to form a semiconductor manufacturing process, and automatic control can be performed in this way. Further, the inspection result of the film thickness of the past 10 times or the diffusion depth of the impurity or the etching rate of the batch carried out by the processing apparatus may be based on the inspection average 値X of the processing apparatus and the upper limit specification Su of the processing apparatus. Or the lower limit specification S1 of the processing device, and calculate the engineering capability of the processing device. number. In this case, the inspection frequency is changed to 2 times, 1 time, and 目前 of the current time point even if the engineering capability index Cp is corresponding.  Five times, it is also possible to perform semiconductor manufacturing process management equivalent to the above-described control of the inspection frequency. Further, as an example of the oxidation furnace of the processing apparatus, when the film thickness of the target crucible is 1 〇 nm, the control of the inspection frequency with the upper limit specification Su being 1 2 nm and the lower limit specification S 1 being 8 nm can be performed. . Further, the completion result/product rate collection unit 36 sends the product rate information 36 to the GDS data retrieval requesting unit 37, urging the removal of a portion of the mask information used for the lithographic data used in the lithography project. The signal adaptation device 33 is sent to the aforementioned parameter. For example, in the case where the defect portion on the wafer of the product ratio of the left and right semiconductor devices shows locality, there is a case where the adjustment effect of the model of the self-diagnosis system 31 is favorably applied. -23- 1280 603 (20) (Embodiment 2) An operation flow of the manufacturing system 30 of the semiconductor device according to the second embodiment of the present invention will be described with reference to Fig. 2 . In addition, with the aforementioned! The description of the components or engineering in which the embodiment is repeated is omitted. The manufacturing system 30 of the semiconductor device includes a first processing item 43 for processing a wafer loaded by the first processing item 43 and a first inspection for performing inspection of the wafer processed by the first processing item 43. Project 44, and the second inspection project 45 that performs the inspection of the wafer of the first inspection project 44, and the second treatment worker 46' that has passed the wafer of the second inspection project 45. And the inspection project, the completion of the batch completion of the semiconductor device 47 in the wafer, and the inspection of the D/S processing of the wafer. The semiconductor device manufacturing system 30 further includes a self-diagnosis system 31 of the self-diagnosis first processing project 43, a self-diagnosis system 46 self-diagnosis system 34, and a product rate obtained by the D/S processing project 48. The completion result/product rate collection unit 3 6 of the information 4 8 a is connected to the completion result/product rate collection unit 3 6 to predict the completion result of the semiconductor device/the completion result of the product rate/product rate prediction system 35. The manufacturing system 30 of the semiconductor device is inspected by the D/S processing project 48 to complete the wafer of the completed batch 47 by the aforementioned batch, and the product rate information is sent to the completion result/product rate collecting unit 3 6 . The new product rate information 3 6b is sent to the completion result/product rate prediction system 35. Further, the manufacturing system 3 of the semiconductor device reflects the state of the manufacturing process of the upstream semiconductor -24- 1280603 (21) in the downstream semiconductor manufacturing process, and predicts the product rate of the semiconductor device in the wafer each. In other words, the phenomenon of managing the processing device of the configuration project, the maintenance period of the replacement film forming processing device, the cleaning period of the film forming processing device, and the event information of the part replacement period of the thin processing device are transferred to the lower flow engineering (2) The self-diagnosis system 3 of the etching processing apparatus for the semiconductor manufacturing process of the other processing operation 46 can immediately reverse the semiconductor manufacturing process performed by the second processing unit 46 in the state of the thin film forming processing apparatus operated in the fourth step 43 . Further, the self-diagnostic system 3 1 disposed in the upstream project is disposed in the downstream self-diagnosis system 34, and transmits the batch information 49 on the quality management of the wafer processed by the borrowing device. The self-diagnostic system 34 systematically evaluates the information 43b and the batch information 49 in a comprehensive manner, and whether the batch of the wafer in the second processing project 46 passes through the state of the processing device is good, and the state of the upstream device is deteriorated. The upflow project can perform high-precision self-diagnosis processing based on the device information 46a that is immediately sent from the processing device that is processed by the second processing project 46 in accordance with the customer-determined quality such as the number comparison. In addition, the self-diagnosis system 34 uses the event information 4 3 b, the message 49, and the processing device information 46a that executes the process in the second process 46 to calculate the wafer that has passed through the second process 46 (for example, 10%) After the product rate, the calculation result is sent to the prediction unit 40. A batch of the consumption film formed in the upstream process is processed in the manufacturing process 1 to be processed in the event connected to the event processed, or the process B is judged to implement the batch product rate to the delivery-25- 1280603 (22) In this case, the defect portion of the improper process based on the first processing item 43 cannot be repaired in the second processing project 46, and the progress of the flow processing in the semiconductor manufacturing process is further reduced. Therefore, the delivery prediction unit 40 can predict or determine the number of semiconductor devices that will eventually become good in the middle of the semiconductor manufacturing process. The delivery forecasting unit 40 is capable of automatically executing the wafer input amount control express application processing 4 for a production planning computer (not shown) for creating a manufacturing system of the semiconductor device manufacturing system 30. In the final inspection of the wafer, the defective product can be used to flow the repairable batch to the wafer engineering at an early stage, and the cash flow of the semiconductor manufacturer of the enterprise can be expected to be maximized. (Third Embodiment) The manufacturing system 51 of the semiconductor device described in the third embodiment can cope with various processing devices for processing and processing the semiconductor device. For example, it is of course applicable to a film forming processing device that can perform a film forming process. The diffusion processing device for the impurity is a film deposition film device of CVD (Chemical Weather Deposition), a reflow (melting) PSG film, a BSG film, a BPSG film (insulation film), or the like, and a CVD oxide film. a thermochemical reaction treatment device such as a density amount, a thickness of a deuterated metal film (electrode), a sputtering device or a vacuum vapor deposition device for depositing a metal wiring layer, a plating treatment device for electroplating, a CMP treatment device for chemical mechanical honing of a semiconductor substrate, Dry or wet etching processing apparatus for etching the surface of a semiconductor substrate, spin coating processing apparatus related to lithography processing, exposure of a stepper, etc. -26- 1280603 (23) Processing apparatus, a chip-shaped semiconductor device to be cut The electrode ^gg is placed at various semiconductor manufacturing processes such as the wire bonding device of the lead frame. Fig. 3 is a schematic block diagram of a manufacturing system 5 1 of a semiconductor device according to a third embodiment of the present invention. The manufacturing system 5 1 of the semiconductor device includes, for example, an oxidation furnace 54 that executes a process processing unit using a thermal process of thermochemical reaction, an oxidation furnace controller 52 as a process control unit control device, and an oxidation furnace controller 52. The operation and non-operation, and the operation state of the computer 1 1, and the oxide film thickness of the oxide film on the wafer between the computer 1 1 and the oxidation furnace 5 4 is calculated as an instant simulator 53. Further, in the present embodiment, the oxide film thickness instant simulator 53 has a structure similar to that of the oxidation furnace controller 52, but may be oxidized. The interior of the furnace controller 52 is integrated as part of its function. The oxide film thickness instant simulator 53 is responsive to the start signal sent to the oxidation furnace 54 by the oxidation furnace controller 52, and the internal oxide film thickness calculation unit 56 displays the inside of the furnace which is immediately sent by the oxidation furnace 54. The internal information of the temperature or pressure of the device begins to calculate the oxide film thickness of the wafer loaded into the oxidation furnace 54. The calculation of the thickness of the oxide film is immediately sent to the computer 1 1, and is used for the production management of the factory using the ME S. The computer system transmits the control signal to the oxidation furnace controller 52 in accordance with the control information of the MES of the internal database, which is calculated in the thickness of the oxide film and reaches a certain thickness of the oxide film. The oxidation furnace controller 52 responds to the control signal to send a stop signal to the oxidation furnace 54 to stop the oxidation treatment. The stop signal is monitored by the oxide film thickness calculation unit 56 of the -27-1280603 (24) of the oxide film thickness instant simulator 5 3, and the oxide film thickness instant simulator 5 3 can be immediately detected. The timing at which oxidation treatment stops. In the manufacturing apparatus of the conventional semiconductor device, the oxide film thickness calculation unit does not monitor the stop signal of the stop of the physical processing, and the internal information of the device at the current time point is the internal state of the furnace after the stop signal is sent, and Can't do it. However, the manufacturing system 51 of the semiconductor device of the present embodiment shown in FIG. 3 monitors the stop signal sent from the oxidation furnace controller 52 by the oxide film thickness simulator 51, and oxidizes it according to the oxidation process. At the time of the stop, the internal information of the device showing the decrease in the internal temperature or pressure of the oxidation furnace 54 can continue to process the oxide film thickness calculation in real time. The oxide film thickness calculation unit 56 starts the calculation of the oxide film thickness of the wafer formed inside the oxidation furnace 54 after receiving the start signal transmitted from the oxidation furnace controller 52, in accordance with the internal information of the device. After the process, the stop signal sent by the oxidation furnace controller 52 is received, and the calculation of the oxide film thickness is continued immediately after a certain period of time. The calculation of the oxide film thickness of the oxide film thickness calculating unit 56 is performed by the time point calculated by each time point sent by the oxidation furnace 54. The instant is followed by the experimental plan. D Ο E (experimental setting s ten method) f 旲 type 5 9 'From the start of the signal reception time point, the stop signal is received after the oxidation process is completed, and the integration process is gradually performed during the specific time period. The thickness of the entire oxide film of the wafer. In addition, the manufacturing system 51 of the semiconductor device by the oxide film thickness instant simulator 53 differs from the conventional manufacturing device in that the computer 11 attaches the processing room N 0 information to the processed EES data 60, for example, the oxidation furnace 1280603 (25) In the case of the calculation of the information, the situation is the same as that of the processing room in the interior of the processing room, so that the EES data 60 corresponding to each of the multiple processing chambers can be oxidized. The accuracy of the film thickness. Moreover, it is advantageous to perform the real-time simulation of the thickness of the oxide film in the batch processing. In this embodiment, the time passing through the oxidizing furnace 54 is added to the element. The thermal chemical reaction process, for example, information on the event of the replacement of the dimension of the consumables or the cleaning period of the oxidizing furnace, and the subsequent elapsed time, by the oxide film thickness instant simulator 5 3 The integration function for integration processing. Therefore, precise quality management can be performed as compared with a conventional semiconductor device manufacturing apparatus that processes all the batches under the same semiconductor manufacturing process conditions. Further, although the manufacturing system 5 1 of the semiconductor device is described as an oxidizing device, the present invention is not limited to the oxidizing treatment. For example, a semiconductor device manufacturing system having an instant simulator function such as "endpoint monitor + etching rate estimation" exemplified as a component of the instant simulator of FIG. 3 can be constructed for a processing device such as an etching apparatus. . (Fourth Embodiment) Fig. 4 is a flow chart showing a model of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. The first processing procedure 43 of the processing A, the first inspection project 44 for performing the online QC, the second inspection project 45 for performing the defect inspection, the second processing project 46 for performing the processing B, the defect discovery report portion 39a for the technician, QC information 44a, 45a -29- 1280603 (26) The maintenance amount $2b is the same as that of the first embodiment described above, and the overlapping description will be omitted. The manufacturing system of the semiconductor device shown in the present embodiment is constructed by diagnosing a model of each processing device, various sensors, and self-diagnosis system by measuring the difference between the quality of the official and the actual measurement. Quality estimation department 6 1 series by the first. 1 Processing Engineering 43 The processing device performing the process accepts device information 43 a (for example, EES data) including a plurality of variables X, according to the model of the self-diagnosis system represented by the function f and its parameter a, parameter b and included in The variable X of the plural number of the device information 43a received immediately is calculated, and the estimated quality data 6 1 a of the output Y data of the plurality of batches included in the thermochemical reaction process at the time point of the target is calculated, and the estimated quality data 6 1 is calculated. a is sent to the comparator 6 2 acting as an abnormality detecting device. Here, it is estimated that the quality data 6 1 a includes the in-plane distribution of the oxide film thickness of the wafer or the average thickness of the oxide film thickness, and the D standard data showing the standard deviation of the deviation of the oxide film thickness. The computer 11 connected to the control of the ME S of the comparator 62 provides quality information of the instant semiconductor device. The computer 11 is connected to a line QC processing device that executes the first inspection project 44 or a defect inspection device that performs the second inspection project 45, and compares the estimated quality data 6 1 a with the QC information of the first inspection project 44 44a or the difference information of the QC information 45a of the second inspection project 45, the online QC processing device or the defect inspection device outputs the optimization information 64 of the inspection frequency of the first inspection project 44 or the second inspection project 45, which may be omitted. The first inspection project 44 or the second inspection project 45 can shorten the manufacturing period of the semiconductor device by -30-1280603 (27). The quality estimation unit 6 1 receives, for example, a model and parameter information 63 based on the Mahalanobis distance stored as the quality management data of the QC database 65, by changing over time. The first processing item 43 performs calculation processing of the state inside the oxidation furnace of the process to calculate the estimated quality data 6 1 a. It is assumed that the quality data 6 1 a is sent to the comparator 62 as described above, but is also sent as feedback information 6 1 a to the oxidation furnace which is in parallel with the first processing project 4 3 as a feedforward information. 6 1 c is sent to a semiconductor processing other than the oxidation processing process such as an etching processing device or a lithography processing device which is located in the second processing project of the first processing project 43 Process processing device. The comparator 62 receives the estimated quality data 61a from the quality estimation unit 61, the QC information 44a from the inspection device that executes the first inspection project 44, and the QC information 45a from the inspection device that implements the second inspection project 45. And the maintenance information 32b from the warning device 32 is configured. In this manner, the comparator 62 receives the processing information from the device information 4 3 a of the quality estimation unit 6 and the estimated quality data 61 a of the model and parameter information 63, and can perform the process in the first inspection project 44 and the second inspection project 45. After the inspections of the various inspection devices are processed, the parameters of the self-diagnosis system can be estimated while comparing the estimation and measurement of the quality management. That is, while the parameter of the estimated self-diagnosis system is approximated to the actual measurement, the comparator 62 sends a parameter a 'parameter b of the self-diagnosis system to the quality estimation unit 6]. -31 - 1280603 (28) The estimated quality Ys outputted by the quality estimation unit 61 is fed back to the semiconductor manufacturing process of the first processing project 4 3, and the quality is stabilized, and the estimated quality Ys is fed forward to the second In the processing project 46, the parameters of the processing device for performing the processing of the second processing project 46 and the estimated quality Ys can be determined in advance, and at the current time, the batch in the first processing project 43 is moved into the second processing project 4 The stage of 6 can be processed according to the process of speculative quality Ys. Further, as described above, the comparator 62 acquires the estimated quality data 6 1 a and the QC information 44a and 45a which are actual measured values, and the stage of the separation between the estimated 値 and the measured 値 is determined, and the first processing item 43 can be determined early. The processing device, the inspection device of the first inspection project 44, and the inspection device of the second inspection project 45 are all improperly generated, and the quality management state of high precision cannot be performed. The comparator 62 detects the display based on the estimated quality data 6 1 a! When the processing device of the processing project 43, the inspection device of the first inspection project 44, or the inspection device of the second inspection project 45 generates an improper signal, the device/sensor abnormality detection signal 62a is sent to the warning device 32 and the operation. The monitor of the staff, the semiconductor manufacturing process is stopped, and the operator's maintenance instruction screen 38 displays the quality management information at the current time. (Fifth Embodiment) Fig. 5 is a model flow chart for explaining a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. Batch input project 42, first processing project 43, first inspection project 44, second processing project 46, batch completion work - 32 - 4 1280603 (29) Process 47, D/S processing project 48, quality estimation unit 61 The same as the above-described first embodiment, and the overlapping description will be omitted. According to the manufacturing method of the semiconductor device of the present embodiment, the first processing item 43 which is formed by the thin film formation processing, and the second processing which is disposed under the first processing item 43 are provided on the semiconductor manufacturing process. Project 4, and inspection of the D/S treatment of the device performance and product rate of the semiconductor device that has been completed in the batch, 48 ° processing processing A, the first processing project 43 is a device that executes the processing processing device The information 43a is sent to the quality estimation unit 61, and the quality measurement unit 61 transmits the estimated quality data 6 1 a to the estimated quality management unit 66 based on the device information 43 a . After the processing of the batch of the processing A is completed at the current time, the estimated quality management unit 66 obtains the result of the online QC processing of the wafer by the first inspection process 44 as the comparison data 67, and can be compared with the estimated quality. The data 6 1 a comparison can determine the accuracy of the speculative quality material 6 1 a. For example, the estimated quality management unit 6 6 compares the estimated quality data 6 1 a estimated by the quality estimation unit 6 1 with the measured actual measurement in the first inspection project 44, and sequentially implements the correlation between the device information 4 3 a and the actual measurement. . Here, the related processing in the present embodiment means that the estimated quality data 6 〗 〖 estimated by the quality pushing unit 61 is approximated, and the device information 43a obtained in each batch is fed back to the first processing item 43. In the semiconductor manufacturing process, in the process of processing the next batch, the correction device can be close to the actual measurement. Therefore, by the correlation processing, it is possible to appropriately configure the flow of the flow of the flow to the location of the point-of-sales site. -33- 1280603 (30) Correction of the estimated quality data 6 1 a of the quality estimation unit 6 1 The parameters of the model. For example, the deviation between the estimated quality data 6 1 a and the actual measurement after the correlation processing of 10 batches is reduced to the extent that the first inspection project 44 (online QC) or the third inspection project 44c (online QC) becomes unnecessary. For the connection in push. The process and device simulation device 69a of the quality control unit 66 transfers the product rate information of the batch of the processing A in the first processing project 4 3 . The quality control unit 66 can predict the product rate of the batch processed in the processing project 43. Similarly, the second processing item 46 of the processing B sends the device information for performing the processing of the second processing item 46 to the quality estimating unit 68, and the quality estimating unit 68 uses the device information as the estimated quality data based on the received device information. The QC information 68a is sent to the speculative quality management unit 66a. When the process of the batch of the processing b is completed at the current time point, the estimated quality management unit 66a obtains the QC information 44d which is the inspection result data of the wafer of the third inspection project 44c, and obtains the comparison data 67a. Can be compared with QC Information 68a. It is assumed that the Q C information 6 8 a estimated by the quality comparison unit 6 6 a and the q c information 44 8 measured by the third inspection project 44 c are successively executed in association with the device information and the actual measurement. For example, the deviation between the QC information 68a and the actual measurement after the processing of the batch is performed is to check the third inspection project 4 4 c of the wafer carried out by the second processing of the processing B. The line Q c ) becomes unnecessary, and the product rate information of the batch of the processing B is transferred to the second processing project 46 for the process and the device connected to the estimated quality management unit 66a -34 - 1280603 (31) It is assumed that the quality management unit 66a can predict the product rate of the batch processed in the processing project 46. The process and device simulation device 69a is based on the product rate information of the first processing project 43 of the upstream project and the product rate information of the second processing project 46 of the downstream project. The semiconductor manufacturing process and the simulation of the device as a semiconductor device are carried out, and the estimated product rate information of each batch is sent to the device performance rate prediction unit 7〇a of the next segment. The device performance product rate prediction unit 70a predicts the product rate of the semiconductor device based on the information estimated by the estimated quality management unit 66 and the estimated quality management unit 66a. However, in the present embodiment, the collection is performed. The QC information 44a of the first inspection project 44 of the online QC processing and the QC information 44d of the third inspection project 44c can predict the product rate of the semiconductor device at the intermediate processing stage based on the actual measurement. The process and device simulation device 69 is combined with the QC information 44a of the first inspection project 44 disposed in the upstream project (or the former project), and the QC information 44d of the third inspection project 44c disposed in the downstream project (or the latter project). The simulation of the process and the device is carried out, and the product rate information of the simulation result is sent to the device performance product rate prediction unit 70 of the next segment. The device performance product rate prediction unit 70 transmits the product rate prediction information 72 of each lot to the device performance product rate prediction unit 70a described above. The device performance product rate prediction unit 70a compares the estimated product rate information and the product rate prediction information 72, and by implementing the product rate prediction process 75 of the semiconductor device, it is possible to provide a higher-precision product rate prediction, and the product rate prediction process 75-35 - 1280603 (32) Line, which can be reset (for example, the omission or partial omission of the inspection) by the frequency of the QC on the line of the first inspection project 44 and the third inspection project 44c. Further, the manufacturing system of the semiconductor device according to the present embodiment predicts the product rate of the semiconductor device based on the estimated quality of the device information of the processing devices disposed in the respective processes of the first processing item 43 and the second processing item 46. At the same time, based on the inspection results of the wafers carried out by each processing project, the product rate of the semiconductor device is predicted, but it is also possible to parallel with the predicted product rate, The D/S processing project 48 of the probe inspection device can determine the device performance product rate. The comparison process 71 is based on the product rate measured by the D/S processing project 48 and the product rate of the device performance product rate prediction unit 70, and the difference can also correct the simulation accuracy of the device performance product rate prediction unit 70, and the comparison processing 7 3 The product rate measured by the D/S processing project 48 and the product rate of the device performance product rate prediction unit 70a may be corrected by the difference between the device performance product rate prediction unit 70a. That is, the parameters of the simulation model of the process and device simulation devices 69, 69a can be appropriately corrected. According to the manufacturing system of the semiconductor device shown in this embodiment, according to the product rate of the actually-measured semiconductor device, the semiconductor manufacturing process can be repeated while correcting the product rate prediction, and the product rate prediction with high precision can be performed, for example, The NPW (product-free wafer) which is a wafer for quality management can be omitted, and the inspection project as an online QC can be omitted, and the advantages of the batch manufacturing simulation of each batch of semiconductor manufacturing can be performed. (Embodiment 6) - 36 - 1280603 (33) Fig. 6 is a view showing a method of defining a manufacturing apparatus for causing a defective batch in the semiconductor device according to the sixth embodiment of the present invention. Although the oxidizing furnace is used as an example of the processing of the semiconductor device in the figure, the processing apparatus used in the first processing project 43 of the present invention is not limited to the oxidizing furnace, and may of course be applied to the processing of other semiconductor processes. Device. For example, in the first processing project 43 of the oxidation process, an oxide film is formed on the wafer by a thermochemical reaction process in a processing chamber inside the processing device. Further, the processing device used in the first processing item 43 instantaneously transmits pressure, temperature, voltage, and valve opening to the measuring device 7 by a plurality of detectors disposed inside the processing chamber connected to the measuring device 7 7 . Device information such as. The measuring device 7 determines the state of the wafer in the semiconductor manufacturing process based on various kinds of detection data received. For example, by collecting a plurality of data from a processing chamber inside the processing apparatus of the semiconductor manufacturing process in which the first processing item 43 is executed, it is possible to define a batch of wafers processed by each semiconductor manufacturing process. Further, the measuring device 77 has an instantaneous data collecting capability, for example, converting nine kinds of analog data simultaneously detected at a specific time interval into digital data, and recording and analyzing the digital data in a time series for each batch. The histogram in the center of the figure is stored in time series in the state inside the processing chamber collected by the measuring device 77, and the time series data of the memory is converted into a scalar and displayed as a detection 値79 (detection). . It can be confirmed on the display that the test can be controlled by the low-wave high-pitched and high-wave high-control processes that can be controlled by the process -37- 1280603 (34) Non-control 値8 0 (uncontrollable). The measuring device 7 7 displays the number information of the inside of the feature processing 8 1 (regionalized) processing chamber based on the processing chamber curve of the specific processing time of the scalar corresponding processing project 43 indicated by the uncontrolled 値80. This feature quantization 81 shows whether or not there is a defect in a particular location of a batch of wafers in process. For example, depending on the control 値80, the parameter A of the feature quantity (or signal) that is inside the processing chamber is regarded as 0. 78. The parameter B is used as a calculation process, and the feature quantity database not recorded in the digital information recorded in the internal or external portion of the measuring device 7 is accessed, and the same degree of processing of the defect identification processing is performed 82. knowledge). The feature amount used in the same degree of processing 8 2 described above is managed in the form of the correlation table 83 in the figure, and the correction of the device state of the furnace processing project 43 can be used (correcti, for example, corresponding to the left side of the relevant table 8 3 The field of the right side of XI indicated by the field of the defect parameter number shown in the field (Α = 0·8/Β = -0·6), and the parameter of the operation processing of the measuring device 77 Α0. 78, parameter Β-0. 63 is treated to the same degree. The batch state of the wafer is the same as the defect shown on the upper left. In the same way as the dog state 84, the majority of the good number is recorded in odd and even numbers. The processing information or TEG information of the statistical semiconductor manufacturing process and the classification information of the semiconductor device may also be included in the data. , the status of the parsing, with the element information, the second test element. 63, and the feature quantity is carried out as a result of the number of defects, such as the number of defects, such as the number of defects in the case of the number of defects, and the batch of wafers and materials including the inspection history -38- 1280603 (35) In addition, by the processing of the wafer defined by the characteristics of the right side of the χ 1 of the left side of the corresponding table, in the processing project 43 of the oxidation engineering, there will be a plurality of processing chambers. In the case where the difference between certain EES signals is detected, the speculative failure mode of the processing device can be defined. Defects in the form of defects indicated by the left side of the relevant table 8.3. The code is X2 and is processed to the same extent as the batch state of the wafer of 82. , after the parameter A as the feature quantity of the feature quantity database, it is 0. 2, the parameter B is 〇.  The number of information in the number of digits below 7 is read out, and the information is approximated by the data of the feature quantization 81. The batch status of the wafer is based on the batch shown in the middle of the figure. State 8 5, the processing project is evaluated in a random state, statistical data on which a small number of wafers are moved out. Similarly, the batch state of the wafer of the same degree 82 is treated by the X3 of the defect classification number of the defect form shown in the left side column of the relevant table 83, as a feature of the memory of the feature quantity database. The parameter A of the quantity is 0. 4, the parameter B is -0 · 3 decimal point below the number of digits 値 information is read, compared with the material of the feature quantization 8 1 , the batch state of the wafer According to the batch status shown in the middle left of the figure, there are a small number of wafers in the first half of the batch, and the statistical data of the batches of the majority of the wafers in the second half of the batch are evaluated and processed. In addition, when the wafer corresponding to the batch of the defect classification number of X3 is gradually increased in temperature in the furnace, for example, when the temperature of the furnace is gradually increased, the repair of the defect can be improved. As described above, the measuring device 77 detects the state of the processing chamber of -39-1280603 (36) of the processing project 43 in the same manner, and performs the feature quantization 8.1, and performs the same degree of processing successively 8 2, so that the processing is performed by the same degree. 2 The stage of finding a batch of bad majority can automatically define the treatment project that becomes a bad cause. Therefore, when a bad majority is found, the processing of the defective batch is stopped immediately. The report operator is constructed to perform maintenance. In addition, the feature quantization 8 1 is a new form of the "new mark" shown in the lower right of the batch distribution map, and the feature quantity is stored for the aforementioned feature quantity database. Displays information on the batch status of the wafer. (Embodiment 7) Fig. 7 is a model flow chart for explaining a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention. Batch input project 42, first processing project 43, first. Inspection project 44, third inspection project 44c, second treatment project 46, batch completion project 47, D/S treatment project 48, quality estimation unit 61, estimation quality management unit 66, detection 値7 9, The non-control 値 80, the feature quantization 81, the same degree processing 82, the correlation table 83, and the new symbol are the same as those of the above-described embodiment, and the overlapping description will be omitted. The manufacturing system of the semiconductor device is such that the wafer 1 7 b corresponding to the defect portion 8 4 b associated with the information of the known feature quantization 81 or the defect parameter XI, χ 2, X3 of the wafer 17c having the defective portion 84a The feature number of the classification number and the complex number is stored in the feature quantity database, and the batch of the feature quantization 81 is subjected to the same degree of processing 8 2 to find a bad batch, even if the same defect portion 8 4 a exists, As an unknown form of failure, there are also difficulties in batch processing, batch elimination and maintenance for wafers of 1 7 a. On the other hand, in the present embodiment, the processing device that performs the processing of the processing project 4 transmits the device information collected in real time to the quality estimation unit 6 1 corresponding to each batch, and then the downstream process is completed, and the batch is completed. Engineering 4 7 wafer 1 7 a is checked by D / S processing project 4 8 'to define the final. Defect portion 84a. D / S processing project 48 8 memory or output batch number, the address of the defect part, the manufacturing system of the semiconductor device uses this batch number as a clue to search and process the processing A of processing A of this batch The device information of the device (for example, referring to Fig. 4a of Fig. 2) causes the quality speculating unit 61 to monitor and control the retrieved device information 4 3 a as bad batch information. The parameters inside the quality estimation unit 61 are automatically updated. As described above, the quality management unit 66 receives the estimated quality data from the quality estimation unit 61, and estimates the product rate of the semiconductor device. In the semiconductor manufacturing process after the current time point, the semiconductor device manufacturing system can be used early. The production line excludes batches having a defect form such as wafer 17a, which can effectively prevent the consumption of unnecessary chemicals and the like. In addition, the manufacturing system of the semiconductor device can of course also automatically register the feature quantity information of the newly found bad form as the defect classification number X4 of the defect parameter in the correlation table 83" in the feature quantity database 0 (8th) (Embodiment) As shown in Fig. 8, the semiconductor package 14a of the eighth embodiment of the present invention is placed on the circle 1 19b, and the electric power of the inspection process is Self-information, 1 7a~ Checking the results in the circle. The manufacturing system of the wafer is equipped with: processing device for processing wafer 7 & processing device 14b for processing wafer 17b, and processing wafer i7c device 14c And the processing device 14d for processing the wafer 17d, and the self-diagnostic devices 5a to 5d for setting the processing devices 14a to 14d (1, and the databases 13a to 13d for the respective diagnostic devices 5a to 5d, and the inspection crystal 7a) The inspection device 19a, the inspection device for inspecting the wafer 17b, the inspection device 19c for inspecting the wafer 17c, and the inspection wafer i7d inspection device 19d are connected to the self-diagnostic devices 5a to 5d, and are processed by the respective devices 14a to 14d. Each wafer i7a The estimated quality of the brain is 1 to 17d. The self-diagnostic devices 5a to 5d used in the eighth embodiment can be composed of the hardware resources and the cooperative software of the self-diagnosis system 11a used in the first embodiment. Therefore, the diagnostic devices 5a to 5d of the self-diagnostic system are self-diagnosed by the device of the receiving processing device. The computer 1 1 is connected to the self-diagnostic devices 5 a to 5 d, and the estimated quality of all the wafers 1 7d is memorized. In the memory device 12, in addition, in each sequence, the inspection results of the selected batch of wafers are received by the batches of crystals sent from the inspection devices 19a to 19d, so that the inspection according to the inspection is performed. The quality 値 (for example, 'film thickness, etching rate, diffusion of impurities, melting state') corresponds to the batch number and wafer number, and is recorded in the record 12. With the quality management of the computer 11, there are multiple numbers in the selected batch. In this case, the inspection devices 19a to 19d only inspect the representative wafer 'to make the inspection - 42 - 1280603 (39) the result of the inspection corresponds to the batch number, the representative wafer number, and the computer 1 1 receives the information. Speculated to be The representative wafer has the same quality, and the computer 11 makes it correspond to the batch number and the wafer number, and each batch and the wafer are quality-managed. Therefore, the computer 11 uses the APC and the MES which are stored in the main database 13 The data is managed to manage the entire manufacturing system, and different processes are performed for the plurality of processing devices 14a to 14d. For example, the processing device 14a performs an oxide film forming process for the wafer 17a, and the processing device 14b performs an etching process for the wafer 17b. The processing device 14c performs an impurity diffusion process on the wafer 17c, and the processing device 14d performs reflow (or melting) control on the wafer 17d, for example. However, although the processing devices 14a to 14d shown in the drawings are simplifications, four are exemplified, but the manufacturing process of the current LSI can be easily understood. Generally, the manufacturing system of the semiconductor device is provided with a plurality of processing devices of the same type. The overall configuration has more than 10 processing devices. Each of the processing devices 14a to 14d outputs device information indicating an internal state through various sensors. For example, if the device is a plasma processing device, the pressure inside the processing chamber, the temperature, the high frequency power, and the high frequency impedance are matched. The device information determined by each process such as the capacitor 値 and the flow rate of the gas introduced into the processing chamber is output to the self-diagnostic devices 5a to 5d which are individually provided. The self-diagnostic device 5a is connected to the database 13a for storing the device information, and the processing device 14a for processing the wafer 17a by the ESS processes the device information, and calculates the estimated quality of the corresponding wafer 17a based on the device information (for example, When the processing device 1 4 a is an oxidizing furnace, the film thickness is formed on the wafer 1 7 & -43 - 1280603 (40), and the estimated quality is sent to the same wafer 1 7a of the computer 11 in the data. Library 1 3a memory speculates quality 値. Further, for example, if the processing device 14a is an oxidizing furnace, the quality 値 means that the device received by the processing device 14a is modeled into a film thickness (for example, Ye = aX + b ), and is thick.値Y e is the estimated thickness of the film formed on the wafer 1 7 a. X can be the temperature of the heater or the flow of the gas. The model of the memory film thickness of each device can be modeled. The self 5a inputs the device information into the model of the film thickness to calculate the 値. The self-diagnostic device 5b is connected to the storage device information 13b, and the information of the processing device 14b of the wafer 17b is processed by the ESS, and the push of the corresponding wafer 17b is calculated based on the device information (for example, when the processing device 14b is a dry etching device) In order to etch the speculative quality 値 to the computer 1 1 , the corresponding wafer database 13 3b stores the estimated quality 値. The self-diagnostic device 5 c is connected to the save device information 13c, and the wafer 17c is processed by the ESS. The processing device 14c information 'calculates the corresponding wafer 1 7c according to the device information (for example, the processing device 14c is set to be a diffusion furnace, which is an impurity level), and sends the estimated quality to the computer 1 1 , 17c In the database i3c, the quality of the device is estimated. The self-diagnostic device 5d is connected to the storage device information 13d' when the processing device Md for processing the wafer 17d by the ESS is used. The library 1 3 a diagnostic device speculates the quality of the database receiving device to measure the quality rate), and the data quality of the database receiving device is measured in 1 7b. The device 1280603 (41) information, based on the device information, calculates the estimated quality 对应 of the corresponding wafer 17d (for example, if the processing device 14 d is an annealing furnace, the melting state of the insulating film), the estimated quality is transmitted. At the same time as the computer 1 1 , the estimated quality 记忆 is stored in the database 13 3d corresponding to the wafer 1 7d. Referring to FIGS. 8 and 9 , in the manufacturing process of the wafer, the etching is taken as an example to describe the manufacture of the semiconductor device. In the manufacturing system, the inspection quality 値Y q of the range of the expected 値 is extracted, and the estimated quality 値Y e and the inspection quality 値Y q are compared, and the model of the estimated quality 値Ye is updated along the next flow. The term "expected 値" means that the inspection quality 値Yq stored in the past of the memory device 12 is time-series, and the tendency to check the quality 値Y q is calculated, and the quality of inspection can be appropriately expected at the current time. (Re-inspection flow) Hereinafter, the processing device 14a, the processing device 14b, the processing device 14c, and the processing device 14b of the dry etching device in the processing device 14d will be described as an example. (a) In the start step 90 (hereinafter, the step is abbreviated as "S"), the reception check device 19b periodically checks the inspection result of the wafer 17b processed by the processing device 14b, and moves to the stage. Abnormal check S 9 1. The computer 1 converts the inspection result into the inspection quality 値γ q, compares the inspection port α and the memory in the memory device 12, and determines whether the inspection quality 値Yq is abnormal. In the case of abnormality determination, S 92 minutes is measured again to send a re-measurement command to the inspection device 1 9 b. 1280603 (42) (b) Inspection device 1 9 b Re-measure S 9 2 Re-measure wafer 1 7b, re-measure the re-measurement result to computer 1 1 ° (c) Computer 1 1 Re-measure S 9 2. Convert the inspection result of the re-measurement into the inspection quality 値Yq, compare it with the expectation ,, and, in the case of abnormal determination, move to the mail delivery S 9 3, and send an email to the process personnel. It is known that the abnormality of the wafer 17b occurs. (d) The computer 1 1 moves to the history update S 9 4, and the memory device 1 2 records the abnormality of the wafer 17b, corresponding to the wafer number, the wafer batch, and the processing wafer processing device 14b. Update the database. (Measurement 値 comparison process). (a) In the re-measurement S92, the computer 1 1 compares the inspection quality 値Yq of the re-measurement of the reception with the expectation 而 to make an appropriate determination, and makes the re-measurement history and the inspection device 1 9b and the wafer 1 7b Corresponding to the memory device 12, the node 95 moves to the speculative quality comparison S96. (b) In the abnormality check S91, the computer 11 moves to the estimated quality comparison S96 even if the inspection quality 値Yq is determined to be appropriate. (c) The computer 11 compares the estimated quality 値Ye and the inspection quality 値Yq calculated by the self-diagnostic device 5b in the estimated quality comparison S96, and determines whether or not it matches the determination criterion. When the criterion is that the estimated quality 値Ye exists in the reliable section of the regression line of the estimated quality 値Ye and the inspection quality 値Yq, it is judged to be the same, and when it is deviated from the reliable section, it is judged as inconsistent. (d) In the case of the speculative quality comparison S96, the computer 11 determines the inconsistency judgment -46 - 1280603 (43), and moves to the element determination processing S 9 7 to correct the self-diagnosis parameter. For example, the self-diagnosis parameter is expressed by the following formula (1).

Ye 1=aX1+b …（1 ) 電腦1〗將現在的推測品質値「Ye 1 c」記億在記憶裝 置12，將變更係數「a」、係數「b」之其中一者或者係 數「a」、係數「b」之雙方的新的推測品質値「Ye 1 η」記 憶在記憶裝置1 2。 (e )電腦1 1在要素判定S97中，參照記億在記憶裝 置1 2之檢查品質値Yq之履歷，比較過去之推測品質値 .Yq 1 c的增減與判定爲不一致之時間點的推測品質値 Ye 1 η，使推測品質値Ye 1 η與推測品質値Yq能近似，而 判定是否做係數「a」之變更、係數^ b」之變更、追加與 裝置資訊「XI」不同之裝置資訊「Xn」。 (f )電腦1 1在推測品質値Y e 1 η與過去之推測品質 値Yq 1 c比較，判定爲假定外之變動的情形，在裝置資訊 追加S98中，追加與裝置資訊「XI」不同之新的裝置資 訊「Xn」，移往推測式更新S 1 0 1 ’將新的自我診斷參數 經由自我診斷裝置5 b而記錄在資料庫1 3 b。 (g )電腦1 1在推測品質値Y e 1 n與過去之推測品質 値Y q 1 c比較，於判定爲單調變化之情形’在a變更S 9 9 中，令係數「a」增減，使推測品質値γ e 1 n與推測品質値 Y q近似，移往推測式更新S 1 0 1，將新的自我診斷參數經 -47- 1280603 (44) 由自我診斷裝置5b而記錄在資料庫13b。 (h)電腦1 1在推測品質値Y e 1 η與過去之推測品質値 Y q 1 c比較，判定爲急遽變化之情形，在b變更S 1 0 0中， 增減係數「b」，使推測品質値Y e 1 η與推測品質値γ q近 似，移往推測式更新S 1 0 1，將新的自我診斷參數經由自 我診斷.裝置5b而記錄於資料庫13b。 (i )之後，電腦1 1移往郵件送訊S 1 0 2，對於製程 擔任人員發送電子郵件，實行新的自我診斷參數之更新報 告。 (j) 電腦1 1移往履歷更新S94，將晶圓17b之異常記 錄在記憶裝置1 2，與晶圓之號碼、晶圓之批次、處理晶 圓之處理裝置14b相對應，更新資料庫。 (k) 電腦1 1在推測品質比較S96中，做了一致判定之 情形，往規格確認S106分叉，判定推測品質値Yeln是 否進入規格。在判定爲進入規格之情形，移往履歷更新 S 94，將晶圓1 7b之正常記錄在記憶裝置1 2，與晶圓之號 碼、晶圓之批次、處理晶圓之處理裝置1 4b相對應而更新 資料庫。 此處，所謂「規格」係在製造半導體裝置之各製程 中，劃一決定之基準値，與前述之期待値不同。 (感測器異常通知流程） (a )電腦1 1在開始S 9 0中，晶圓1 7 b之批次被搬入 處理裝置]4 b，處理得以開始之情形，移往感測器檢查 -48- (45) 1280603 S103，檢查藉由自我診斷裝置5b之設置於處理裝 之各種感測器的動作。例如，判定蝕刻氣體之流 器 '局頻電源之感測器、處理室之壓力感測器等之 響飽刻之裝置資訊之感測器是否正常動作，在判定 時’移往推測品質計算s 1 〇 4，即使其中只有一個 異常之情形，往感測器異常通知S〗i 3分岔。 (b)電腦11在感測器異常通知S113中，由自 裝置5 b收訊對應處理裝置丨4 b之裝置資訊的感測 通知’參照記憶在記憶裝置1 2之處理裝置1 4 b的 履歷資訊’抽出被判定爲異常之感測器的相關履歷 例如，做成記載由前次之異常發生時至此次之異常 之經過時間（或者，連續正常動作期間）、處理裝 被設置在生產線起，被判定爲異常之合計次數、依 裝置14b正常動作時之裝置資訊的傾向之正常推薦 電子郵件。 (C )電腦1 1移往郵件送訊s 1 1 4，將在感測 通知S I 1 3所做成之電子郵件發送給製程擔任人員 處理裝置1 4 b之感測器異常，結束處理。 (推測品質計算流程） (a)自我診斷裝置5b由開始S90移往感測 S 1 0 3，在感測器全部正常之情形，移往推測品 S 1〇4，在將晶圓17b搬入處理裝置14b開始處理之 例如，也開始取得顯示進行處理室之阻抗調整之電 置 1 4b 量感測 輸出影 爲正常. 感測器 我診斷 器異常 感測器 資訊。 判定時 置14b 據處理 値等之 器異常 ’通知 器檢查 Ϊ計算 階段， 容的裝 -49- 1280603 (46) 置資訊「X 1」，使用式子（1 )，計算推測品質値Ye J， 移往品質管理SI 05。 (b )電腦1 1在品質管理S 1 0 5中，收訊自我診斷裝 置5 b所計算之晶圓1 7 b的推測品質値Y e 1之同時，依據 批次號碼或晶圓號碼判定晶圓1 7 b是否已經在檢查裝置 1 9b受到檢查。在判定檢查完畢之情形，往推測品質比較 S 96分岔，實行實測値比較流程之程序。 另一方面，在晶圓17b沒有受到檢查裝置19b檢查之 情形，往規格確認S 1 0 6分岔。即以處理裝置1 4 b —面處 理複數之批次，定期地檢查晶圓1 7b故，存在有未被檢查 之晶圓1 7 b，另外，即使是經過檢查之批次，非代表晶圓 之晶圓17b未被檢查裝置19b所檢查之履歷被保存在記憶 裝置1 2故，電腦1 1參照晶圓之履歷，往規格確認S 1 0 6 分岔。 (c )電腦1 1在規格確認S 1 06判定推測品質値Ye 1 是否進入規格。在判定爲進入規格之情形，移往履歷更新 S 94，將晶圓1 7b之正常記錄於記憶裝置1 2，與晶圓號 碼、晶圓之批次號碼、處理晶圓之處理裝置1 4b相對應而 更新資料庫，結束處理。 另一方面，電腦1 1在規格確認S 1 06中，判定推測品 質値Yel沒有進入規格之情形，往追加檢查決定S107分 岔。 (d )電腦1 1在追加檢查決定S 1 07中，以來自製程 擔任人員之指令而做追加檢查之情形，往追加品質管理 -50- 1280603 (47) S108分岔，令檢查裝置19b檢查晶圓17b，將轉換檢查結 果之檢查品質値Yq與晶圓1 7b相對應，保存在記憶裝置 12。 (e )電腦1 1將處理移往推測品質比較S 96，在追加 品質管理S 1 08中，比較保存在記億裝置1 2之檢查品質値 Yq與推測品質値Ye 1，實行實測値比較流程之程序。 (f)電腦11在追加檢查決定S107中，依據來自製 程擔任人員之指令，在不做晶圓1 7b之追加檢查的情形， 移往上位成分報告S 1 09，比較記憶在記憶裝置1 2之過去 的推測品質値Yqlc與在規格確認S1 06中判定爲沒有進 入規格之推測品質値.Ye 1 η，製作記載計算以式子（1 )所 表示之推測品質値Ye 1之模型中不一致之大的上位之成分 .·(例如，上位之係數「a」，及下一係數「b」）之電子郵 件。 另外，電腦1 1在上位成分報告S1 09中，將在規格確 認S 1 06被判定爲規格外之推測品質値Ye 1 η記憶在記憶 裝置1 2的資料庫之同時，參照記億在資料庫之推測品質 値Yq 1 c之履歷，調查過去是否有同樣之異常，製作記載 調查結果之電子郵件。 (g )電腦1 1移往郵件送訊S 1 1 0，對製程擔任人員 發送在上位成分報告S 1 09所製作之電子郵件，通知晶圓 17b之推測品質値Yel的異常發生。 如此，在關於第8實施形態之半導體裝置之製造系統 中，電腦1 1比較自我診斷裝置5 b計算之推測品質値Y e 1 -51 - 1280603 (48) 與定期性取得之由檢查裝置1 9b所獲得的檢查品質値 Yq，因應推測品質値Yel與檢查品質値Yq之差，修正推 測品質値Ye 1之推測式子的係數，或者變更推測式子故， 可以提高處理裝置1 4b之自我診斷的精度。 第1 〇圖係顯示第9圖之推測品質計算S 1 0 4所使用之 晶圓的.剖面圖。處理裝置14b將晶圓搬入處理室內。所搬 入之晶圓係具備有，形成在矽基板1 1 9之上方的層間絕緣 .膜之TEOS(四乙鄰矽酸鹽）118、形成在TEOS118上之反 射防止膜1 1 7之膜構造。另外，本發明並不將層間絕緣膜 限定爲 TEOS，也設其他的半導體薄膜形成材料之 TMPO、TEM爲對象。 在反射防止膜1 1 7的表面具有：形成有曝光顯像處理 結束之抗蝕劑1 1 6之領域，及在曝光顯像處理中，抗蝕劑 1 1 6被去除，露出反射防止膜1 1 7之領域。 處理裝置Mb對於反射防止膜117露出之領域，進行 反射防止膜1 17之蝕刻直到TEOS1 18顯現爲止。自我診 斷裝置5b係由處理裝置1 4b收訊蝕刻反射防止膜丨丨7之 蝕刻氣體（四氟化碳CF4、溴化氫HBr、氧氣〇2等）之 流量、高頻電源之進行波、高頻電源之反射波等之高頻電 源相關的參數、壓力等之複數的裝置資訊Xi(i係收集；^ 資訊的個數份存在）。 自我診斷裝置5b例如爲了計算蝕刻率之推測品w Yel，將進行處理室之阻抗調整之電容器的電容値當成裝 置資訊取得。另外，將蝕刻氣體之流量當成裝置資訊Χ2 -52· (49) 1280603 取得，計算鈾刻率之推測品質 Ye2係製造製程之選擇事 項。 第1 1圖係顯示第9圖之推測品質比較S96所使用之 判定基準之曲線。曲線之橫軸係表示自我診斷裝置5 b計 算之蝕刻率的推測品質値Ye 1，曲線的縱軸係表示檢查裝 置1 9b.依據檢查過晶圓1 7b之實測値，電腦1 1計算之蝕 刻率的檢查品質値Yql。 電腦1 1在推測品質比較S96中，比較推測品質値 Yel與檢查品質値Yql之際，於推測品質値Yel存在於 推測品質値Yel與檢查品質値Yql之回歸直線的可靠區 間內（虛線1 24與虛線1 25所夾住之領域）之情形，判定 爲一致，在偏離可靠區間時，判定爲不一致。 電腦1 1依據檢查在處理裝置1 4b所蝕刻之複數批次 的晶圓之實測値，計算對應晶圓號碼之蝕刻率的檢查品質 値Yq 1，記億在記憶裝置1 2。另外，電腦1 1由自我診斷 裝置5 b收訊對應晶圓號碼之蝕刻率的推測品質値Ye 1， 記憶在記憶裝置1 2。 在求得推測品質値Y e 1之模型的式子（1 )適當之情 形，對於各晶圓號碼之檢查品質値Yq 1出現與推測品質 値 Yel之交點的晶圓中，則具有在蝕刻率^ 2.3」〜 「4.3」（n m /秒）之範圍中，與回歸直線1 2 6重疊或位於 附近之品質。 但是，設置在處理裝置14b之處理室的壓力、電容器 之値、蝕刻氣體之流量變動時，在批次間，會有晶圓品質 -53- 1280603 (50) 產生 122 Yql 推測 Yel 質値 歸直 測品 查品 品質 回歸 測品 查品 質値 歸直 測品 查品 質値 歸直 測品 變動之情形。例如’出現以圖中之圓圈1 2 〇、；! 2 I、 、：123所包圍之交點的晶圓，係對於檢查品質値 ’分別產生與推測品質値Yel之差故，需要變更求得 品質値Ye 1之模型的式子（丨），以提高推測品質値 之可靠性。 出.現以圓圈120所包圍之交點的晶圓，係對於檢查品 Y q 1爲「2 · 8」，推測品質値γ e丨爲「2 · 3」，位於回 線1 26之上側，變更模型之式子（1 )的參數以令推 質値Y e 1增加。例如，增加係數「^」，使近似於檢 質値Yql。 在出現以圓圈1 2 1所包圍之交點的晶圓，係對於檢查 値Y q 1爲「3 · 1」，推測品質値γ e丨爲「2.6」，位於 直線1 2 6上側’變更模型之式子（1 )的參數以令推 質値Yel增加。例如’增加係數「a」，使近似於檢 質値Yql。 出現以圓圈1 22所包圍之交點的晶圓，係對於檢查品 Y q 1爲「2 · 3」，推測品質値Y e 1爲「2.8」，位於回 線1 2 6之下側’變更模型之式子（1 )的參數以令推 質値Ye 1減少。例如’減少係數「a」，使近似於檢 質値Yql。 出現以圓圈1 23所包圍之交點的晶圓，係對於檢查品 Y q 1爲「2.5」，推測品質値Y e 1爲「3 · 〇」，位於回 線12 6之下側，變更模型之式子（1 )的參數以令推 質値Y e 1減少。例如，減少係數「a」，使近似於檢 -54- 1280603 (51) 查品質値Yql。 電腦1 1在變更模型的式子（1 )之參數時，參照基於 記憶在記億裝置1 2之晶圓的實測値之檢查品質値Yq 1的 時間序列曲線之資料。 如第1 2圖所示般，在檢查品質値Y q 1之時間序列曲 線中，橫軸係表示處理晶圓之日期，縱軸表示蝕刻率 (nm /秒）之檢查品質値Yql。 出現以第1 1圖之圓圈1 20所包圍之交點的晶圓，係 相當於以圖中之圓圈1 3 0所包圍之2月4曰所處理的批 次，由2月1日起，檢查品質値Yql係單調增加故，電 腦1 1令式子（1 )之係數「a」增加，更新爲蝕刻率之推 測品質値Yeln。 出現以第1 1圖之圓圈1 2 1所包圍之交點的晶圓，也 相當於以圖中之圓圈131所包圍之2月5曰所處理的批 次，由2月4日起，檢查品質値Yq 1係單調增加故，電 腦1 1令式子（1 )之係數「a」增加，更新爲蝕刻率之推 測品質値Yeln。 出現以第1 1圖之圓圈1 22所包圍之交點的晶圓，係 相當於以圖中之圓圈1 3 2所包圍之2月7曰所處理的批 次，與2月5日之檢查品質値Yq 1相比，急遽減少故， 電腦1 1令式子（1 )之係數「b」減少，更新爲蝕刻率之 推測品質値Yeln。 出現以第1 1圖之圓圈1 23所包圍之交點的晶圓，相 當於以圖中之圓圈1 3 3所包圍之2月1 3日所處理的批 -55- 1280603 (52) 次，由2月7日之檢查品質値Yq 1係單調增加故，電腦 1 1做式子（1 )之係數「a」的變更判定，推測品質値檢 查品質値 Y q 1 η位於回歸直線1 2 6之下側故，減少係數 「a」，更新爲鈾刻率之推測品質値Ye 1 η。 出現以第1 1圖之圓圈1 3 4所包圍之交點的晶圓，係 相當於.2月22日所處理的批次，與2月1 3日之檢查品質 値Yq 1 c相比，急遽增加。此批次係在現況之式子（1 ) 中，爲假定外之變動，電腦U移往第9圖之推測式子更 新S101，將新的自我診斷參數經由自我診斷裝置5b而記 錄在資料庫13b，移往郵件送訊S102(參照第9圖），對製 程擔任人員以郵件通知推測品質推測式子之變更。 在第8實施形態中，電腦1 1變更資料庫1 3 b之自我 診斷參數的同時，令對應記憶在記憶裝置1 2之晶圓號碼 的推測品質値Ye 1 c與檢查品質値Yq 1 c對應批次而加以 記憶，使以複數之批次所處理的複數之晶圓的推測品質値 Y e 1 η近似於檢查品質値γ q 1 n。 而且，電腦1 1依據蝕刻率之推測品質値Ye 1與檢查 品質値Yq 1之比較結果及檢查品質値Yq 1 c之時間序列變 化，實行要素判定處理S97(參照第9圖），選擇式子（1 ) 之要素，自動更新係數「a」、係數「b」之變更，在式子 (1 )被更新後，求得新的推測品質値Ye 1 η，可以保持在 適當之狀態。 因此，只監視蝕刻率之推測品質値Ye 1而會引起之處 理裝置1 4b的異常錯誤檢測及異常漏掉之防止變成可能。 -56- 1280603 (53) 即藉由異常錯誤檢測之防止，可令處理裝置〗4b之稼動率 提升’藉由異常漏掉之防止，可防患低產品率批次之發生 於未然。 在以下中，於處理裝置14a、處理裝置14b、處理裝 置Ik、處理裝置14d之中，以具有氧化爐之處理裝置 1 4 a爲例做說明。 自我診斷裝置5a係將供應給處理裝置14a之供給氣 體（氧氣02、氮氣N2、氫氣H2等）之流量、加熱器電 力、氧化爐周圍之氣壓等當成裝置資訊而收訊。將收訊之 裝置資訊記憶於資料庫1 3 a的同時，使用以下之式子 .(2 )而計算晶圓17a之氧化膜厚的推測品質値Ye2。Ye 1=aX1+b (1) The computer 1 says that the current estimated quality 値 "Ye 1 c" is recorded in the memory device 12, and one of the coefficient "a" and the coefficient "b" or the coefficient "a" is changed. The new estimated quality 値 "Ye 1 η" of both the coefficients "b" is stored in the memory device 12. (e) In the element determination S97, the computer 1 1 compares the history of the inspection quality 値Yq of the memory device 1 2, and compares the estimation of the time when the increase and decrease of the past estimation quality 値.Yq 1 c is determined to be inconsistent. The quality 値Ye 1 η is such that the estimated quality 値Ye 1 η and the estimated quality 値Yq can be approximated, and it is determined whether or not the coefficient "a" is changed, the coefficient ^b" is changed, and device information different from the device information "XI" is added. "Xn". (f) The computer 11 compares the estimated quality 値Y e 1 η with the past estimated quality 値Yq 1 c, and determines that the change is assumed to be outside. In the device information addition S98, the device information "XI" is added. The new device information "Xn" is moved to the speculative update S1 0 1 'The new self-diagnosis parameter is recorded in the database 13b via the self-diagnostic device 5b. (g) The computer 11 increases or decreases the coefficient "a" when the estimated quality 値Y e 1 n is compared with the past estimated quality 値Y q 1 c and determines that the change is monotonous. The estimated quality 値γ e 1 n is approximated to the estimated quality 値Y q , and moved to the speculative update S 1 0 1, and the new self-diagnosis parameter is recorded in the database by the self-diagnostic device 5b via -47-1280603 (44). 13b. (h) The computer 11 compares the estimated quality 値Y e 1 η with the past estimated quality 値Y q 1 c and determines that it is a sudden change. When b changes S 1 0 0, the coefficient “b” is increased or decreased. The estimated quality 値Y e 1 η is approximated to the estimated quality 値γ q, and moved to the speculative update S 1 0 1, and the new self-diagnosis parameter is recorded in the database 13b via the self-diagnosis device 5b. (i) After that, the computer 1 1 moves to the mail delivery S 1 0 2, and an email is sent to the process person to perform a new self-diagnosis parameter update report. (j) The computer 1 1 moves to the history update S94, and records the abnormality of the wafer 17b in the memory device 12, and updates the database in correspondence with the wafer number, the wafer batch, and the processing wafer processing device 14b. . (k) When the computer 1 1 makes a coincidence determination in the estimated quality comparison S96, it branches to the specification check S106 to determine whether or not the estimated quality 値Yeln has entered the specification. When it is determined that the specification is entered, the process proceeds to the history update S 94, and the normal recording of the wafer 17b is recorded in the memory device 12, and the number of the wafer, the batch of the wafer, and the processing device for processing the wafer 14b Update the database accordingly. Here, the "specification" is a standard that is determined in each process of manufacturing a semiconductor device, and is different from the above-mentioned expectation. (Sensor abnormality notification flow) (a) The computer 1 1 at the start S 90, the batch of the wafer 1 7 b is carried into the processing device] 4 b, and the processing is started, and the sensor is checked - 48-(45) 1280603 S103, the operation of the various sensors provided in the processing device by the self-diagnostic device 5b is checked. For example, it is determined whether the sensor of the etch gas flow sensor, the sensor of the local frequency power supply, the pressure sensor of the processing room, etc., is functioning normally, and is moved to the speculative quality calculation s when determining. 1 〇 4, even if there is only one abnormal situation, the sensor is notified of S i i 3 minutes. (b) The computer 11 receives the sensing notification of the device information of the corresponding processing device 丨4b from the device 5b in the sensor abnormality notification S113, and refers to the history of the processing device 1 4b stored in the memory device 12. The information "extracting the history of the sensor that is determined to be abnormal, for example, describes the elapsed time from the occurrence of the previous abnormality to the current abnormality (or the continuous normal operation period), and the processing package is set on the production line. A normal recommendation email that is determined to be the total number of abnormalities and the tendency of the device information when the device 14b is operating normally. (C) The computer 1 1 moves to the mail delivery s 1 1 4, and transmits an email made by the sensing notification S I 1 3 to the process handler of the processing staff 1 4 b, and ends the processing. (Preliminary quality calculation flow) (a) The self-diagnosis device 5b moves from the start S90 to the sensing S1 0 3, and when the sensor is all normal, moves to the speculative S 1〇4, and carries the wafer 17b into the process. The device 14b starts processing, for example, and starts to obtain the display of the impedance adjustment of the processing chamber. The sensed output image is normal. The sensor I diagnoses the abnormal sensor information. In the judgment, the 14b is processed according to the abnormality of the processing device, the notification device is checked, and the device is loaded with the information "X 1", and the estimated quality 値Ye J is calculated using the equation (1). Move to Quality Management SI 05. (b) The computer 1 1 in the quality management S 1 0 5, receives the estimated quality 値Y e 1 of the wafer 1 7 b calculated by the self-diagnostic device 5 b, and determines the crystal based on the batch number or the wafer number Whether the circle 1 7 b has been inspected at the inspection device 1 9b. In the case where the judgment is completed, the comparison quality is compared with S 96 minutes, and the procedure of the actual measurement and comparison process is carried out. On the other hand, in the case where the wafer 17b is not inspected by the inspection device 19b, it is confirmed to the specification S 1 0 6 . That is, the processing device 14b processes the plurality of batches, periodically checks the wafers 1 7b, so there are unchecked wafers 1 7 b, and even the inspected batches, non-representative wafers The history of the wafer 17b that has not been inspected by the inspection device 19b is stored in the memory device 1. Therefore, the computer 11 refers to the history of the wafer and confirms the specification S 1 0 6 . (c) The computer 1 1 determines whether the estimated quality 値Ye 1 has entered the specification in the specification check S 1 06. When it is determined that the specification is entered, the process proceeds to the history update S 94, and the normal recording of the wafer 17b is performed on the memory device 12, and the wafer number, the batch number of the wafer, and the processing device for processing the wafer 14b Correspondly update the database and end the processing. On the other hand, in the specification check S 1 06, the computer 11 judges that the estimated quality 値Yel has not entered the specification, and determines the S107 for the additional inspection. (d) In the case of the additional inspection decision S 1 07, the computer 1 1 has made an additional inspection by the instructions of the self-made process, and has been assigned to the additional quality management -50-1280603 (47) S108, so that the inspection device 19b checks the crystal. In the circle 17b, the inspection quality 値Yq of the conversion inspection result is stored in the memory device 12 in correspondence with the wafer 17b. (e) The computer 11 moves the processing to the estimated quality comparison S 96, and compares the inspection quality 値Yq and the estimated quality 値Ye 1 stored in the JI device 1 in the additional quality management S 1 08, and performs the actual measurement 値 comparison process. The program. (f) In the additional inspection decision S107, the computer 11 moves to the upper component report S 1 09 when the additional inspection of the wafer 1 7b is not performed in accordance with the instruction from the process person, and compares and stores it in the memory device 1 2 The past estimated quality 値Yqlc and the estimated quality 値.Ye 1 η determined to have no entry specifications in the specification check S1 06, and the calculation of the difference in the model of the estimated quality 値Ye 1 expressed by the expression (1) are large. The upper part of the component. (for example, the upper coefficient "a", and the next coefficient "b"). Further, in the upper component report S1 09, the computer 1 1 stores the estimated quality 値Ye 1 η determined to be outside the specification in the specification check S 1 06 in the database of the memory device 1 2, and refers to the bank in the database. The estimated quality 値Yq 1 c resume, investigate whether there is the same abnormality in the past, and create an email describing the survey results. (g) The computer 1 1 moves to the mail delivery S 1 10 0, and sends an e-mail created by the upper component report S 1 09 to the process person to notify the wafer 17b that the speculative quality 値Yel has occurred abnormally. As described above, in the manufacturing system of the semiconductor device according to the eighth embodiment, the computer 11 compares the estimated quality 値Y e 1 -51 - 1280603 (48) calculated by the self-diagnostic device 5 b with the periodic inspection device 1 9b. The obtained inspection quality 値Yq, based on the difference between the estimated quality 値Yel and the inspection quality 値Yq, the coefficient of the estimated expression 値Ye 1 is corrected, or the estimation formula is changed, and the self-diagnosis of the processing device 14b can be improved. Precision. The first diagram shows a cross-sectional view of the wafer used in the speculative quality calculation S 1 0 4 of Fig. 9. The processing device 14b carries the wafer into the processing chamber. The wafer to be loaded is provided with an interlayer insulating layer formed above the germanium substrate 1 19 , a TEOS (tetraethyl orthosilicate) 118 of the film, and a film structure of the antireflection film 1 17 formed on the TEOS 118. Further, in the present invention, the interlayer insulating film is not limited to TEOS, and TMPO and TEM of other semiconductor thin film forming materials are also targeted. The surface of the anti-reflection film 1 17 has a region in which the resist 1 16 having the exposure development process is completed, and in the exposure development process, the resist 1 16 is removed to expose the anti-reflection film 1 The field of 1 7 . The processing apparatus Mb performs etching of the anti-reflection film 117 on the area where the anti-reflection film 117 is exposed until the TEOS 1 18 appears. The self-diagnostic device 5b receives the flow rate of the etching gas (such as carbon tetrafluoride CF4, hydrogen bromide HBr, oxygen oxime 2, etc.) of the etching reflection preventing film 丨丨7 by the processing device 14b, and the wave of the high-frequency power source is high. A device information Xi of a plurality of parameters, pressures, etc. related to a high-frequency power source such as a reflected wave of a frequency power source (i is a collection; ^ a number of pieces of information exists). The self-diagnostic device 5b obtains the capacitance of the capacitor that performs the impedance adjustment of the processing chamber as the device information, for example, in order to calculate the etch rate estimation product w Yel . In addition, the flow rate of the etching gas is obtained as the device information Χ 2 - 52 · (49) 1280603, and the estimated quality of the uranium engraving rate is calculated. Ye2 is a manufacturing process selection item. Fig. 1 is a graph showing the judgment standard used in the comparison quality comparison S96 of Fig. 9. The horizontal axis of the curve indicates the estimated quality 蚀刻Ye of the etch rate calculated by the self-diagnostic device 5b, and the vertical axis of the curve indicates the inspection device 1b. According to the actual measurement of the wafer 1bb, the computer 11 calculates the etching. The quality of the inspection is 値Yql. In the speculative quality comparison S96, the computer 11 compares the estimated quality 値Yel and the inspection quality 値Yql, and the estimated quality 値Yel exists in the reliable interval of the regression line between the estimated quality 値Yel and the inspection quality 値Yql (dashed line 1 24 In the case of the area sandwiched by the broken line 156, it is judged to be identical, and when it deviates from the reliable section, it is judged to be inconsistent. The computer 1 1 calculates the inspection quality of the etching rate corresponding to the wafer number based on the actual measurement of the plurality of wafers etched by the processing device 14b, 记Yq 1, and records in the memory device 12. Further, the computer 11 receives the estimated quality 値Ye1 of the etching rate corresponding to the wafer number by the self-diagnostic device 5b, and stores it in the memory device 12. In the case where the formula (1) of the model for estimating the quality 値Y e 1 is appropriate, the etch rate is obtained in the wafer where the inspection quality 値Yq 1 of each wafer number appears at the intersection with the estimated quality 値Yel. ^ 2.3" ~ "4.3" (nm / sec) in the range of the regression line 1 2 6 overlap or near the quality. However, when the pressure in the processing chamber of the processing device 14b, the enthalpy of the capacitor, and the flow rate of the etching gas fluctuate, there will be a wafer quality of -53 - 1280603 (50) between the batches, and 122 Yql is estimated to be Yel quality. Detecting the quality of the product, returning the product, checking the quality of the product, and checking the quality of the product. For example, the wafer having the intersection of the circle 1 2 〇, ;! 2 I, , and 123 in the figure is the difference between the quality and the quality of the inspection 値Yel, and the quality is required to be changed.式Ye 1 model (丨) to improve the reliability of the speculative quality. The wafer at the intersection surrounded by the circle 120 is "2 · 8" for the inspection product Y q 1 , and the estimated quality 値 γ e 丨 is "2 · 3", which is located above the return line 1 26 and changes the model. The parameter of the formula (1) is such that the push 値Y e 1 is increased. For example, increase the coefficient "^" to approximate the quality 値Yql. In the wafer where the intersection surrounded by the circle 1 2 1 appears, the inspection 値Y q 1 is "3 · 1", and the estimated quality 値 γ e 丨 is "2.6", which is located on the upper side of the straight line 1 2 6 The parameter of equation (1) is such that the push 値Yel is increased. For example, 'increasing the coefficient "a" makes it approximate the quality 値Yql. The wafer having the intersection surrounded by the circle 1 22 is "2 · 3" for the inspection product Y q 1 , and the estimated quality 値 Y e 1 is "2.8", which is located below the return line 1 2 6 'change model The parameter of equation (1) is such that the push 値Ye 1 is reduced. For example, the reduction coefficient "a" approximates the quality 値 Yql. The wafer having the intersection surrounded by the circle 1 23 is "2.5" for the inspection product Y q 1 , and the estimated quality 値 Y e 1 is "3 · 〇", which is located below the return line 12 6 and changes the model. The parameter of sub (1) is such that the push 値Y e 1 is reduced. For example, reduce the coefficient "a" to approximate the quality of 54Yql -54 - 1280603 (51). When changing the parameters of the equation (1) of the model, the computer 11 refers to the data of the time series curve based on the inspection quality 値Yq 1 of the actual measurement of the wafer stored in the recording device. As shown in Fig. 2, in the time series curve of the inspection quality 値Y q 1 , the horizontal axis indicates the date of processing the wafer, and the vertical axis indicates the inspection quality 値Yql of the etching rate (nm / sec). The wafer that appears at the intersection surrounded by the circle 1 20 of Fig. 1 is equivalent to the batch processed by February 4, which is surrounded by the circle 1 3 0 in the figure, and is checked from February 1st. The quality 値Yql is monotonously increased, and the coefficient "a" of the computer (1) is increased to the estimated quality of the etching rate 値Yeln. The wafer in which the intersection surrounded by the circle 1 21 of Figure 11 appears is also equivalent to the batch processed by February 5, surrounded by the circle 131 in the figure, and the quality is checked from February 4th.値Yq 1 is monotonously increased, and the coefficient "a" of the computer (1) is increased to the estimated quality of the etching rate 値Yeln. The wafer showing the intersection surrounded by the circle 1 22 of Fig. 1 is equivalent to the batch processed by February 7曰 surrounded by the circle 1 3 2 in the figure, and the inspection quality on February 5th.値Yq 1 is less urgent, so the coefficient "b" of the computer (1) is reduced to the estimated quality of the etching rate 値Yeln. A wafer having an intersection surrounded by a circle 1 23 of FIG. 1 is equivalent to a batch of -55 - 1280603 (52) times processed on February 13 surrounded by a circle 133 in the figure. On February 7th, the inspection quality 値Yq 1 is monotonously increased, and the computer 1 1 makes the change of the coefficient "a" of the formula (1), and the quality 値 inspection quality 値Y q 1 η is located at the regression line 1 2 6 On the lower side, the coefficient "a" is reduced and updated to the estimated quality 値Ye 1 η of the uranium engraving rate. The wafer that appears at the intersection surrounded by the circle 1 3 4 of Figure 1 is equivalent to the batch processed on February 22, and is more urgent than the inspection quality 値Yq 1 c on February 13 increase. This batch is in the current equation (1). In the case of a hypothetical external change, the computer U moves to the speculative sub-update S101 of Fig. 9, and the new self-diagnosis parameter is recorded in the database via the self-diagnostic device 5b. 13b, moving to the mail delivery S102 (refer to Fig. 9), and notifying the process person to notify the change of the speculative quality estimation formula by mail. In the eighth embodiment, the computer 11 changes the self-diagnosis parameter of the database 13b, and causes the estimated quality 値Ye 1 c corresponding to the wafer number of the memory device 12 to correspond to the inspection quality 値Yq 1 c . The batch is memorized so that the estimated quality 値Y e 1 η of the plurality of wafers processed in a plurality of batches approximates the inspection quality 値γ q 1 n. Further, the computer 11 performs the element determination processing S97 (refer to Fig. 9) based on the comparison result between the comparison quality 値Ye 1 of the etching rate and the inspection quality 値Yq 1 and the inspection quality 値Yq 1 c (see Fig. 9), and the selection formula (1) The element is automatically updated with the coefficient "a" and the coefficient "b". After the expression (1) is updated, the new estimated quality 値Ye 1 η is obtained and can be maintained in an appropriate state. Therefore, it is possible to monitor only the estimated quality 値Ye 1 of the etching rate, which causes the abnormality detection of the physical device 14b and the prevention of abnormal leakage. -56- 1280603 (53) That is, by preventing the abnormal error detection, the processing rate of the processing device "4b can be increased". By preventing the abnormal leakage, it is possible to prevent the low-product rate batch from occurring. In the following, among the processing device 14a, the processing device 14b, the processing device 1k, and the processing device 14d, a processing device 14a having an oxidation furnace will be described as an example. The self-diagnostic device 5a receives the flow rate of the supply gas (oxygen 02, nitrogen gas N2, hydrogen gas H2, etc.) supplied to the processing device 14a, the heater power, the air pressure around the oxidation furnace, and the like as device information. The information of the device to be received is stored in the database 13 3 a, and the estimated quality 値Ye2 of the oxide film thickness of the wafer 17a is calculated using the following equation (2).

Ye3 = cX2 + dX3 + eX4 + f …（2) 裝置資訊X2係表示加熱器電力，裝置資訊X3係表 禾氧氣02之流量，裝置資訊X4係表示氧化爐周圍之氣 驗。另外，電腦Π係對係數「c」、係數「d」、係數 %」、係數「f」分配自我診斷參數。 晶圓1 7 a之氧化膜厚雖受到全部之參數的影響，但 %’如第13圖所示般，在長期連休前（圖中之4月13曰 至4月28日）之氧化膜厚（nm )的推測品質値Ye2c係 控制在「98」〜「99」之範圍。處理裝置14a由4月28 曰之夜晚至5月6日之早上停止，長期連休後（圖中之5 月6日以後）的氧化膜厚（n m )之推測品質値γ e 2 η係移 -57· 1280603 (54) 動於「96」〜「97」之範圍，氧化膜厚之推測品質値Ye 2 大爲變動。 如第14圖所示般，自我診斷裝置5a由處理裝置14a 收訊加熱器電力（W )之裝置資訊，。長期連休前之加熱 器電力140，在使處理裝置14a稼動後，5 0 0秒後爲 900W，600秒後爲200W，650秒後爲100W以下。 相對於此，長期連休後之加熱器電力1 4 1，在使處理 裝置14a稼動後，500秒後爲600W，600秒後爲零W， 65 0秒後由零往200W上升，75 0秒後爲150W〜3 00W以 下，與長期連休前之加熱器電力140比較，直到65 0秒， 加熱器電力下降，700秒後，加熱器電力上升，此點係不 相同處。 處理裝置14a監控氧化爐之溫度上升。長期連休前之 溫度142，在使處理裝置14a稼動後，5 60秒後上升爲 8 〇 〇 °C，7 0 0秒後上升爲8 4 0 °C，8 0 0秒以後移到8 4 0〜8 5 0 °C之範圍。長期連休後之溫度143，在使處理裝置14a稼 動後，5 7 0秒後上升爲 8 0 (TC，7 0 0秒後上升爲 8 3 0 °C， 8〇〇秒以後移到840〜85 0 °C之範圍，與長期連休前比較， 溫度上升曲線下降。 自我診斷裝置5a是由處理裝置14a收訊在長期連休 之前後不同的裝置資訊X2之加熱器電力的裝置資訊故， 可知道溫度上升曲線在長期連休前後有變動。 因此，電腦1 1實行推測品質比較處理，比較依據在 檢查裝置19a所實測之長期連休後的晶圓17a之膜厚之檢 -58- 1280603 (55) 查品質値Yq2，及由自我診斷裝置5a所收訊之長期連休 後之晶圓1 7a的氧化膜厚之推測品質値Ye2 ’進行不^ $ 判定。 電腦11實行要素判定處理，使式子（2 )之係數 「c」增加，藉由自動產生對應長期連休後之自我診斷# 數，今後，事先掌握長期連休前後（例如，一年數次之許 經常作業）之設置在氧化爐的加熱器之狀態變化，可以提 高晶圓1 7a之氧化膜厚之推測品質値Ye2的可靠性。 電腦11對於自我診斷裝置5a，通知式子（2)之變寅 令設置在自我診斷裝置5 a側之資料庫1 3 a記憶新的式子 (2 )，也令記憶裝置1 2記憶式子（2 )之變更。另外’ .式子（2 )之變更通知係藉由郵件送訊處理，由電腦1 1自 動地對製程擔任人員發送電子郵件。 如此，藉由定期地比較基於晶圓1 之氧化膜厚實測 之檢查品質値Yq2與自我診斷裝置5a計算之氧化膜厚之 推測品質値Ye2，可以掌握長期連休前後（一年數次之非 經常作業）之加熱器的狀態變化，可以防患晶圓1 7 a之氧 化膜厚的推測品質値Ye2之異常於未然。 另外，本發明之實施形態所記載之作用及效果，不@ 是列舉由本發明所產生之最適當的作用及效果而已，基於 本發明之作用及效果，並不限定於本發明之實施形態所記 載者。 以下，揭示與關於本發明之實施形態之半導體裝置之 製造系統及半導體裝置之製造方法有關連之技術事項。 -59- 1280603 (56) (a )關於本發明之實施形態之半導體裝置之製造系 統，係具備：實行使用半導體基板之製程處理之處理裝 置，及由處理裝置收訊裝置資訊，計算製程處理之推測品 質値之自我診斷系統，及檢查製程處理之結果的檢查裝 置，及比較檢查結果與推測品質値，在推測品質値判定爲 有效時.，維持自我診斷系統之參數，在推測品質値判定爲 無效時，變更自我診斷系統之參數的係數之電腦。 (b )本發明之實施形態所使用的電腦，在推測品質 値判定爲無效時，變更參數之式子。 (c )本發明之實施形態所使用之電腦，在檢查結果 存在於由推測品質値與實測値所成之回歸直線之可靠區域 內時，進行有效判定。 (d )本發明之實施形態所使用之電腦，計算基於記 憶在記憶裝置之過去的實測値之品質傾向，比較檢查結果 與品質傾向，進行判定。 (e )本發明之實施形態所使用之電腦，依據半導體 基板之氧化處理製程之檢查結果，進行判定。 (f )本發明之實施形態所使用之電腦，依據半導體 基板之蝕刻處理製程之檢查結果，進行判定。 (g )關於本發明之實施形態之半導體裝置之製造方 、法’係具備：診斷實行半導體基板之製程處理之處理裝 胃’在滿足特定條件之階段，產生自動修復要求訊號之自 動修復要求工程，及檢查經過處理之半導體基板的品質之 ^質檢查工程，及依據藉由品質檢查工程所取得之品質管 -60- 1280603 (57) 理資訊，判定自動修復要求訊號之產生時序的良否，在該 判定結果爲有效判定時，維持自我診斷系統之參數，在該 判定結果爲無效判定時，變更自我診斷系統之參數的同 時，變更品質檢查之動作頻度之自動檢查頻度修正工程。 (h )關於本發明之實施形態之半導體裝置之製造方 法，在.判定結果爲無效判定時，電腦追加自我診斷系統之 參數。 (i )關於本發明之實施形態之半導體裝置之製造方 法，係具備：監控實行半導體基板之製程處理之處理裝置 的狀態之同時，依循處理製程模型，積分該處理裝置之裝 置資訊，實行半導體製造製程之模擬，推測藉由該處理之 半導體基板的品質之即時模擬工程。 (j )關於本發明之實施形態之半導體裝置之製造方 法，係具備：監控實行半導體基板之製程處理之處理裝置 的裝置資訊，輸出該半導體基板之推測品質資訊之品質推 測工程，及輸出經過處理之半導體基板的檢查品質資訊之 品質檢查工程，及比較推測品質資訊與檢查品質資訊，判 定品質檢查工程之時序的良否，在判定結果爲無效判定 時，檢知處理裝置之異常之異常檢知工程。 (k )關於本發明之實施形態之半導體裝置之製造方 法，係具備：監控實行半導體基板之製程處理之處理裝置 的裝置資訊，輸出該半導體基板之推測品質資訊之品質推 測工程，及輸出經過處理之半導體基板之檢查品質資訊之 品質檢查工程，及實行推測品質資訊與檢查品質資訊之品 -61 - 1280603 (58) 質相關處理之推測品質管理工程，及依據推測品質資訊， 實行半導體製造製程模擬，預測半導體裝置之產品率之產 品率預測工程，及經過藉由處理裝置之處理，至少檢查晶 圓工程結束之半導體裝置之產品率之產品率檢查工程，及 比較藉由產品率預測工程之產品率及藉由產品率檢查工程 之產品率之產品率相關處理工程。 (1 )關於本發明之實施形態之半導體裝置之製造方 法，係具備：實行半導體基板之製程處理之加工處理工 程，及輸出經過加工處理工程之半導體基板之品質資訊之 品質檢查工程，及收訊在品質檢查工程所獲得之品質資 訊，實行半導體製造製程模擬，預測半導體裝置之產品率 之產品率預測工程，及經過處理裝置之處理，至少檢查晶 圓工程結束之半導體裝置之產品率之產品率檢查工程，及 比較藉由產品率預測工程之產品率與藉由產品率檢查工程 之產品率，提高產品率預測工程之產品率的預測精度之產 品率相關處理工程。 (m )關於本發明之實施形態之半導體裝置之製造方 法，係具備：實行半導體基板之製程處理之加工處理工 程，及監控加工處理裝置之裝置資訊，輸出半導體基板之 推測品質資訊之品質推測工程，及輸出經過加工處理工程 之半導體基板之品質資訊之品質檢查工程，及實行推測品 質資訊與品質資訊之品質相關處理之推測品質管理工程， 及實行基於藉由品質檢查工程之品質資訊之半導體製造製 程模擬，預測半導體裝置之產品率之第1產品率預測工 -62- 1280603 (59) 程，及依據藉由推測品質管理工程之推測品質資訊，實行 與第1產品率預測工程之半導體製造製程模擬不同之半導 體製造製程模擬，預測半導體裝置之產品率之第2產品率 預測工程，及經過加工處理工程，至少檢查晶圓工程結束 之半導體裝置的產品率之產品率檢查工程，及比較藉由第 1產品率預測工程之產品率與藉由產品率檢查工程之產品 率之第1產品率相關處理工程，及比較藉由第2產品率預 測工程之產品率與藉由產品率檢查工程之產品率之第2產 品率相關處理工程，及依據第1及第2產品率相關處理工 程之相關結果，提高第1及第2產品率預測工程之產品率 預測精度之預測產品率比較工程。 (η )關於本發明之實施形態之半導體裝置之製造方 法，係具備：檢測顯示實行半導體基板之製程處理之處理 裝置的狀態之檢測値，由該檢測値之中抽出該處理之非控 制値，獲得特徵量之特徵量化工程，及比較藉由特徵量化 工程所抽出而獲得之特徵量與藉由範圍分類而將固有之缺 陷影像予以數値化，而事先記憶之相關表內的特徵量，在 相互之特徵量判定爲相同程度化所得之値的階段，中斷半 導體製造製程，將半導體基板當成不良批次而通報知品質 檢知工程。 (〇 )關於本發明之實施形態之半導體裝置之製造方 法，係進而具備：在具有無法與相關表內之特徵量相同程 度化之新的特徵量的不良批次被檢測出時，依據該不良批 次之製程履歷資訊，抽出顯示不良批次產生時之處理裝置 -63- 1280603 (60) 的狀態之裝置資訊，將該處理裝置的裝置資訊自動地反饋 給品質推測部之推測品質自動更新工程。 【圖式簡單說明】 第1圖係關於本發明之第1實施形態之半導體裝置的 製造系.統之模型系統圖。 第2圖係說明關於本發明之第1及第2實施形態之半 導體裝置的製造方法之模型流程圖。 第3圖係關於本發明之第3實施形態之半導體裝置的 製造系統之模型方塊圖。 第4圖係說明關於本發明之第4實施形態之半導體裝 置的.製造方法之模型流程圖。 第5圖係說明關於本發明之第5實施形態之半導體裝 置的製造方法之模型流程圖。 第6圖係說明界定使發生關於本發明之第6實施形態 之半導體裝置的不良批次的製造裝置之方法圖。 第7圖係說明關於本發明之第7實施形態之半導體裝 置的製造方法之模型流程圖。 第8圖係關於本發明之第8實施形態之半導體裝置的 製造系統之系統圖。 第9圖係關於本發明之第8實施形態之半導體裝置的 製造方法之流程圖。 第1 0圖係本發明之第8實施形態所使用之半導體裝 置的剖面圖。 -64 - l28〇6〇3 (61) 圖係說明本發明之第8實施形態所使用 方法_。 第1 2圖係說明本發明之第8實施形態所使用 方法圖。- 〜 a ®係說明本發明之第8實施形態所使用 方法ϋ。 4圖係本發明之第8實施形態所使用之溫 曲線_。 【主荽元件符號說明】 — 5a :自我診斷裝置，10 :製造系統，11:電腦 記憶裝置 Ί _ 1 3 ·資料庫，1 4 :處理裝置，1 5 :直接 接材料，；< .βθ ’閘門’ 17:晶圓，18:連結，ΐ9: 置，2 〇 · •光罩，2 1 :檢測處理，22 :判定處理，23 判定，2 4 · &, _ •判定處理，2 5 :設計資訊，31製造 3 1 ·【丫 我^斷系統，32:警告裝置，；53:參數調適 ·自我診斷系統，35 :產品率預測系統，36 :產 J 7 ’要求部，3 8 :維護指示畫面，3 9 :缺陷 口口β 4 0 .父貨預測部，4 3 :處理工程，4 4 :檢查 c &旦工程’ 45 :檢查工程，46 :處理工程， 次完成工程，48 : D/S處理工程，51 :製造系統， 化爐控制器’ 53 :氧化膜厚即時模擬器，54 :氧 56 :氧化膜厚計算部，61 :品質推測部，65 :資 66 :推測品質管理部，68 :品質推測部，69 :裝置 之判定 之判定 之判定 度上升 ，12 : 材料間 檢查裝 :現象 系統， 裝置， 品率收 發現報 工程， 47 ··批 52 :氧 化爐， 料庫， 模擬裝 •65· 1280603 (62) 置，7 0 :裝置性能產品率預測部，7 5 :產品率預測處理， 7 7 :測定裝置Ye3 = cX2 + dX3 + eX4 + f ... (2) Device information X2 indicates heater power, device information X3 is the flow of oxygen 02, and device information X4 indicates the atmosphere around the oxidation furnace. In addition, the computer system assigns self-diagnostic parameters to the coefficient "c", the coefficient "d", the coefficient %", and the coefficient "f". Although the oxide film thickness of the wafer is affected by all the parameters, the %' is as shown in Fig. 13, and the oxide film thickness is long before the long-term break (April 13 to April 28 in the figure). The estimated quality of (nm) 値Ye2c is controlled in the range of "98" to "99". The processing device 14a is stopped from the night of April 28 to the morning of May 6, and the estimated quality of the oxide film thickness (nm) after a long period of rest (after May 6 in the figure) is shifted by - γ e 2 η - 57· 1280603 (54) In the range of "96" to "97", the estimated quality of the oxide film thickness 値Ye 2 greatly changed. As shown in Fig. 14, the self-diagnostic device 5a receives the device information of the heater power (W) from the processing device 14a. The heater power 140 before the long-term rest period is 900 W after 500 seconds, 200 W after 600 seconds, and 100 W or less after 650 seconds after the processing device 14a is moved. On the other hand, after a long-term rest, the heater power 141 is 600W after 500 seconds, and after 600 seconds, it is zero W, and after 65 seconds, it rises from zero to 200W, after 75 seconds. It is 150W~3 00W or less, compared with the heater power 140 before the long-term rest, until the 65th second, the heater power drops, and after 700 seconds, the heater power rises, which is different. The processing device 14a monitors the temperature rise of the oxidation furnace. The temperature 142 before the long-term break is raised to 8 〇〇 ° C after 5 60 seconds after the processing device 14a is moved, and rises to 840 ° C after 700 seconds, and moves to 8 4 0 after 800 seconds. ~ 8 5 0 °C range. After the long-term retreat, the temperature 143 rises to 80 after 570 seconds after the processing device 14a is moved (TC, and rises to 830 °C after 700 seconds, and moves to 840-85 after 8 seconds). In the range of 0 °C, the temperature rise curve is lowered as compared with the long-term rest period. The self-diagnostic device 5a is the device information that the processing device 14a receives the heater power of the device information X2 different before and after the long-term rest, so that the temperature can be known. The rise curve changes before and after the long-term break. Therefore, the computer 11 performs the speculative quality comparison process, and compares the film thickness of the wafer 17a after the long-term break measured by the inspection device 19a - 58-1280603 (55)値Yq2, and the estimated quality 値Ye2' of the oxide film thickness of the wafer 17a after the long-term resumption of the self-diagnosis device 5a is not determined. The computer 11 performs element determination processing to make the expression (2) The coefficient "c" is increased, and the number of self-diagnosis # after the long-term break is automatically generated. In the future, the state of the heater in the oxidation furnace before and after the long-term break (for example, several times a year) is grasped in advance. change The reliability of the estimated quality 値Ye2 of the oxide film thickness of the wafer 17a can be improved. The computer 11 is provided with the self-diagnostic device 5a, and the change of the notification formula (2) is set in the database of the self-diagnostic device 5a side. 1 3 a memory new formula (2), also changes the memory device 1 2 memory type (2). In addition, the change notification of '. (2) is processed by mail, by computer 1 1 The e-mail is automatically sent to the person in charge of the process. Thus, by periodically comparing the inspection quality 値Yq2 based on the oxide film thickness of the wafer 1 with the estimated quality 値Ye2 of the oxide film thickness calculated by the self-diagnostic device 5a, it is possible to grasp the long-term. The change in the state of the heater before and after the break (a number of non-frequent operations in a year) can prevent the abnormality of the estimated thickness 値Ye2 of the oxide film thickness of the wafer 1 7 a. However, the embodiment of the present invention is described. The actions and effects of the present invention are not limited to those described in the embodiments of the present invention, and the effects and effects of the present invention are not limited to those described in the embodiments of the present invention. The manufacturing system of the semiconductor device according to the embodiment of the invention and the method of manufacturing the semiconductor device are related to the technical matters. - 59 - 1280603 (56) (a) The manufacturing system of the semiconductor device according to the embodiment of the present invention includes: a processing device for processing processing of a semiconductor substrate, a self-diagnostic system for calculating a speculative quality of the processing process, and an inspection device for inspecting the result of the processing, and comparing the inspection result with the estimated quality, When it is judged that the quality 値 is valid, the parameter of the parameter of the self-diagnosis system is changed when the parameter of the self-diagnosis system is maintained and the estimated quality 値 is determined to be invalid. (b) The computer used in the embodiment of the present invention changes the parameter expression when the estimated quality 値 is determined to be invalid. (c) The computer used in the embodiment of the present invention performs effective determination when the inspection result exists in a reliable region of the regression line formed by the estimated quality 値 and the actual measurement 。. (d) The computer used in the embodiment of the present invention calculates the quality tendency based on the actual measurement of the memory in the past, and compares the inspection result with the quality tendency to determine. (e) The computer used in the embodiment of the present invention is judged based on the inspection result of the oxidation processing process of the semiconductor substrate. (f) The computer used in the embodiment of the present invention is judged based on the inspection result of the etching process of the semiconductor substrate. (g) A method and a method for manufacturing a semiconductor device according to an embodiment of the present invention include: a process for diagnosing a process for processing a semiconductor substrate, and a process for automatically repairing an automatic repair request signal at a stage where a specific condition is satisfied And checking the quality inspection process of the processed semiconductor substrate, and determining the timing of the automatic repair request signal generation based on the quality control data obtained by the quality inspection project-60- 1280603 (57) When the result of the determination is the effective determination, the parameter of the self-diagnosis system is maintained, and when the determination result is invalid, the parameter of the self-diagnosis system is changed, and the automatic inspection frequency correction process of the operation frequency of the quality inspection is changed. (h) In the method of manufacturing a semiconductor device according to the embodiment of the present invention, when the determination result is invalid, the computer adds a parameter of the self-diagnosis system. (i) A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: monitoring a state of a processing device that performs a process for processing a semiconductor substrate, and integrating the device information of the processing device in accordance with a process model to implement semiconductor manufacturing The simulation of the process is presumed to be an instant simulation of the quality of the semiconductor substrate by the process. (j) A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: device information for monitoring a processing device that performs a process for processing a semiconductor substrate, outputting a quality estimation project for estimating quality information of the semiconductor substrate, and outputting processed The quality inspection project of the inspection quality information of the semiconductor substrate, and the comparison of the quality information and the inspection quality information, and the quality of the quality inspection project are judged. When the determination result is invalid, the abnormality detection engineering of the processing device is detected. . (k) A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: device information for monitoring a processing device that performs a process for processing a semiconductor substrate, outputting a quality estimation project for estimating quality information of the semiconductor substrate, and outputting the processed Quality inspection project for inspection quality information of semiconductor substrates, and products for speculative quality information and inspection quality information -61 - 1280603 (58) Predictive quality management engineering for quality related processing, and simulation of semiconductor manufacturing process based on speculative quality information a product rate prediction project for predicting the product rate of a semiconductor device, and a product rate inspection project for at least checking the product rate of the semiconductor device at the end of the wafer process by processing the processing device, and comparing products by the product rate prediction project Rate and product rate related processing engineering by product rate inspection project product rate. (1) A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: a processing process for performing a process for processing a semiconductor substrate, and a quality inspection project for outputting quality information of a semiconductor substrate subjected to a processing process, and a reception. The quality information obtained in the quality inspection project, the semiconductor manufacturing process simulation, the product rate prediction project for predicting the product rate of the semiconductor device, and the processing of the processing device, at least the product rate of the semiconductor device at the end of the wafer engineering Inspect the project, and compare the product rate of the project rate prediction project with the product rate of the product rate inspection project, and improve the product rate-related processing project for predicting the product rate of the product rate prediction project. (m) The method of manufacturing a semiconductor device according to the embodiment of the present invention includes: a processing process for performing a process for processing a semiconductor substrate, and device information for monitoring the processing device, and outputting a quality estimation project for estimating quality information of the semiconductor substrate And the quality inspection project for the quality information of the semiconductor substrate processed by the processing and the quality management project for the quality-related processing of the quality information and quality information, and the semiconductor manufacturing based on the quality information of the quality inspection project. Process simulation, predicting the product rate of semiconductor devices, the first product rate prediction process - 62-1280603 (59), and based on the speculative quality information of the quality management project, implementing the semiconductor manufacturing process with the first product rate prediction project A product rate inspection project that simulates different semiconductor manufacturing process simulations, predicts the product rate of a semiconductor device, and a product rate inspection project that at least checks the product rate of a semiconductor device at the end of a wafer process, and compares 1st product rate forecast The product rate of Cheng Cheng is related to the first product rate of the product rate of the product rate inspection project, and compares the product rate of the project rate by the second product rate and the product rate of the product rate by the product rate inspection project. The rate-related processing project, and the predicted product rate comparison project for improving the product rate prediction accuracy of the first and second product rate prediction projects based on the correlation results of the first and second product rate related processing projects. (n) A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: detecting a state in which a state of a processing device that performs a process for processing a semiconductor substrate is detected, and extracting the uncontrolled enthalpy of the process from the detection 値Obtaining the feature quantization project of the feature quantity, and comparing the feature quantity obtained by the feature quantization engineering and the defect image of the inherent defect image by the range classification, and the feature quantity in the related table previously memorized is When the feature quantity of each other is judged to be the same level, the semiconductor manufacturing process is interrupted, and the semiconductor substrate is notified as a defective batch, and the quality inspection project is notified. Further, the method of manufacturing a semiconductor device according to the embodiment of the present invention further includes: when the defective batch having a new feature amount that cannot be equal to the feature amount in the related table is detected, The process history information of the batch is extracted, and the device information indicating the state of the processing device - 63 - 1280603 (60) when the defective batch is generated is extracted, and the device information of the processing device is automatically fed back to the quality estimation project of the quality estimation unit. . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a model system diagram of a manufacturing system of a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a model flow chart for explaining a method of manufacturing a semiconductor device according to the first and second embodiments of the present invention. Fig. 3 is a schematic block diagram showing a manufacturing system of a semiconductor device according to a third embodiment of the present invention. Fig. 4 is a flow chart showing a model of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. Fig. 5 is a model flow chart for explaining a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. Fig. 6 is a view showing a method of defining a manufacturing apparatus for causing a defective batch of the semiconductor device according to the sixth embodiment of the present invention. Fig. 7 is a flow chart showing a model of a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention. Fig. 8 is a system diagram showing a manufacturing system of a semiconductor device according to an eighth embodiment of the present invention. Figure 9 is a flow chart showing a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention. Fig. 10 is a cross-sectional view showing a semiconductor device used in an eighth embodiment of the present invention. -64 - l28〇6〇3 (61) The figure shows the method_ used in the eighth embodiment of the present invention. Fig. 1 is a view showing the method used in the eighth embodiment of the present invention. - 〜 a ® illustrates the method used in the eighth embodiment of the present invention. 4 is a temperature curve _ used in the eighth embodiment of the present invention. [Description of Symbols of Main Units] — 5a: Self-diagnostic device, 10: Manufacturing system, 11: Computer memory device _ _ 1 3 · Database, 1 4: Processing device, 1 5 : Direct material, ; < .βθ 'Gate' 17: Wafer, 18: Link, ΐ9: Set, 2 〇· • Photomask, 2 1 : Detection processing, 22: Judgment processing, 23 judgment, 2 4 · &, _ • Judgment processing, 2 5 : Design Information, 31 Manufacturing 3 1 · [丫我^断系统,32: Warning device,; 53: Parameter adjustment and self-diagnosis system, 35: Product rate prediction system, 36: Production J 7 'Requirement Department, 3 8 : Maintenance instruction screen, 3 9 : Defective mouth β 4 0 . Parent forecasting department, 4 3 : Processing engineering, 4 4 : Checking c & Dan engineering ' 45 : Inspection engineering, 46 : Processing engineering, finishing engineering, 48 : D/S processing project, 51: Manufacturing system, furnace controller '53: oxide film thickness instant simulator, 54: oxygen 56: oxide film thickness calculation unit, 61: quality estimation unit, 65: capital 66: speculation quality Management Department, 68: Quality Estimation Unit, 69: The degree of judgment of the judgment of the device is increased, 12: Inspection between materials: Phenomenon system, Set, rate collection and discovery project, 47 ·· batch 52: oxidation furnace, material storage, simulation equipment • 65· 1280603 (62), 7 0: device performance product rate prediction department, 7 5: product rate prediction processing, 7 7 : Measuring device

• 66 -• 66 -

Claims (1)

I2SQ6Q3 I n 乂二二二.：： I i： 十、申請專利範圍 第93 1 265 3 6號專利申請案 中文申請專利範圍修正本 民國95年8月2 日修正 1· 一種半導體裝置的製造系統，其特徵爲具備： 實行半導體基板之製程處理之處理裝置，及 控制前述處理裝置之處理控制裝置，及 使前述半導體基板之製程處理進行，監控前述處理裝 置之狀態，積分前述處理裝置的內部資訊，實行前述製程 處理之模擬，推測藉由前述製程處理，前述半導體基板之 處理的進行之即時模擬器。 2 ·如申請專利範圍第1項所記載之半導體裝置的製 造系統，其中，前述即時模擬器係由從前述處理控制裝置 所送訊之處理停止訊號的收到時間點起，積分前述內部資 訊，實行前述製程處理之模擬。 3 ·如申請專利範圍第1項所記載之半導體裝置的製 造系統，其中，前述即時模擬器係實行前述半導體基板之 氧化處理之模擬，推測藉由前述製程處理，前述半導體基 板之處理的進行。 4 ·如申請專利範圍第1項所記載之半導體裝置的製 造系統，其中，前述即時模擬器係實行前述半導體基板之 蝕刻處理的模擬，推測藉由前述製程處理，前述半導體基 板之處理的進行。 5 ·如申請專利範圍第1項所記載之半導體裝置的製 12806瓜 f.I2SQ6Q3 I n 乂二二二.:: I i: X. Patent Application No. 93 1 265 3 No. 6 Patent Application Revision of Chinese Patent Application Revision of the Republic of China on August 2, 1995 Revision 1 · Manufacturing System for Semiconductor Devices A processing device for performing a process for processing a semiconductor substrate, a process control device for controlling the processing device, and a process for processing the semiconductor substrate, monitoring a state of the processing device, and integrating internal information of the processing device The simulation of the above-described process processing is carried out, and an instant simulator for performing the processing of the semiconductor substrate by the above-described process processing is presumed. The manufacturing system of the semiconductor device according to the first aspect of the invention, wherein the instant simulator integrates the internal information from a time point of receipt of a processing stop signal transmitted from the processing control device. Perform the simulation of the aforementioned process processing. The manufacturing system of the semiconductor device according to the first aspect of the invention, wherein the instant simulator performs the simulation of the oxidation treatment of the semiconductor substrate, and it is presumed that the processing of the semiconductor substrate is performed by the process. The manufacturing system of the semiconductor device according to the first aspect of the invention, wherein the instant simulator performs the simulation of the etching process of the semiconductor substrate, and it is presumed that the processing of the semiconductor substrate is performed by the process. 5 · The system of the semiconductor device as described in the first paragraph of the patent application 12806 melon f. 造系統’其中’前述即時模擬器係監控前述半導體基板之 端點，推測前述半導體基板之處理的進行。 6 ·如申請專利範圍第1項所記載之半導體裝置的製 造系統，其中，前述處理控制裝置係由與前述即時模擬器 不同之電腦，收訊前述製程處理之開始指令，對於前述處 理裝置，送訊處理開始訊號及處理停止訊號。 7 ·如申請專利範圍第6項所記載之半導體裝置的製 造系統，其中，前述即時模擬器係將推測前述半導體基板 之處理的進行之結果送訊給前述電腦。 8 · —種半導體裝置的製造系統，其特徵爲具備： 實行使用半導體基板之製程處理之處理裝置，及 由前述處理裝置收訊裝置資訊，使用推定前述製程處 理之進行的即時模擬來計算出前述製程處理之推測品質値 之自我診斷系統，及 檢查前述製程處理之結果之檢查裝置，及 比較前述檢查結果與前述推測品質値，在前述推測品 質値判定爲有效時，維持前述自我診斷系統之參數，在前 述推測品質値判定爲無效時，變更前述自我診斷系統之參 數之電腦。 9. 一種半導體裝置的製造系統，其特徵爲具備： 實行使用半導體基板之製程處理之處理裝置，及由前 述處理裝置收訊裝置資訊’使用推定前述製程處理之進行 的即時模擬器來進行前述處理裝置之自我管理之自我診斷 系統，及檢查前述製程處理之結果之檢查裝置，及依據前 -2 - 1280603The above-mentioned instant simulator monitors the end points of the semiconductor substrate, and presumes the progress of the processing of the semiconductor substrate. The manufacturing system of the semiconductor device according to the first aspect of the invention, wherein the processing control device receives a start command of the process control by a computer different from the instant simulator, and sends the start command to the processing device. The processing starts the signal and processes the stop signal. The manufacturing system of the semiconductor device according to the sixth aspect of the invention, wherein the instant simulator transmits a result of presuming processing of the semiconductor substrate to the computer. 8. A manufacturing system for a semiconductor device, comprising: a processing device that performs a process for processing a semiconductor substrate, and a device for receiving the device by the processing device, and calculating the foregoing using an instantaneous simulation performed by estimating the process The self-diagnosis system for estimating the quality of the process, and the inspection device for inspecting the results of the process, and comparing the inspection result with the estimated quality 値, maintaining the parameters of the self-diagnosis system when the estimated quality 値 is determined to be valid When the presumed quality 値 is determined to be invalid, the computer that changes the parameters of the self-diagnosis system is used. A manufacturing system for a semiconductor device, comprising: a processing device that performs a process for processing a semiconductor substrate; and an instant simulator that uses the process device for estimating the process to perform the process described above The self-management self-diagnosis system of the device, and the inspection device for checking the results of the aforementioned process processing, and the basis of the previous-2 - 1280603 述檢查結果’判定是否自動修復前述處理裝置，在判定結 果爲有效判定時，維持前述自我診斷系統之參數，在判定 結果爲無效判定時’變更前述自我診斷系統之參數之電 腦。 10· —種半導體裝置的製造系統，其特徵爲具備： 貫行半導體基板之製程處理之處理裝置，及依據自我 診斷參數而使用推定前述製程處理之進行的即時模擬器來 g多斷處理裝置之自我診斷裝置’及檢查製程處理之檢查裝 置’及連接於自我診斷裝置及檢查裝置，在半導體基板之 檢查結果爲有效時.，維持自我診斷參數，在檢查結果爲無 效時，變更自我診斷參數之電腦。 11· 一種半導體裝置的製造系統，其特徵爲：具備 有， 實行半導體基板之製程處理之處理裝置，及 取得處理裝置之裝置資訊，使用推定前述製程處理之 進行的即時模擬器而輸出半導體基板之推測品質資訊之品 質推測部，及 輸出經過處理之半導體基板的品質資訊之品質檢查裝 置，及 實行推測品質資訊與品質資訊之品質相關處理之推測 品質管理部，及 依據由推測品質管理部所輸出之推測品質資訊’實行 模擬，預測半導體裝置之產品率之產品率預測裝置’及 經過處理裝置之處理，至少檢查晶圓工程結束之半導 -3-The inspection result is determined to determine whether or not the processing device is automatically repaired. When the determination result is valid, the parameters of the self-diagnosis system are maintained, and when the determination result is invalid, the computer that changes the parameters of the self-diagnosis system is changed. 10. A manufacturing system for a semiconductor device, comprising: a processing device for processing a semiconductor substrate; and an instant simulator for estimating the process according to the self-diagnosis parameter; The self-diagnostic device 'and the inspection device for checking the process processing' and the self-diagnostic device and the inspection device are connected to the self-diagnostic device and the inspection device to maintain the self-diagnosis parameter when the inspection result of the semiconductor substrate is valid, and to change the self-diagnosis parameter when the inspection result is invalid. computer. A manufacturing system for a semiconductor device, comprising: a processing device for performing a process for processing a semiconductor substrate; and device information for acquiring the processing device, and outputting a semiconductor substrate using an instant simulator that estimates the process processing a quality estimation unit for estimating quality information, a quality inspection device for outputting quality information of the processed semiconductor substrate, and a speculative quality management unit for performing quality-related processing for estimating quality information and quality information, and outputted by the estimated quality management unit Speculative quality information 'Performance simulation, product rate prediction device for predicting the product rate of semiconductor devices' and processing by processing device, at least check the semi-conducting end of wafer engineering -3- 體裝置的產品率之產品率檢查裝置； 實行產品率相關處理來比較產品率預測裝置之產品率 及產品率檢查裝置之產品率。 12. —種半導體裝置的製造系統，其特徵爲：具備 有， 實行半導體基板之製程處理之處理裝置，及 監控處理裝置之裝置資訊，使用推定前述製程處理之 進行的即時模擬器而輸出半導體基板之推測品質資訊之品 質推測部，及 輸出經過處理之半導體基板之品質資訊之品質檢查裝 置，及 實行推測品質資訊與品質資訊之品質相關處理之推測 品質管理部，及 實行依據來自品質檢查裝置之品質資訊的模擬，預測 半導體裝置之產品率之第1產品率預測裝置，及 依據來自推測品質管理部之推測品質資訊，實行與第 1產品率預測裝置的模擬不同之另外的模擬，預測半導體 裝置之產品率之第2產品率預測裝置，及 經過半導體製造製程，至少檢查晶圓工程結束之半導 體裝置的產品率之產品率檢查裝置； 實行第1產品率相關處理來比較第1產品率預測裝置 的產品率及產品率檢查裝置的產品率，及實行第2產品率 相關處理來比較第2產品率預測裝置的產品率及產品率檢 查裝置之產品率。 -4- 1280603 13· —種半導體裝置的製造系統，其特徵爲具備： 實行半導體基板之製程處理之處理裝置，及 比較：檢測處理裝置之裝置資訊並使用推定前述製程 處理之進行的即時模擬器而由檢測値中抽出處理之非控制 値再予以特徵量化而成之特徵量，及藉由範圍分類將固有 之缺陷影像予以數値化並預先加以記憶之相關表內之特徵 量；在判定爲該特徵量化而成之特徵量是可與該相關表內 之特徵量鑑別化之値的階段，中斷處理，將半導體基板當 成不良批次而進行通知之品質檢知部。 14. 一種半導體裝置的製造系統，其特徵爲具備： 實行半導體基板之製程處理的處理裝置，及 比較：檢測出處理裝置的裝置資訊，推定前述製程處 理之進行的即時模擬器來從檢測値中抽出處理之非控制 値，然後加以特徵量化而成的特徵量，和藉由範圍分類而 將固有之缺陷影像予以數値化並預先加以記憶之相關表內 之特徵量；當檢測到有無法鑑別之新的特徵量的不良批次 時，依據該不良批次之製程履歷資訊，抽出顯示該半導體 基板之不良批次產生時之處理裝置的狀態之裝置資訊，將 該裝置資訊自動地反饋給品質推測部之推測品質自動更新 手段。 15. —種半導體裝置的製造方法，其特徵爲： 藉由處理裝置，實行半導體基板之製程處理， 使前述半導體基板之製程處理進行，監控前述處理裝 置之狀態，積分前述處理裝置之內部資訊，實行前述製程 -5- 1280603 . _^一一、 如％?帘一曰修_^管设叫 ..................... — 一 處理之模擬，推測藉由前述製程處理，前述半導體基板之 處理的進行。 1 6 ·如申請專利範圍第1 5項所記載之半導體裝置的 _造方法，其中，前述製程處理係前述半導體基板之氧化 處理製程。The product rate inspection device of the product rate of the body device; the product rate related process is implemented to compare the product rate of the product rate prediction device and the product rate of the product rate inspection device. 12. A manufacturing system for a semiconductor device, comprising: a processing device for performing a process for processing a semiconductor substrate; and device information for monitoring the processing device, and outputting a semiconductor substrate using an instant simulator that estimates the process processing a quality estimation unit for estimating quality information, a quality inspection device for outputting quality information of the processed semiconductor substrate, and a speculative quality management unit for performing quality-related processing for estimating quality information and quality information, and implementing the quality inspection device The simulation of the quality information, the first product rate prediction device for predicting the product rate of the semiconductor device, and the simulation of the first product rate prediction device based on the estimated quality information from the estimated quality management unit, and the prediction of the semiconductor device The second product rate prediction device of the product rate, and the product rate inspection device that checks the product rate of the semiconductor device at the end of the wafer process through the semiconductor manufacturing process; and the first product rate correlation process is performed to compare the first product rate prediction device The product Products and products of the testing device, and the implementation of the second process related to the rate of product Comparative product 2 Product Rate Prediction product rate of the apparatus and products of the inspection apparatus. -4- 1280603 A manufacturing system for a semiconductor device, comprising: a processing device for performing a process for processing a semiconductor substrate; and comparing: detecting device information of the processing device and using an instant simulator for estimating the process And the feature quantity obtained by the non-control 抽 extracted from the detection 値 and then quantized by the feature, and the feature quantity in the related table which is quantized and pre-memorized by the range classification; The feature quantity quantized by the feature is a stage in which the feature quantity in the correlation table can be distinguished, and the quality detection unit that notifies the semiconductor substrate as a defective batch is interrupted. A manufacturing system for a semiconductor device, comprising: processing means for performing a process of processing a semiconductor substrate; and comparing: detecting device information of the processing device, and estimating an instant simulator for performing the process processing from the detection Extracting the non-control 値 of the processing, and then extracting the feature quantity obtained by the feature, and the feature quantity in the related table by counting the inherent defect image by the range classification and pre-memorizing; when it is detected that it is impossible to identify In the case of a new defective batch of the feature quantity, the device information indicating the state of the processing device at the time of occurrence of the defective batch of the semiconductor substrate is extracted based on the process history information of the defective batch, and the device information is automatically fed back to the quality. The speculative quality automatic update means of the speculation unit. A method of manufacturing a semiconductor device, comprising: performing a process of processing a semiconductor substrate by a processing device, performing a process of processing the semiconductor substrate, monitoring a state of the processing device, and integrating internal information of the processing device; Carry out the aforementioned process -5 - 1280603. _ ^ one, such as %? curtain one repair _ ^ pipe set called ..................... - a treatment In the simulation, it is estimated that the processing of the semiconductor substrate is progressed by the above-described process. The method of manufacturing a semiconductor device according to the invention, wherein the process is an oxidation process of the semiconductor substrate. 1 7 ·如申請專利範圍第1 5項所記載之半導體裝置的 _ ^方法，其中，前述製程處理係前述半導體基板之蝕刻 處理製程。 1 8 ·如申請專利範圍第1 5項所記載之半導體裝置的 製造方法，其中，前述製程處理之模擬係由從前述處理控 制裝置所送訊之處理停止訊號之收到時間點起，積分前述 內部資訊。The method of the semiconductor device according to claim 15 wherein the process is an etching process of the semiconductor substrate. The method of manufacturing a semiconductor device according to the above aspect of the invention, wherein the simulation of the process processing is performed by integrating a time period from the reception of a processing stop signal sent by the processing control device Internal information. 1 9 ·如申請專利範圍第1 5項所記載之半導體裝置的 製造方法，其中，前述模擬係監控前述半導體基板之端點 的出現’積分前述處理裝置的內部資訊，推測前述半導體 基板之處理的進行。 2 0 ·如申請專利範圍第1 5項所記載之半導體裝置的 製造方法，其中，前述半導體基板之處理係蝕刻工程。The method for manufacturing a semiconductor device according to the above aspect of the invention, wherein the simulation system monitors an occurrence of an end point of the semiconductor substrate to integrate the internal information of the processing device, and estimates the processing of the semiconductor substrate. get on. The method of manufacturing a semiconductor device according to the above aspect of the invention, wherein the processing of the semiconductor substrate is an etching process.
TW093126536A 2003-09-08 2004-09-02 Manufacturing system of semiconductor device and manufacturing method of semiconductor device TWI280603B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003355684 2003-09-08

Publications (2)

Publication Number Publication Date
TW200512794A TW200512794A (en) 2005-04-01
TWI280603B true TWI280603B (en) 2007-05-01

Family

ID=34674780

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093126536A TWI280603B (en) 2003-09-08 2004-09-02 Manufacturing system of semiconductor device and manufacturing method of semiconductor device

Country Status (3)

Country Link
KR (1) KR100733590B1 (en)
CN (2) CN1595607A (en)
TW (1) TWI280603B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10001774B2 (en) 2013-03-22 2018-06-19 Kabushiki Kaisha Toshiba Manufacturing supporting system, manufacturing supporting method, and manufacturing supporting program for electronic device

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7289863B2 (en) * 2005-08-18 2007-10-30 Brooks Automation, Inc. System and method for electronic diagnostics of a process vacuum environment
US9418413B1 (en) 2009-07-06 2016-08-16 Camtek Ltd. System and a method for automatic recipe validation and selection
TWI497623B (en) * 2009-07-06 2015-08-21 Camtek Ltd A system and a method for automatic recipe validation and selection
JP5572194B2 (en) * 2012-09-21 2014-08-13 株式会社東芝 Manufacturing management system, manufacturing management method, and manufacturing management program
US20140303912A1 (en) * 2013-04-07 2014-10-09 Kla-Tencor Corporation System and method for the automatic determination of critical parametric electrical test parameters for inline yield monitoring
CN103346105B (en) * 2013-06-27 2015-09-30 上海华力微电子有限公司 A kind of can according to the defect sampling observation method of technique wafer number load dynamic conditioning
CN103336518B (en) * 2013-07-08 2016-03-30 上海华力微电子有限公司 The method of metric data is obtained from external auxiliary analytic system
CN106486391B (en) * 2015-08-31 2020-08-07 北大方正集团有限公司 Semiconductor manufacturing control method and system based on MES system
KR102525873B1 (en) * 2015-10-16 2023-04-27 삼성전자주식회사 Semiconductor process simulation device and simulation method thereof
US10310490B2 (en) * 2016-02-01 2019-06-04 Qoniac Gmbh Method and apparatus of evaluating a semiconductor manufacturing process
CN113642819A (en) * 2020-05-11 2021-11-12 上海华力集成电路制造有限公司 Automatic scheduling device and method for products in abnormal stations in interlinked allowable time zones
JP6983966B1 (en) * 2020-09-16 2021-12-17 株式会社東芝 Thickness measuring device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5076205A (en) * 1989-01-06 1991-12-31 General Signal Corporation Modular vapor processor system
US5711843A (en) * 1995-02-21 1998-01-27 Orincon Technologies, Inc. System for indirectly monitoring and controlling a process with particular application to plasma processes
US5910011A (en) * 1997-05-12 1999-06-08 Applied Materials, Inc. Method and apparatus for monitoring processes using multiple parameters of a semiconductor wafer processing system
KR100216066B1 (en) * 1997-05-20 1999-08-16 윤종용 Control system and control method for ic test process
US6763130B1 (en) 1999-07-21 2004-07-13 Applied Materials, Inc. Real time defect source identification
JP4409744B2 (en) 2000-10-20 2010-02-03 ライトロン株式会社 Etching process progress display method and etching process monitoring apparatus
JP4213871B2 (en) 2001-02-01 2009-01-21 株式会社日立製作所 Manufacturing method of semiconductor device
JP3993396B2 (en) * 2001-03-30 2007-10-17 株式会社東芝 Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10001774B2 (en) 2013-03-22 2018-06-19 Kabushiki Kaisha Toshiba Manufacturing supporting system, manufacturing supporting method, and manufacturing supporting program for electronic device

Also Published As

Publication number Publication date
CN101937836A (en) 2011-01-05
CN1595607A (en) 2005-03-16
KR100733590B1 (en) 2007-06-28
CN101937836B (en) 2012-08-08
TW200512794A (en) 2005-04-01
KR20050025936A (en) 2005-03-14

Similar Documents

Publication Publication Date Title
JP4008899B2 (en) Semiconductor device manufacturing system and semiconductor device manufacturing method
JP5020101B2 (en) Defect detection and classification (FDC) using lanturan controllers
JP4771696B2 (en) Method and system for predicting electrical characteristics of semiconductor devices during manufacture
JP5102488B2 (en) Method for fault detection in manufacturing equipment
JP5095999B2 (en) A system and method using a first principle simulation for analyzing a process performed by a semiconductor processing tool.
TWI280603B (en) Manufacturing system of semiconductor device and manufacturing method of semiconductor device
JP4795957B2 (en) A system and method using a first principle simulation for controlling a semiconductor manufacturing process.
JP4568216B2 (en) Semiconductor device manufacturing system
JP5032118B2 (en) A system and method using a first principle simulation in a semiconductor manufacturing process.
TWI412906B (en) Manufacturing execution system with virtual-metrology capabilities and manufacturing system including the same
US7580767B2 (en) Methods of and apparatuses for maintenance, diagnosis, and optimization of processes
JP4693464B2 (en) Quality control system, quality control method and lot-by-lot wafer processing method
US20060129257A1 (en) Novel method and apparatus for integrating fault detection and real-time virtual metrology in an advanced process control framework
CN112652556A (en) Processing apparatus, apparatus management controller, processing system, recording medium, method for manufacturing semiconductor device, and display method
JP2008004641A (en) Defect detection system, defect detection method, and program
TW200307972A (en) Correlation of end-of-line data mining with process tool data mining
JP7149428B2 (en) Semiconductor device manufacturing system and semiconductor device manufacturing method
US6563300B1 (en) Method and apparatus for fault detection using multiple tool error signals
US20120016643A1 (en) Virtual measuring system and method for predicting the quality of thin film transistor liquid crystal display processes
TWI708197B (en) Predictive maintenance method for component of production tool and computer program product thereof
Chien et al. A novel approach to hedge and compensate the critical dimension variation of the developed-and-etched circuit patterns for yield enhancement in semiconductor manufacturing
KR20220092795A (en) Information processing apparatus, information processing system, and part ordering method
US6821792B1 (en) Method and apparatus for determining a sampling plan based on process and equipment state information
JP2006505130A (en) Method and apparatus for providing first-principles feedforward manufacturing control
US6697696B1 (en) Fault detection control system using dual bus architecture, and methods of using same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees